An embodiment of a semiconductor device includes a semiconductor substrate, a first dielectric layer, a first current-carrying electrode, and a second current-carrying electrode formed over the semiconductor substrate. A control electrode is formed over the semiconductor substrate and disposed between the first current-carrying electrode and the second current-carrying electrode. A conductive element formed over the first dielectric layer, adjacent the control electrode, and between the control electrode and the second current-carrying electrode, includes a first region formed a first distance from the upper surface of the semiconductor substrate and a second region formed a second distance from the upper surface of the semiconductor substrate. An insulating region is formed between the control electrode and the conductive element.

A method of forming a film can include heating a CVD reactor chamber containing a substrate to a temperature range between about 750 degrees Centigrade and about 950 degrees Centigrade, providing a first precursor comprising Al to the CVD reactor chamber in the temperature range, providing a second precursor comprising Sc to the CVD reactor chamber in the temperature range, providing a third precursor comprising nitrogen to the CVD reactor chamber in the temperature range, and forming the film comprising ScAlN on the substrate.

A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a barrier layer on the buffer layer; forming a hard mask on the barrier layer; performing an implantation process through the hard mask to form a doped region in the barrier layer and the buffer layer; removing the hard mask and the barrier layer to form a first trench; forming a gate dielectric layer on the hard mask and into the first trench; forming a gate electrode on the gate dielectric layer; and forming a source electrode and a drain electrode adjacent to two sides of the gate electrode.

A high electron mobility transistor (HEMT) includes a semiconductor channel layer, a semiconductor barrier layer, a patterned semiconductor capping layer, and a patterned semiconductor protection layer disposed on a substrate in sequence. The HEMT further includes an interlayer dielectric layer and a gate electrode. The interlayer dielectric layer covers the patterned semiconductor capping layer and the patterned semiconductor protection layer, and includes a gate contact hole. The gate electrode is disposed in the gate contact hole and electrically coupled to the patterned semiconductor capping layer, where the patterned semiconductor protection layer is disposed between the gate electrode and the patterned semiconductor capping layer. The resistivity of the patterned semiconductor protection layer is between the resistivity of the patterned semiconductor capping layer and the resistivity of the interlayer dielectric layer.

A semiconductor device includes a III-V compound semiconductor layer, a III-V compound barrier layer, a gate trench, a p-type doped III-V compound layer, an insulation layer, and a gate electrode. The III-V compound barrier layer is disposed on the III-V compound semiconductor layer. The gate trench is disposed in the III-V compound barrier layer. The p-type doped III-V compound layer is disposed in the gate trench, and a top surface of the p-type doped III-V compound layer and a top surface of the III-V compound barrier layer are substantially coplanar. The insulation layer is disposed on the III-V compound barrier layer. The insulation layer includes an opening located corresponding to the gate trench in a vertical direction. A part of the p-type doped III-V compound layer is disposed on the insulation layer in the vertical direction. The gate electrode is disposed on the p-type doped III-V compound layer.

A semiconductor device for power amplification includes a substrate, a lower electrode, a semiconductor layer, a source electrode, a drain electrode, a gate electrode, and a field plate. The semiconductor layer is divided into an active region and an isolation region. In a plan view, a channel region includes unit channel regions that are separated by the isolation region and arranged in a Y-axis direction. The source electrode includes unit source electrodes each of which faces a corresponding one of the unit channel regions. The field plate includes unit plates each of which faces a corresponding one of the unit channel regions. At least one of plate drive lines is provided, for each of the unit plates, within the isolation region, the plate drive lines extending in an X-axis direction and electrically connecting the unit source electrodes and the unit plates.

A nitride semiconductor device includes: an electron transit layer; an electron supply layer that is formed on the electron transit layer and that has a band gap which is larger than that of the electron transit layer; a dielectric layer that is formed on the electron supply layer; and an electrode that has a contact part which is in electrical contact with the electron supply layer via at least an opening passing through the dielectric layer. The contact part has: an inclined surface that is inclined so as to decrease in width toward the electron transit layer; a tip surface that is in contact with the bottom face of the opening; and a curved surface that is provided between the tip surface and the inclined surface and that is curved so as to protrude toward the electron transit layer.

A semiconductor device for power amplification includes a lower electrode, a semiconductor layer, a source electrode, a drain electrode, and a gate electrode. The semiconductor layer is divided into an active region and an isolation region. A channel region includes unit channel regions that are separated by the isolation region. The source electrode includes unit source electrodes each of which faces a corresponding one of the unit channel regions. Unit source regions each include at least one source via that contains a conductor in contact with the lower electrode, the unit source regions each including a corresponding one of the unit source electrodes. In a plan view, a length of a side of a minimum rectangular region in an X-axis direction is greater than a length of a side of the minimum rectangular region in the Y-axis direction, the minimum rectangular region surrounding the at least one source via.

A power amplifier semiconductor device includes: a substrate; a semiconductor layer provided on the surface of the substrate and including a plurality of unit HEMTs; a connection layer provided on the semiconductor layer and including a source electrode, a drain electrode, and a gate electrode of each of the plurality of unit HEMTs; a terminal layer provided on the connection layer; a back electrode which is provided on the bottom surface of the substrate and whose potential is set to a source potential; and substrate vias that pass through the substrate and have a shield wiring layer on inner walls of the substrate vias. In plan view, either one of the drain aggregation portion or the gate aggregation portion is or both of the drain aggregation portion and the gate aggregation portion are each surrounded by the substrate vias.

Structures for a high-electron-mobility transistor and methods of forming such structures. The structure comprises a device structure including a gate and an ohmic contact, and one or more inactive blocks laterally positioned between the gate and the ohmic contact.