Provided is a semiconductor device and method of manufacturing same, the semiconductor device including: a plurality of active patterns on a substrate; a source/drain pattern on the substrate; a power rail in the substrate; a pillar pattern between the plurality of active patterns; a channel pattern on the pillar pattern; a backside conductive contact between the source/drain pattern and the power rail; and a liner pattern on the pillar pattern, wherein the liner pattern includes: a first portion that covers a top surface of a lower portion of the backside conductive contact; and a second portion that extends from the first portion and along a sidewall of the lower portion of the backside conductive contact.

A semiconductor device includes a substrate, and an interconnection layer on the substrate. The interconnection layer includes an interconnection structure having a first interconnection line therein that includes a metal alloy containing a single phase of ruthenium and a non-ruthenium first element having a concentration in a range from greater than 0 at % to 40 at % in the metal alloy. In the event the first element is molybdenum, the concentration of the first element in the metal alloy may range from 0.1 at % to 30 at %; but, in the event the first element is tungsten, the concentration of the first element in the metal alloy may range from 0.1 at % to 40 at %.

A semiconductor device includes a first fin pattern extending in a first direction, source/drain patterns on the first fin pattern, a gate electrode extending in a second direction, an insulating structure in contact with the first fin pattern, a lower conductive pattern and an upper conductive pattern overlapping the insulating structure in a third direction, and a connection contact extending through the insulating structure and electrically connecting the lower conductive pattern and the upper conductive pattern. The first fin pattern includes a first fin portion, a second fin portion spaced apart from the first fin portion, and a third fin portion between the first fin portion and the second fin portion. A width in the second direction of the first fin portion and a width in the second direction of the second fin portion are greater than a width in the second direction of the third fin portion.

A semiconductor device may include a channel pattern on a substrate, a source/drain pattern electrically connected to the channel pattern, a gate electrode on the channel pattern, an interlayer insulating layer on the source/drain pattern, and an active contact that extends into the interlayer insulating layer and is electrically connected to the source/drain pattern. The active contact may include a lower active contact, which includes a barrier pattern and a lower metal pattern on the barrier pattern, and an upper active contact on the lower active contact. The upper active contact may include an upper metal pattern and an insulating pattern on side surfaces of the upper metal pattern. The lower metal pattern and the upper metal pattern may be in contact with each other.

Provided is a semiconductor device including a first active pattern and a second active pattern on a substrate, a first source/drain pattern and a first channel pattern on the first active pattern, a second source/drain pattern and a second channel pattern on the second active pattern, and a gate electrode crossing each of the first channel pattern and the second channel pattern. Along a horizontal extension direction of the gate electrode, a first width of an upper surface of the first channel pattern is greater than a second width of an upper surface of the second channel pattern, and an upper surface of the first source/drain pattern is located at a vertically higher level than the upper surface of the first channel pattern.

A semiconductor device includes an active pattern extending on a substrate in a first direction, channel patterns vertically stacked on the active pattern, a separation structure extending in a second direction and separating each of the active pattern and the channel patterns into first and second portions, a gate structure extending in the second direction and onto the first portions of the channel patterns, a separation pattern extending in the first direction, separating the first portions of the channel patterns into first and second channel patterns, and separating the gate structure into first and second gate structures, and a third gate structure extending in the second direction and onto the second portions of the channel patterns. The second portions of the channel patterns have a width greater than a sum of first and second widths of the first and second channel patterns, respectively.

An integrated circuit device includes a stacked transistor structure on a substrate. The stacked transistor structure includes a first transistor and a second transistor stacked on the first transistor. Each of the first and second transistors includes a plurality of channel patterns that extend between source/drain regions in a first direction and are alternately stacked with gate patterns in a second direction. For at least one of the first and second transistors, respective lengths of the channel patterns, the gate patterns, and/or inner spacers at opposing ends of the gate patterns differ along the first direction. Related devices and fabrication methods are also discussed.

A semiconductor device may include a first fin pattern, a first source/drain pattern on the first fin pattern, a second fin pattern spaced apart in a first direction from the first fin pattern, a second source/drain pattern on the second fin pattern, a first gate electrode overlapping the first fin pattern and extending in a second direction crossing the first direction, a second gate electrode overlapping the second fin pattern and extending in the second direction, and a first dummy structure between the first fin pattern and the second fin pattern and between the first gate electrode and the second gate electrode. The first dummy structure may include first to third line parts extending in the second direction, first and second connection parts connecting the first and second line parts to each other, and a third connection part connecting the second and third line parts to each other.

A semiconductor device includes a substrate including an active region extending in a first direction, gate structures extending in a second direction overlapping the active region, on the substrate, and spaced apart from each other in the first direction, a blocking gate structure overlapping the active region, between the gate structures, and extending in the second direction, source/drain regions disposed in a region in which the active region is recessed, on both sides of the blocking gate structure, a backside contact structure disposed below at least one of the source/drain regions, and backside blocking structures disposed below the gate structures and the blocking gate structure, respectively. The blocking gate structure includes a first element different from the gate structures.

A semiconductor device includes active patterns spaced apart from one another in a first direction and extending in a second direction different from the first direction; a lower channel pattern and a lower source/drain pattern on the active patterns, in which the lower channel pattern and the lower source/drain pattern are alternately arranged in the second direction; an upper channel pattern on the lower channel pattern, and an upper source/drain pattern on the lower source/drain pattern; a gate pattern on the active patterns and on the lower channel pattern and the upper channel pattern; and a gate inner spacer on the gate pattern, and between the lower source/drain pattern and the upper source/drain pattern.