An integrated circuit device according to the inventive concept includes: a fin-type active area protruding from a substrate and extending in a first horizontal direction; a stopper layer that is above and spaced apart from the fin-type active area; a gate electrode extending in a second horizontal direction orthogonal to the first horizontal direction, on the fin-type active area, and in a space between the fin-type active area and the stopper layer; and a gate capping layer on upper surfaces of the gate electrode and the stopper layer.

Improved methods for forming gate isolation structures between portions of gate electrodes and semiconductor devices formed by the same are disclosed. In an embodiment, a method includes forming a channel structure over a substrate; forming a first isolation structure extending in a direction parallel to the channel structure; forming a dummy gate structure over the channel structure and the first isolation structure; depositing a hard mask layer over the dummy gate structure; etching the hard mask layer to form a first opening through the hard mask layer over the first isolation structure; conformally depositing a first dielectric layer over the hard mask layer, in the first opening, and over the dummy gate structure; etching the first dielectric layer to extend the first opening and expose the dummy gate structure; and etching the dummy gate structure to extend the first opening and expose the first isolation structure.

A method of manufacturing an interconnect structure includes forming an opening through a dielectric layer. The opening exposes a top surface of a first conductive feature. The method further includes forming a barrier layer on sidewalls of the opening, passivating the exposed top surface of the first conductive feature with a treatment process, forming a liner layer over the barrier layer, and filling the opening with a conductive material. The liner layer may include ruthenium.

A method for fabricating a semiconductor device includes the steps of first forming a gate dielectric layer on a substrate, forming a gate material layer on the gate dielectric layer, patterning the gate material layer and the gate dielectric layer to form a gate structure, removing a portion of the gate dielectric layer, forming a spacer adjacent to the gate structure and at the same time forming an air gap between the gate dielectric layer and the spacer, and then forming a source/drain region adjacent to two sides of the spacer.

A method for fabricating a semiconductor device includes the steps of first forming a gate dielectric layer on a substrate, forming a gate material layer on the gate dielectric layer, patterning the gate material layer and the gate dielectric layer to form a gate structure, removing a portion of the gate dielectric layer, forming a spacer adjacent to the gate structure and at the same time forming an air gap between the gate dielectric layer and the spacer, and then forming a source/drain region adjacent to two sides of the spacer.

A method of manufacturing a semiconductor device includes forming a fin structure in which first semiconductor layers and second semiconductor layers are alternatively stacked, the first and second semiconductor layers having different material compositions; forming a sacrificial gate structure over the fin structure; forming a gate spacer on sidewalls of the sacrificial gate structure; etching a source/drain (S/D) region of the fin structure, which is not covered by the sacrificial gate structure and the gate spacer, thereby forming an S/D trench; laterally etching the first semiconductor layers through the S/D trench, thereby forming recesses; selectively depositing an insulating layer on surfaces of the first and second semiconductor layers exposed in the recesses and the S/D trench, but not on sidewalls of the gate spacer; and growing an S/D epitaxial feature in the S/D trench, thereby trapping air gaps in the recesses.

A method includes forming a mask layer above a substrate. The substrate is patterned by using the mask layer as a mask to form a trench in the substrate. An isolation structure is formed in the trench, including feeding first precursors to the substrate. A bias is applied to the substrate after feeding the first precursors. With the bias turned on, second precursors are fed to the substrate. Feeding the first precursors, applying the bias, and feeding the second precursors are repeated.

A fin field effect transistor device structure includes a fin structure formed over a substrate. The structure also includes a liner layer and an isolation structure surrounding the fin structure. The structure also includes a gate dielectric layer formed over the fin structure and the isolation structure. The structure also includes a gate structure formed over the gate dielectric layer. The structure also includes source/drain epitaxial structures formed on opposite sides of the gate structure. The fin structure includes a protruding portion laterally extending over the liner layer.

Techniques for area scaling of contacts in VTFET devices are provided. In one aspect, a VTFET device includes: a fin(s); a bottom source/drain region at a base of the fin(s); a gate stack alongside the fin(s); a top source/drain region present at a top of the fin(s); a bottom source/drain contact to the bottom source/drain region; and a gate contact to the gate stack, wherein the bottom source drain and gate contacts each includes a top portion having a width W1.sub.CONTACT over a bottom portion having a width W2.sub.CONTACT, wherein W2.sub.CONTACT<W1.sub.CONTACT, and wherein a sidewall along the top portion is discontinuous with a sidewall along the bottom portion. The bottom portion having the width W2.sub.CONTACT is present alongside the gate stack and the top source/drain region. A method of forming a VTFET device is also provided.

A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate stack structure formed over a substrate. The gate stack structure includes a gate electrode structure having a first portion and a second portion and a first conductive layer below the gate electrode structure. In addition, the first portion of the gate electrode structure is located over the second portion of the gate electrode structure, and a width of a top surface of the first portion of the gate electrode structure is greater than a width of a bottom surface of the second portion of the gate electrode structure.