A method of etching for a semiconductor structure having a substrate, and a first structure located on part of a top surface of the substrate, where two side surfaces of the first structure are configured as sidewalls, can include: forming an insulation layer to cover the substrate, the first structure, and the sidewalls; performing a dry etching process to etch a first portion of the insulation layer; and performing a wet etching process to etch a remaining portion of the insulation layer, in order to expose the top surface of the substrate, where a thickness of the first portion of the insulation layer etched by the dry etching process is greater than a thickness of the remaining portion of insulation layer etched by the wet etching process, in order to decrease formation of cavity in the substrate and/or sidewalls.

A semiconductor device includes a chip having a principal surface, a trench insulating structure formed in the principal surface of the chip, a first conductivity type body region formed in a surface layer portion of the principal surface such that the body region is in contact with the trench insulating structure, a second conductivity type source region formed in a surface layer portion of the body region while being separated from the trench insulating structure, a first conductivity type butting region formed in a region between the trench insulating structure and the source region in the surface layer portion of the body region, and a planar gate structure that passes through a side of the butting region, covers the body region and the trench insulating structure, and is capable of controlling reversal and non-reversal of a channel in the body region.

An LDMOS transistor can include: a field oxide layer structure adjacent to a drain region; and at least one drain oxide layer structure adjacent to the field oxide layer structure along a lateral direction, where a thickness of the drain oxide layer structure is less than a thickness of the field oxide layer, and at least one of a length of the field oxide layer structure and a length of the drain oxide layer structure is adjusted to improve a breakdown voltage performance of the LDMOS transistor.

In an aspect, a process of forming an electronic device can include patterning a substrate to define a trench having a sidewall and forming a first semiconductor layer within the trench and along the sidewall. In an embodiment, the process can further include forming a barrier layer within the trench after forming the first semiconductor layer; forming a second semiconductor layer within the trench after forming the barrier layer, wherein within the trench, first and second portions of the second semiconductor layer contact each other adjacent to a vertical centerline of the trench; and exposing the second semiconductor layer to radiation sufficient to allow a void within second semiconductor layer to migrate toward the barrier layer. In another embodiment, after forming a semiconductor within the trench, the process can further include forming an insulating layer that substantially fills a remaining portion of the trench.

An integrated circuit (IC) having a high voltage semiconductor device with a plurality of field plates between the gate and drain. The IC further includes a biasing circuit electrically coupled to each of the plurality of field plates, the biasing circuit including a plurality of high voltage depletion mode transistors, each having a pinch off voltage. The high voltage depletion mode transistors may have different pinch off voltages, and each of the field plates are each independently biased by a different one of the high voltage depletion mode transistors.

A gate drive circuit for a power semiconductor device, a low-side switching circuit, a high-side switching circuit, and a drive method are disclosed. When a first gate driver receives a control signal which is at a first level, the first gate driver connects a first gate to a first voltage, so that the first gate controls a channel region. When the transistor operates on a Miller plateau, the area of an overlapping region between the first gate and a drain inside the transistor is relatively small, so the Miller capacitance of the transistor is relatively small, thereby improving the switching speed of the transistor. A second gate is connected to a second voltage after a first duration, so that the second gate controls a drift region of the transistor to form an accumulation layer, and the accumulation layer has a relatively high carrier concentration.

An apparatus includes lightly doped drain regions vertically extending into a semiconductor substrate. A channel region is horizontally interposed between the lightly doped drain regions, and source/drain regions vertically extend into the lightly doped drain regions. Breakdown-enhancement implant intrusion regions are within the lightly doped drain regions and are horizontally interposed between the channel region and the source/drain regions. The breakdown enhancement implant regions have a different chemical species than the lightly doped drain regions and have upper boundaries vertically underlying upper boundaries of the lightly doped drain regions. The apparatus also has a gate structure vertically overlying the channel regions and it is horizontally interposed between the breakdown-enhancement implant regions. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.

A high-voltage device structure and methods of forming the same are described. In some embodiments, the structure includes a deep well region of a first conductivity type disposed in a substrate, a doped region disposed on the deep well region; a well region of the first conductivity type surrounding the deep well region and the doped region; a source region disposed on the well region, a drain region disposed on the doped region, and a first pickup region of the first conductivity type disposed on the well region. The first pickup region is laterally in contact with the source region, and the first pickup region, the well region, and the deep well region are electrically connected.

According to one aspect of the present disclosure, a semiconductor device includes a substrate having a first type dopant. In some embodiments, the semiconductor device also includes an epitaxial layer above the substrate, having a second type dopant and a top region. In some embodiments, the semiconductor device also includes a trench in the top region of the epitaxial layer; at least one doped ring implanted in the epitaxial layer below the trench; and a dielectric material filling within the trench. In some embodiments, there is a twelve-sided body tie in the epitaxial layer, wherein the sides of the twelve-sided body tie are not all equal to each other.

A high voltage semiconductor device includes a semiconductor substrate, an isolation structure, a gate oxide layer, and a gate structure. The semiconductor substrate includes a channel region, and at least a part of the isolation structure is disposed in the semiconductor substrate and surrounds the channel region. The gate oxide layer is disposed on the semiconductor substrate, and the gate oxide layer includes a first portion and a second portion. The second portion is disposed at two opposite sides of the first portion in a horizontal direction, and a thickness of the first portion is greater than a thickness of the second portion. The gate structure is disposed on the gate oxide layer and the isolation structure.