A Dual-wavelength hybrid (DWH) device includes an n-type ohmic contact layer, cathode and anode terminal electrodes, first and second injector terminal electrodes, p-type and n-type modulation doped QW structures, and first through sixth ion implant regions. The first injector terminal electrode is formed on the third ion implant region that contacts the p-type modulation doped QW structure and the second injector terminal electrode is formed on the fourth ion implant region that contacts the n-type modulation doped QW structure. The DWH device operates in at least one of a vertical cavity mode and a whispering gallery mode. In the vertical cavity mode, the DWH device converts an in-plane optical mode signal to a vertical optical mode signal, whereas in the whispering gallery mode the DWH device converts a vertical optical mode signal to an in-plane optical mode signal.

The invention includes a semiconductor device comprising an interlevel dielectric layer over a buried insulator layer over a semiconductor substrate; a source and drain in the interlevel layer; a channel between the source and drain, the channel including a first region having a first bandgap adjacent to a second region having a second bandgap, wherein the first band gap is larger than the second bandgap; and a gate over the channel.

A power device includes a gate, and a segmented source adjacent to the gate, wherein the segmented source includes segments having a first threshold voltage and includes segments having a second threshold voltage different from the first threshold voltage.

A two-transistor memory cell based upon a thyristor for an SRAM integrated circuit is described together with a process for fabricating it. The memory cell can be implemented in different combinations of MOS and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM.

A transistor includes first and second load terminals and a semiconductor body coupled to both terminals. The semiconductor body includes: a drift region having dopants of a first conductivity type; a transistor section for conducting a forward load current and having a control head coupling the first load terminal to a first side of the drift region; and a diode section for conducting a reverse load current. A diode port couples the second load terminal to a second side of the drift region and includes: a first emitter electrically connected to the second load terminal and having dopants of the first conductivity type for injecting majority charge carriers into the drift region; and a second emitter having dopants of a second conductivity type for injecting minority charge carriers into the drift region. A pn-junction transition between the first and second emitters has a breakdown voltage of less than 10 V.

After forming a buried nanowire segment surrounded by a gate structure located on a substrate, an epitaxial source region is grown on a first end of the buried nanowire segment while covering a second end of the buried nanowire segment and the gate structure followed by growing an epitaxial drain region on the second end of the buried nanowire segment while covering the epitaxial source region and the gate structure. The epitaxial source region includes a first semiconductor material and dopants of a first conductivity type, while the epitaxial drain region includes a first semiconductor material different from the first semiconductor material and dopants of a second conductivity type opposite the first conductivity type.

The invention includes a semiconductor device comprising an interlevel dielectric layer over a buried insulator layer over a semiconductor substrate; a source and drain in the interlevel layer; a channel between the source and drain, the channel including a first region having a first bandgap adjacent to a second region having a second bandgap, wherein the first band gap is larger than the second bandgap; and a gate over the channel.

The invention includes a semiconductor device comprising an interlevel dielectric layer over a buried insulator layer over a semiconductor substrate; a source and drain in the interlevel layer; a channel between the source and drain, the channel including a first region having a first bandgap adjacent to a second region having a second bandgap, wherein the first band gap is larger than the second bandgap; and a gate over the channel.

The invention provides a semiconductor device. The semiconductor device includes a buried oxide layer disposed on a substrate. A semiconductor layer having a first conduction type is disposed on the buried oxide layer. A first well doped region having a second conduction type is disposed in the semiconductor layer. A cathode doped region having the second conduction type is disposed in the first well doped region. A first anode doped region having the first conduction type is disposed in the first well doped region, separated from the cathode doped region. A first distance from a bottom boundary of the first anode doped region to a top surface of the semiconductor layer is greater than a second distance from the bottom boundary to an interface between the semiconductor layer and the buried oxide layer.

A tunnel field-effect transistor device includes a p-type GaN source layer, an n-type GaN drain layer, and an interlayer interfaced between the source-layer and the drain layer. In one example, the interlayer includes an Indium Nitride (InN) layer. In one example, the interlayer includes a graded Indium gallium nitride layer and an InN layer. In one example, the interlayer may include a graded Indium gallium nitride (In.sub.xGa.sub.1-xN) layer and an Indium gallium nitride (InGaN) layer. In one example, the tunnel field-effect transistor device includes an in-line configuration. In one example, the tunnel field-effect transistor device includes a side-wall configuration.