Patent classifications
H10D62/177
SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD FOR SEMICONDUCTOR STRUCTURE
Disclosed are a semiconductor structure and a manufacturing method for the semiconductor structure. The semiconductor structure includes a light-emitting structure; a light control layer disposed on a side of the light-emitting structure, including a plurality of light control regions regularly arranged and a substrate structure located between the plurality of light control regions; where the plurality of light control regions include a wavelength conversion structure, and the wavelength conversion structure includes a quantum dot and a porous structure adsorbed with the quantum dot. In the present disclosure, the plurality of light control regions and the substrate structure are provided to ensure uniform light output, good directionality, high light extraction rate, and avoidance of light crosstalk in each light control region. The porous structure is utilized to adsorb the quantum dot and achieve a full color display, thereby improving resolution, simplifying a manufacturing process and reducing costs.
OXIDE FLUORESCENT MATERIAL AND LIGHT EMITTING DEVICE USING THE SAME
An oxide fluorescent material has a composition represented by the following formula (1).
(Ga.sub.1-uM.sup.1.sub.u).sub.2(Ge.sub.1-vM.sup.2.sub.v).sub.wO.sub.x:Cr.sub.y,M.sup.3.sub.z(1), wherein M.sup.1 represents at least one element selected from the group consisting of Al, Sc, and In; M.sup.2 represents at least one element selected from the group consisting of Si, Ti, Zr, Sn, and Hf, M.sup.3 represents at least one element selected from the group consisting of Ni, Eu, Fe, Mn, Nd, Tm, Ho, Er, and Yb; and u, v, w, x, y, and z satisfy 0u1.0, 0v0.5, 1.0w3.0, 5x9, 0.005y1.0, and 0z0.5, respectively.
POWER AMPLIFIER SYSTEMS INCLUDING CONTROL INTERFACE AND WIRE BOND PAD
A power amplifier module includes a power amplifier including a GaAs bipolar transistor having a collector, a base abutting the collector, and an emitter, the collector having a doping concentration of at least about 310.sup.16 cm.sup.3 at a junction with the base, the collector also having at least a first grading in which doping concentration increases away from the base; and an RF transmission line driven by the power amplifier, the RF transmission line including a conductive layer and finish plating on the conductive layer, the finish plating including a gold layer, a palladium layer proximate the gold layer, and a diffusion barrier layer proximate the palladium layer, the diffusion barrier layer including nickel and having a thickness that is less than about the skin depth of nickel at 0.9 GHZ. Other embodiments of the module are provided along with related methods and components thereof.
IGBT having deep gate trench
There are disclosed herein various implementations of an insulated-gate bipolar transistor (IGBT) with buried depletion electrode. Such an IGBT may include a collector at a bottom surface of a semiconductor substrate, a drift region having a first conductivity type situated over the collector, and a base layer having a second conductivity type opposite the first conductivity type situated over the drift region. The IGBT also includes a plurality of deep insulated trenches with a buried depletion electrode and at least one gate electrode disposed therein. In addition, the IGBT includes an active cell including an emitter adjacent the gate electrode, and an implant zone, situated between adjacent deep insulated trenches. The implant zone is formed below the base layer and has the first conductivity type. In one implementation, the IGBT may also include a dummy cell neighboring the active cell.
Bipolar transistor compatible with vertical FET fabrication
Integrated chips and methods of forming the same include forming a gate stack around a first semiconductor fin and a second semiconductor fin. The gate stack around the second semiconductor fin is etched away. An extrinsic base is formed around the second semiconductor fin in a region exposed by etching away the gate stack.
FABRICATION OF INTEGRATED CIRCUIT STRUCTURES FOR BIPOLOR TRANSISTORS
Methods of according to the present disclosure can include: providing a substrate including: a first semiconductor region, a second semiconductor region, and a trench isolation (TI) laterally between the first and second semiconductor regions; forming a seed layer on the TI and the second semiconductor region of the substrate, leaving the first semiconductor region of the substrate exposed; forming an epitaxial layer on the substrate and the seed layer, wherein the epitaxial layer includes: a first semiconductor base material positioned above the first semiconductor region of the substrate, and an extrinsic base region positioned above the seed layer; forming an opening within the extrinsic base material and the seed layer to expose an upper surface of the second semiconductor region; and forming a second semiconductor base material in the opening.
Power amplifier modules with harmonic termination circuit and related systems, devices, and methods
One aspect of this disclosure is a power amplifier module that includes a power amplifier configured to provide a radio frequency signal at an output, an output matching network coupled to the output of the power amplifier and configured to provide impedance matching at a fundamental frequency of the radio frequency signal, and a harmonic termination circuit coupled to the output of the power amplifier. The power amplifier is included on a power amplifier die. The output matching network can include a first circuit element electrically connected to an output of the power amplifier by way of a pad on a top surface of a conductive trace, in which the top surface has an unplated portion between the pad the power amplifier die. The harmonic termination circuit can include a second circuit element. The first and second circuit elements can have separate electrical connections to the power amplifier die. Other embodiments of the module are provided along with related methods and components thereof.
Semiconductor device and method for producing the same
A method of producing a semiconductor device is disclosed in which, after proton implantation is performed, a hydrogen-induced donor is formed by a furnace annealing process to form an n-type field stop layer. A disorder generated in a proton passage region is reduced by a laser annealing process to form an n-type disorder reduction region. As such, the n-type field stop layer and the n-type disorder reduction region are formed by the proton implantation. Therefore, it is possible to provide a stable and inexpensive semiconductor device which has low conduction resistance and can improve electrical characteristics, such as a leakage current, and a method for producing the semiconductor device.
Vertical P-type, N-type, P-type (PNP) junction integrated circuit (IC) structure
Various particular embodiments include an integrated circuit (IC) structure having: a stack region; and a silicon substrate underlying and contacting the stack region, the silicon substrate including: a silicon region including a doped subcollector region; a set of isolation regions overlying the silicon region; a base region between the set of isolation regions and below the stack region, the base region including an intrinsic base contacting the stack region, an extrinsic base contacting the intrinsic base and the stack region, and an amorphized extrinsic base contact region contacting the extrinsic base; a collector region between the set of isolation regions; an undercut collector-base region between the set of isolation regions and below the base region; and a collector contact region contacting the collector region under the intrinsic base and the collector-base region via the doped subcollector region.
Method of forming a biCMOS semiconductor chip that increases the betas of the bipolar transistors
The betas of the bipolar transistors in a BiCMOS semiconductor structure are increased by forming the emitters of the bipolar transistors with two implants: a source-drain implant that forms a first emitter region at the same time that the source and drain regions are formed, and an additional implant that forms a second emitter region at the same time that another region is formed. The additional implant has an implant energy that is greater than the implant energy of the source-drain implant.