A field effect transistor includes a semiconductor stack including a channel provided on a border between a first nitride semiconductor and a second nitride semiconductor provided on the first nitride semiconductor in a stacking direction. A source electrode, a gate electrode, and a drain electrode are disposed on the semiconductor stack. The gate electrode is disposed between the source electrode and the drain electrode. At least one hole is provided to pass through the channel from the first nitride semiconductor to the second nitride semiconductor to provide channel paths from the gate electrode to the drain electrode. A minimum distance of the channel paths is longer than a minimum distance between the gate electrode and drain electrode viewed in the stacking direction. The insulating member is filled in the at least one hole and has a breakdown field strength higher than a breakdown field strength of the semiconductor stack.

A silicon carbide substrate has first to third semiconductor layers. The first and third semiconductor layers have a first conductivity type, and the second semiconductor layer has a second conductivity type. A trench has a bottom surface and first to third side surfaces, the bottom surface being constituted of the first semiconductor layer, the first to third side surfaces being respectively constituted of the first to third semiconductor layers. A gate insulating film having a bottom portion and a side wall portion is provided on the trench. The bottom portion has a minimum thickness d.sub.0. A portion of the side wall portion on the second side surface has a minimum thickness d.sub.1. A portion, connected to the bottom portion, of the side wall portion on the first side surface has a thickness d.sub.2. Moreover, d.sub.2>d.sub.1 and d.sub.2>d.sub.0 are satisfied.

A high electron mobility transistor (HEMT) includes a silicon substrate, an unintentionally doped gallium nitride (UID GaN) layer over the silicon substrate. The HEMT further includes a donor-supply layer over the UID GaN layer, a gate structure, a drain, and a source over the donor-supply layer. The HEMT further includes a dielectric layer having one or more dielectric plug portions in the donor-supply layer and top portions between the gate structure and the drain over the donor-supply layer. A method for making the HEMT is also provided.

A nitride semiconductor device includes: a substrate; a buffer layer formed on the substrate; a laminated body formed by two or more cycles of semiconductor layers each including a first nitride semiconductor layer, and a second nitride semiconductor layer having a larger band gap than a band gap of the first nitride semiconductor layer, the first and second nitride semiconductor layers being laminated in this order on the buffer layer; a first electrode; and a second electrode. A channel layer is formed in each of the semiconductor layers at an interface between the first nitride semiconductor layer and the second nitride semiconductor layer. A carrier concentration of the channel layer in the uppermost semiconductor layer is lower than a carrier concentration of each of the channel layers of the other semiconductor layers.

An electronic device can include a HEMT including at least two channel layers. In an embodiment, a lower semiconductor layer overlies a lower channel layer, wherein the lower semiconductor layer has an aluminum content that is at least 10% of a total metal content of the lower semiconductor layer. An upper semiconductor layer overlies the upper channel layer, wherein the upper semiconductor layer has an aluminum content that is greater as compared to the lower semiconductor layer. In another embodiment, an electronic device can include stepped source and drain electrodes, so that lower contact resistance can be achieved. In a further embodiment, an absolute value of a difference between pinch-off or threshold voltages between different channel layers is greater than 1 V and allows current to be turned on or turned off for a channel layer without affecting another channel layer.

A semiconductor device includes a barrier region and a channel region, source and drain electrodes, and a gate structure that is configured to control a conductive connection between the source and drain electrodes, wherein the barrier region comprises a first barrier layer, a second barrier layer, and a third barrier layer, wherein in a central portion of the device the second barrier layer and the third barrier layer are disposed over the channel region, wherein in outer lateral portions of the device the first barrier layer is disposed over the channel region, and wherein a molar fraction of a second type III element in the central portion is higher than a molar fraction of the second type III element in the first barrier layer.

A semiconductor structure includes a semiconductor substrate, a plurality of stacked units, a conductive structure, a plurality of dielectrics, a first electrode strip, a second electrode strip, and a plurality of contact structures. The stacked units are stacked up over the semiconductor substrate, and comprises a first passivation layer, a second passivation layer and a channel layer sandwiched between the first passivation layer and the second passivation layer. The conductive structure is disposed on the semiconductor substrate and wrapping around the stacked units. The dielectrics are surrounding the stacked units and separating the stacked units from the conductive structure. The first electrode strip and the second electrode strip are located on two opposing sides of the conductive structure. The contact structures are connecting the channel layer of each of the stacked units to the first electrode strip and the second electrode strip.

In some examples, a transistor comprises a gallium nitride (GaN) layer; a GaN-based alloy layer having a top side and disposed on the GaN layer, wherein source, drain, and gate contact structures are supported by the GaN layer, and a first doped region positioned in a drain access region and extending from the top side into the GaN layer.

A technique relates to a semiconductor device. First metal contacts are formed on top of a substrate. The first metal contacts are arranged in a first direction, and the first metal contacts are arranged such that areas of the substrate remain exposed. Insulator pads are positioned at predefined locations on top of the first metal contacts, such that the insulator pads are spaced from one another. Second metal contacts are formed on top of the insulator pads, such that the second metal contacts are arranged in a second direction different from the first direction. The first and second metal contacts sandwich the insulator pads at the predefined locations. Surface-sensitive conductive channels are formed to contact the first metal contacts and the second metal contacts. Four-terminal devices are defined by the surface-sensitive conductive channels contacting a pair of the first metal contacts and contacting a pair of the metal contacts.

According to this GaN-based HFET, resistivity of a semi-insulating film forming a gate insulating film is 3.910.sup.9cm. The value of this resistivity is a value derived when the current density is 6.2510.sup.4 (A/cm.sup.2). By inclusion of the gate insulating film by a semi-insulating film having a resistivity =3.910.sup.9cm, a withstand voltage of 1000 V can be obtained. Meanwhile, the withstand voltage abruptly drops as the resistivity of the gate insulating film exceeds 1 10.sup.11cm, and the gate leak current increases when the resistivity of the gate insulating film drops below 1 10.sup.7cm.