Semiconductor devices are formed using a thin epitaxial layer (nanotube) formed on sidewalls of dielectric-filled trenches. In one embodiment, a method for forming a semiconductor device includes forming a first epitaxial layer on sidewalls of trenches and forming second epitaxial layer on the first epitaxial layer where charges in the doped regions along the sidewalls of the first and second trenches achieve charge balance in operation. In another embodiment, the semiconductor device includes a termination structure including an array of termination cells.

Semiconductor device stacks and devices made there from having Ge-rich device layers. A Ge-rich device layer is disposed above a substrate, with a p-type doped Ge etch suppression layer (e.g., p-type SiGe) disposed there between to suppress etch of the Ge-rich device layer during removal of a sacrificial semiconductor layer richer in Si than the device layer. Rates of dissolution of Ge in wet etchants, such as aqueous hydroxide chemistries, may be dramatically decreased with the introduction of a buried p-type doped semiconductor layer into a semiconductor film stack, improving selectivity of etchant to the Ge-rich device layers.

A method includes forming fin semiconductor features on a substrate. A dopant-containing dielectric material layer is formed on sidewalls of the fin semiconductor features and the substrate. A precise material modification (PMM) process is performed to the dopant-containing dielectric material layer. The PMM process includes forming a first dielectric material layer over the dopant-containing dielectric material layer; performing a tilted ion implantation to the first dielectric material layer so that a top portion of the first dielectric material layer is doped to have a modified etch characteristic different from an etch characteristic of a bottom portion of the first dielectric material layer; and performing an etch process to selectively remove the top portion of the first dielectric material layer and the top portion of the dopant-containing dielectric material layer.

Embodiments include high electron mobility transistors (HEMTs) comprising a substrate and a barrier layer including a doped component. The doped component may be a germanium doped layer or a germanium doped pulse. Other embodiments may include methods for fabricating such a HEMT.

A layer structure and method of fabrication of a semiconductor heterostructure containing a two-dimensional electron gas (2DEG), two-dimensional hole gas (2DHG), or a two-dimensional electron/hole gas (2DEHG). The heterostructure contains a quantum well layer with 2DEG, 2DHG, or 2DEHG embedded between two doped charge reservoir layers and at least two remote charge reservoir layers. Such scheme allows reducing the number of scattering ions in the proximity of the quantum well as well a possibility for a symmetric potential for the electron or hole wavefunction in the quantum well, leading to significant improvement in carrier mobility in a broad range of 2DEG or 2DHG concentration in the quantum well. Embodiments of the invention may be applied to the fabrication of galvano-magnetic sensors, HEMT, pHEMT, and MESFET devices.

A resonant inter-band tunnel diode (RITD) can be fabricated using semiconductor processing similar to that used for Complementary Metal-Oxide-Semiconductor (CMOS) device fabrication, such as can include using silicon. A memory cell (e.g., a random access memory (RAM) cell) can be fabricated to include one or more negative differential resistance device, such as tunneling diodes, such as to provide a single-bit or multi-bit cell. In an example, a hybrid memory cell can be fabricated, such as including one or more negative resistance devices, a MOS transistor structure, and a capacitor structure, such as including an integrated capacitor configuration similar to a generally-available dynamic RAM (DRAM) structure, but such as without requiring a refresh and offering a higher area efficiency.

An integrated circuit can include a plurality of first transistors formed in a substrate and having gate lengths of less than one micron and at least one tipless transistor formed in the substrate and having a source-drain path coupled between a circuit node and a first power supply voltage. In addition or alternatively, an integrated circuit can include minimum feature size transistors; a signal driving circuit comprising a first transistor of a first conductivity type having a source-drain path coupled between a first power supply node and an output node, and a second transistor of a second conductivity type having a source-drain path coupled between a second power supply node and the output node, and a gate coupled to a gate of the first transistor, wherein the first or second transistor is a tipless transistor.

Methods and apparatus for training a multi-layer artificial neural network for use in speech recognition. The method comprises determining for a first speech pattern of the plurality of speech patterns, using a first processing pipeline, network activations for a plurality of nodes of the artificial neural network in response to providing the first speech pattern as input to the artificial neural network, determining based, at least in part, on the network activations and a selection criterion, whether the artificial neural network should be trained on the first speech pattern, and updating, using a second processing pipeline, network weights between nodes of the artificial neural network based, at least in part, on the network activations when it is determined that the artificial neural network should be trained on the first speech pattern.

III-N transistors with recessed gates. An epitaxial stack includes a doped III-N source/drain layer and a III-N etch stop layer disposed between a the source/drain layer and a III-N channel layer. An etch process, e.g., utilizing photochemical oxidation, selectively etches the source/drain layer over the etch stop layer. A gate electrode is disposed over the etch stop layer to form a recessed-gate III-N HEMT. At least a portion of the etch stop layer may be oxidized with a gate electrode over the oxidized etch stop layer for a recessed gate III-N MOS-HEMT including a III-N oxide. A high-k dielectric may be formed over the oxidized etch stop layer with a gate electrode over the high-k dielectric to form a recessed gate III-N MOS-HEMT having a composite gate dielectric stack.

A system and method for manufacturing a semiconductor device is provided. An embodiment comprises forming a deposited layer using an atomic layer deposition (ALD) process. The ALD process may utilize a first precursor for a first time period, a first purge for a second time period longer than the first time period, a second precursor for a third time period longer than the first time period, and a second purge for a fourth time period longer than the third time period.