A light emitting device including a substrate having a first region and a second region, a light emitting stack including vertically stacked semiconductor layers disposed on the first region of the substrate, at least one pillar disposed on the second region of the substrate and laterally spaced apart from the light emitting stack, and at least one electrode extending from the first region to the second region of the substrate and electrically connecting the light emitting stack to the at least one pillar, in which the at least one pillar is disposed on the at least one electrode, respectively.

A method of fabricating an LED light plate, an LED light plate, and a display device are disclosed. The method includes: disposing a functional layer on each LED chip to form multiple chips to be transferred; placing the chips into a receiving tank filled with a suspension; defining a plurality of grooves matching the shape of the functional layer in the transport substrate; placing the transport substrate into the suspension so that a first electrode in each receiving tank faces each second electrode in the respective groove and that each chip is located between the first electrode and the respective second electrode; energizing the first electrode and each second electrode, so that each chip is absorbed by the transporting substrate, and each functional layer is moved into the respective groove; and transplanting the multiple chips onto a target substrate; where each functional layer is filled with multiple charged particles.

A display panel, a tiled display panel and a manufacturing method of display panel are provided. The display panel includes a substrate; a light-shielding layer disposed on the substrate and provided with a plurality of through-holes; a transparent insulation layer including transparent portions arranged in the through-holes respectively; a light-emitting layer disposed on the transparent insulation layer, wherein the light-emitting layer includes a plurality of light-emitting diode (LED) chips are disposed to the plurality of through-holes in a one-to-one correspondence, and a light-emitting surface the LED chip faces to the transparent portion; a device array layer disposed on the light-shielding layer and including a driver and a plurality of metal wirings used to connect the LED chips with the driver; and a sealing layer disposed on the substrate and encapsulating the light-shielding layer, the transparent insulation layer, the light-emitting layer, and the device array layer.

This application discloses a pixel unit for semiconductor device and a manufacturing method, a micro display screen, and a discrete device, the pixel unit includes a target drive circuit, a display unit, and a common cathode, the backplane is provided with a drive circuit, and the drive circuit is provided with at least one anode; the display unit is provided on the backplane, it includes a first device layer and a second device layer stacked vertically from bottom to top, the first device layer and the second device layer are respectively connected to the corresponding anodes of the backplane; the common cathode is respectively connected to each device layer in the display unit, and the common cathode is connected to the external cathode.

An embodiment of the present disclosure provides a semiconductor device arrangement. This arrangement includes a substrate, an adhesive structure, and a first semiconductor device. The substrate includes an upper surface. The adhesive structure is located on the upper surface and includes a first concave region. The first semiconductor device includes a lower surface facing toward the adhesive structure and a conductive bump located under the lower surface and in the first concave region. The conductive bump includes a first portion and a second portion. Wherein the lower surface does not contact the adhesive structure, the first portion contacts the first concave region, and the second portion does not contact the first concave region.

A display device may include: a substrate having a display area and a non-display area, and including a first surface and a second surface facing away from each other in a thickness direction of the substrate, and a side surface connecting the first and second surfaces; a light emitting element on the first surface of the substrate in the display area; a pad electrode on the first surface of the substrate in the non-display area; an intermediate electrode on the second surface of the substrate in the display area; and a side connection line on the side surface, and electrically connected to each of the pad electrode and the intermediate electrode. The pad electrode may include a first pad electrode and a second pad electrode. Opposite side surfaces of the second pad electrode may have the same inclination angles as opposite side surfaces of the first pad electrode.

A method for repairing an electronic substrate by removing a bad electronic component from a pad on the electronic substrate uses steps of: providing a control pad image; providing an image of the pad with which the bad electronic component is bonded; comparing the image of the pad with which the bad electronic component is bonded with the control pad image to determine a difference between the said images; generating a positioning directive based on the difference, and following the positioning directive to position the bad electronic component; and applying an energy beam onto the positioned bad electronic component to deconstruct a bonding between the positioned bad electronic component and the pad. A method for making an LED display is also provided.

A p-type semiconductor region is formed in a front surface side of an n-type semiconductor substrate. An n-type field stop (FS) region including protons as a donor is formed in a rear surface side of the semiconductor substrate. A concentration distribution of the donors in the FS region include first, second, third and fourth peaks in order from a front surface to the rear surface. Each of the peaks has a peak maximum point, and peak end points formed at both sides of the peak maximum point. The peak maximum points of the first and second peaks are higher than the peak maximum point of the third peak. The peak maximum point of the third peak is lower than the peak maximum point of the fourth peak.

The disclosed technology relates to semiconductors, and more particularly to a junction field effect transistor (JFET). In one aspect, a method of fabricating a JFET includes forming a well of a first dopant type in a substrate, wherein the well is isolated from the substrate by an isolation region of a second dopant type. The method additionally includes implanting a dopant of the second dopant type at a surface of the well to form a source, a drain and a channel of the JFET, and implanting a dopant of the first dopant type at the surface of the well to form a gate of the JFET. The method additionally includes, prior to implanting the dopant of the first type and the dopant of the second type, forming a pre-metal dielectric (PMD) layer on the well and forming contact openings in the PMD layer above the source, the drain and the gate. The PMD layer has a thickness such that the channel is formed by implanting the dopant of the first type and the dopant of the second type through the PMD layer. The method further includes, after implanting the dopant of the first type and the dopant of the second type, siliciding the source, the drain and the gate, and forming metal contacts in the contact openings.

Hydrogen atoms and crystal defects are introduced into an n semiconductor substrate by proton implantation. The crystal defects are generated in the n semiconductor substrate by electron beam irradiation before or after the proton implantation. Then, a heat treatment for generating donors is performed. The amount of crystal defects is appropriately controlled during the heat treatment for generating donors to increase a donor generation rate. In addition, when the heat treatment for generating donors ends, the crystal defects formed by the electron beam irradiation and the proton implantation are recovered and controlled to an appropriate amount of crystal defects. Therefore, for example, it is possible to improve a breakdown voltage and reduce a leakage current.