A through-silicon via structure is provided. A semiconductor substrate has a first surface and a second surface, and the second surface is opposite to the first surface. A TSV extends from the first surface to the second surface of the semiconductor substrate. An N-type doped region surrounds the TSV and extends from the first surface to the second surface of the semiconductor substrate. A P-type well region is formed in the semiconductor substrate and surrounds the N-type doped region. A P-type doped region is formed in the P-type well region and surrounds the N-type doped region. The junction of the P-type well region and the N-type doped region forms an electrostatic discharge protection diode.

Provided is a semiconductor device manufacturing method. The device has a substrate including one and another surfaces. A first semiconductor region of a first conductivity type is formed in the substrate. A second conductivity type, second semiconductor region is provided in a first surface layer, that includes the one surface, of the substrate. A first electrode is in contact with the second semiconductor region to form a junction therebetween. A first conductivity type, third semiconductor region is provided in a second surface layer, that includes the another surface, of the substrate. The third semiconductor region has a higher impurity concentration than the first semiconductor region. A fourth semiconductor region of the second conductivity type is provided in the first semiconductor region at a location deeper than the third semiconductor region from the another surface. A second electrode is in contact with the third semiconductor region.

This invention involves a fabrication method of fast recovery diode, which includes following steps: growing a sacrificial oxide layer on a surface of an N substrate; forming a P type doped field-limiting ring region on the substrate; forming a P type doped anode region on the substrate; removing the sacrificial oxide layer; annealing the substrate to form a PN junction; implanting oxygen into the surface of the substrate by ion implantation; annealing the substrate to form a silicon dioxide layer on the surface of the substrate; removing the silicon dioxide layer; forming an anode electrode and a cathode electrode of the fast recovery diode. The method eliminates the curved parts near the silicon surface of the profile of PN junction, decreases electric field intensity at the surface of the substrate, therefore increases the breakdown voltage and reliability of the fast recovery diode.

A semiconductor device includes: a semiconductor substrate; a main electrode; a peripheral electrode; an insulating protective film; a surface metallic layer; and a solder layer, wherein the semiconductor substrate includes: a first region of a first conductive-type in contact with the main electrode on a main contact surface; a second region of a first conductive-type in contact with the peripheral electrode on a peripheral contact surface; and a third region of a second conductive-type provided under the first region, under the second region, and circumferentially outward of the second region, and a circumferentially-outward end of the metallic layer and a circumferentially-outward end of the solder layer are located more circumferentially inward than the circumferentially-outward end of the peripheral electrode.

A vertical gallium nitride (GaN) PN diode uses epitaxial growth of a thick drift region with a very low carrier concentration and a carefully designed multi-zone junction termination extension to achieve high voltage blocking and high-power efficiency. An exemplary large area (1 mm.sup.2) diode had a forward pulsed current of 3.5 A, an 8.3 m-cm.sup.2 specific on-resistance, and a 5.3 kV reverse breakdown. A smaller area diode (0.063 mm.sup.2) was capable of 6.4 kV breakdown with a specific on-resistance of 10.2 m-cm.sup.2, when accounting for current spreading through the drift region at a 45 angle.

Hydrogen atoms and crystal defects are introduced into an n semiconductor substrate by proton implantation. The crystal defects are generated in the n semiconductor substrate by electron beam irradiation before or after the proton implantation. Then, a heat treatment for generating donors is performed. The amount of crystal defects is appropriately controlled during the heat treatment for generating donors to increase a donor generation rate. In addition, when the heat treatment for generating donors ends, the crystal defects formed by the electron beam irradiation and the proton implantation are recovered and controlled to an appropriate amount of crystal defects. Therefore, for example, it is possible to improve a breakdown voltage and reduce a leakage current.

A method of manufacturing a nitride semiconductor device is provided, comprising: forming, on a substrate, a first laminated body where a first nitride semiconductor layer, a second nitride semiconductor layer and a third nitride semiconductor layer are laminated in this order; subsequent to the forming, removing a partial region of the third nitride semiconductor layer, subsequent to the removing; implanting ions to the first nitride semiconductor layer from the partial region where the third nitride semiconductor layer is removed at least through the second nitride semiconductor layer; and subsequent to the implanting the ions, annealing the first laminated body.

A vertical power switching device, such as a vertical superjunction metal-oxide-semiconductor field-effect-transistor (MOSFET), in which termination structures in the corners of the integrated circuit are stretched to efficiently shape the lateral electric field. Termination structures in the device include such features as doped regions, field plates, insulator films, and high-voltage conductive regions and elements at the applied substrate voltage. Edges of these termination structures are shaped and placed according to a 2.sup.nd-order smooth, non-circular analytic function so as to extend deeper into the die corner from the core region of the device than a constant-distance path. Also disclosed are electrically floating guard rings in the termination region, to inhibit triggering of parasitic p-n-p-n structures.

According to various embodiments, a method for processing an electronic component including at least one electrically conductive contact region may include: forming a contact pad including a self-segregating composition over the at least one electrically conductive contact region to electrically contact the electronic component; forming a segregation suppression structure between the contact pad and the electronic component, wherein the segregation suppression structure includes more nucleation inducing topography features than the at least one electrically conductive contact region for perturbing a chemical segregation of the self-segregating composition by crystallographic interfaces of the contact pad defined by the nucleation inducing topography features.

In certain embodiments, a semiconductor device includes a plurality of semiconductor chips. Each semiconductor chip comprises a semiconductor body having a first side and a second side opposite the first side, a graphite substrate bonded to the second side of the semiconductor body and comprising an opening leaving an area of the second side of the semiconductor body uncovered by the graphite substrate, and a back-side metallization arranged in the opening of the graphite substrate and electrically contacting the area of the second side. The semiconductor device further includes a plurality of separation trenches each separating one of the plurality of semiconductor chips from an adjacent one of the plurality of semiconductor chips.