A power MOSFET or a power rectifier may be fabricated according to the invention to include a gate trench and a field plate trench. Both trenches can be formed with a two-step etching process as described in detail in the specification. The devices that embody this invention can be fabricated with higher packaging density and better and more tightly distributed device parameters such as the V.sub.F, R.sub.DSS, and BV.

Semiconductor devices includes a thin epitaxial layer (nanotube) formed on sidewalls of mesas formed in a semiconductor layer. In one embodiment, a semiconductor device includes a first semiconductor layer, a second semiconductor layer formed thereon and of the opposite conductivity type, and a first epitaxial layer formed on mesas of the second semiconductor layer. An electric field along a length of the first epitaxial layer is uniformly distributed.

The semiconductor device of the present invention includes a first conductivity type semiconductor layer made of a wide bandgap semiconductor and a Schottky electrode formed to come into contact with a surface of the semiconductor layer, and has a threshold voltage V.sub.th of 0.3 V to 0.7 V and a leakage current J.sub.r of 110.sup.9 A/cm.sup.2 to 110.sup.4 A/cm.sup.2 in a rated voltage V.sub.R.

A semiconductor structure includes: a substrate, having a cell region and a terminal region, and having a first surface, a second located in the terminal region, and a third surface located in the cell region, the second surface and the third surface being located at different levels; a first trench structure, located in the cell region, traversing the third surface to extend towards the first surface, including a first semiconductor material layer and a first oxide layer partially protruding from the third surface, and extending in a first direction parallel to the third surface; and a second trench structure, located in the cell region, including a second semiconductor material layer and a second oxide layer partially protruding from the third surface, and extending parallel to the first direction, wherein the third surface is provided with a doped region between the first trench structure and the second trench structure.

A Schottky device includes a plurality of mesa structures where one or more of the mesa structures includes a doped region having a multi-concentration dopant profile. In accordance with an embodiment, the Schottky device is formed from a semiconductor material of a first conductivity type. Trenches having sidewalls and floors are formed in the semiconductor material to form a plurality of mesa structures. A doped region having a multi-concentration impurity profile is formed in at least one trench, where the impurity materials of the doped region having the multi-concentration impurity profile are of a second conductivity type. A Schottky contact is formed to at least one of the mesa structures having the dope region with the multi-concentration impurity profile.

A semiconductor device according to an embodiment includes a first metal layer, a second metal layer, an n-type first SiC region provided between the first metal layer and the second metal layer and having an n-type impurity concentration of 110.sup.18 cm.sup.3 or less, and a conductive layer provided between the first SiC region and the first metal layer and containing titanium (Ti), oxygen (O), and at least one element selected from the group consisting of vanadium (V), niobium (Nb), and tantalum (Ta).

A compliant bipolar micro device transfer head array and method of forming a compliant bipolar micro device transfer array from an SOI substrate are described. In an embodiment, a compliant bipolar micro device transfer head array includes a base substrate and a patterned silicon layer over the base substrate. The patterned silicon layer may include first and second silicon interconnects, and first and second arrays of silicon electrodes electrically connected with the first and second silicon interconnects and deflectable into one or more cavities between the base substrate and the silicon electrodes.

A power MOSFET or a power rectifier may be fabricated according to the invention to include a gate trench and a field plate trench. Both trenches can be formed with a two-step etching process as described in detail in the specification. The devices that embody this invention can be fabricated with higher packaging density and better and more tightly distributed device parameters such as the V.sub.F, R.sub.DSS, and BV.

This invention discloses a semiconductor device disposed in a semiconductor substrate. The semiconductor device includes a first semiconductor layer of a first conductivity type on a first major surface. The semiconductor device further includes a second semiconductor layer of a second conductivity type on a second major surface opposite the first major surface. The semiconductor device further includes an injection efficiency controlling buffer layer of a first conductivity type disposed immediately below the second semiconductor layer to control the injection efficiency of the second semiconductor layer.

A method of forming a semiconductor includes a providing a termination trench and an active trench within a semiconductor layer. The active trench is configured to be at a shallower depth than the termination trench to provide a trench depth difference. The selected trench depth difference in combination with one or more of the dopant concentration of the semiconductor layer, the thickness of the semiconductor layer, active trench width to termination trench width, and/or dopant profile of the semiconductor layer provide a semiconductor device having improved performance characteristics.