An integrated circuit includes an NMOS SCR in which a p-type body well of the NMOS transistor provides a base layer for a vertical NPN layer stack. The base layer is formed by implanting p-type dopants using an implant mask which has a cutout mask element over the base area, so as to block the p-type dopants from the base area. The base layer is implanted concurrently with p-type body wells under NMOS transistors in logic components in the integrated circuit. Subsequent anneals cause the p-type dopants to diffuse into the base area, forming a base with a lower doping density that adjacent regions of the body well of the NMOS transistor in the NMOS SCR. The NMOS SCR may have a symmetric transistor, a drain extended transistor, or may be a bidirectional NMOS SCR with a symmetric transistor integrated with a drain extended transistor.

An electrostatic discharge protection circuit is disclosed. A method of manufacturing a semiconductor structure includes forming a semiconductor controlled rectifier including a first plurality of fingers between an n-well body contact and an anode in an n-well, and a second plurality of fingers between a p-well body contact and a cathode in a p-well.

A groove is formed in a first semiconductor layer 1, a sidewall of the groove is coated with a first insulating film 2, a first impurity layer 3 and a second impurity layer 4 thereon are disposed in the groove, a second semiconductor layer 7 is disposed on the second impurity layer, a first semiconductor is disposed at the other part, an n.sup.+ layer 6a and an n.sup.+ layer 6c are positioned at respective ends of the second semiconductor layer 7 and connected to a source line SL and a bit line BL, respectively, a first gate insulating layer 8 is formed on the second semiconductor layer 7, and a first gate conductor layer 9 is connected to a word line WL. Voltage applied to the source line SL, a plate line PL connected to the first semiconductor layer 1, the word line WL, and the bit line BL is controlled to perform data holding operation of holding, near the gate insulating layer, holes generated by an impact ionization phenomenon in a channel region 12 of the second semiconductor layer or by gate-induced drain leakage current, and data erase operation of removing the holes from the channel region 12.

FinFET multi-diode thyristor switches for protecting high data rate communication system interfaces are provided. In certain embodiments herein, high voltage tolerant FinFET thyristors are provided for handling high stress current and high RF power handling capability while providing low capacitance to allow wide bandwidth operation. Thus, the FinFET thyristors can be used to provide electrical overstress protection for ICs fabricated using FinFET technologies, while addressing tight radio frequency design window and robustness. In certain implementations, the FinFET thyristors include a first thyristor, a FinFET triggering circuitry and a second thyristor that serves to provide bidirectional blocking voltage and overstress protection. The FinFET triggering circuitry also enhances turn-on speed of the thyristor and/or reduces total on-state resistance.

The present application discloses a low voltage triggering silicon controlled rectifier which includes: an N well and a P well forming a PN junction, a first P+ region formed in the N well and connected to an anode, and a first N+ region formed in the P well and connected to a cathode. A second P+ region is formed in the N well at the PN junction and diffuses into the P well. A second N+ region is formed in the P well at the PN junction and diffuses into the N well. A first gate structure connected to the anode is formed at the surface of the N well between the first and second P+ regions; and a second gate structure connected to the cathode is formed at the surface of the P well between the first and second N+ regions.

Low capacitance poly-bounded silicon controlled rectifiers (SCRs) are disclosed herein. In certain embodiments, an SCR includes an n-type well (NW) and a p-type well (PW) formed adjacent to one another in a substrate. The SCR further includes active regions including p-type active (P+) fin regions over the NW and connected to an anode terminal of the SCR, and n-type active (N+) fin regions over the PW and connected to a cathode terminal of the SCR. The SCR further includes polysilicon gate regions over the PW and NW that serve to separate the active regions while also improving the SCR's turn-on speed in response to fast overstress transients.