A semiconductor device includes a plurality of first field-effect structures each including a polysilicon gate arranged on and in contact with a first gate dielectric, and a plurality of second field-effect structures each including a metal gate arranged on and in contact with a second gate dielectric. The plurality of first field-effect structures and the plurality of second field-effect structures form part of a power semiconductor device.

According to one embodiment, a semiconductor device comprises a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, a gate electrode, a gate insulating layer, a fourth semiconductor region of the second conductivity type, a first conductive unit and a first insulating layer. The fourth semiconductor region is provided selectively on the first semiconductor region. The fourth semiconductor region is separated from the second semiconductor region. At least a portion of the first conductive unit is surrounded with the fourth semiconductor region. At least a portion of the first insulating layer is provided between the first conductive unit and the fourth semiconductor region. A thickness of a portion of the first insulating layer is thinner than a film thickness of the gate insulating layer.

A method of manufacturing a super junction MOSFET, which includes a parallel pn layer including a plurality of pn junctions and in which an n-type drift region and a p-type partition region interposed between the pn junctions are alternately arranged and contact each other, a MOS gate structure on the surface of the parallel pn layer, and an n-type buffer layer in contact with an opposite main surface. The impurity concentration of the buffer layer is equal to or less than that of the n-type drift region. At least one of the p-type partition regions in the parallel pn layer is replaced with an n region with a lower impurity concentration than the n-type drift region.

A technique relates to semiconductors. A bottom terminal of a transistor and bottom plate of a capacitor are positioned on the substrate. A spacer is arranged on the bottom terminal of the transistor. A transistor channel region extends vertically from the bottom terminal through the spacer to contact a top terminal of the transistor. A capacitor channel region extends vertically from the bottom plate to contact a top plate of the capacitor. A first gate stack is arranged along sidewalls of the transistor channel region and is in contact with the spacer. A second gate stack is arranged along sidewalls of the capacitor channel region and is disposed on the bottom plate. A distance from a bottom of the first gate stack to a top of the bottom terminal is greater than a distance from a bottom of the second gate stack to a top of the bottom plate.

A semiconductor wafer is formed with a first device layer having active devices. A handle wafer having a trap rich layer is bonded to a top surface of the semiconductor wafer. A second device layer having a MEMS device or acoustic filter device is formed on a bottom surface of the semiconductor wafer. The second device layer is formed either by monolithic fabrication processes or layer-transfer processes.

Aspects of the present disclosure describe MOSFET devices that have snubber circuits. The snubber circuits comprise one or more resistors with a dynamically controllable resistance that is controlled by changes to a gate and/or drain potentials of the one or more MOSFET structures during switching events.

This invention discloses a semiconductor device disposed in a semiconductor substrate. The semiconductor device includes a first semiconductor layer of a first conductivity type on a first major surface. The semiconductor device further includes a second semiconductor layer of a second conductivity type on a second major surface opposite the first major surface. The semiconductor device further includes an injection efficiency controlling buffer layer of a first conductivity type disposed immediately below the second semiconductor layer to control the injection efficiency of the second semiconductor layer.

According to one embodiment, a semiconductor device is provided. The semiconductor device has a first region formed of semiconductor and a second region formed of semiconductor which borders the first region. An electrode is formed to be in ohmic-connection with the first region. A third region is formed to sandwich the first region. A first potential difference is produced between the first and the second regions in a thermal equilibrium state, according to a second potential difference between the third region and the first region.

A semiconductor structure is formed with first and second semiconductor wafers and a redistribution layer. The first semiconductor wafer is formed with a first active layer and a first interconnect layer. The second semiconductor wafer is formed with a second active layer and a second interconnect layer. The second semiconductor wafer is inverted and bonded to the first semiconductor wafer, and a substrate is removed from the second semiconductor wafer. The redistribution layer redistributes electrical connective pad locations on a side of the second semiconductor wafer. The redistribution layer also electrically contacts the first interconnect layer through a hole in the second active layer and the second interconnect layer.

A photo relay includes an illuminating unit, a photoelectric conversion IC, a first MOS IC and a second MOS IC. The illuminating unit receives an input signal to generate an illuminating signal. The photoelectric conversion IC receives the illuminating signal to generate a voltage control signal accordingly. The second MOS IC is reversely stacked on the first MOS IC, such that the source electrodes of the two MOS ICs are electrically connected, and the gate electrodes of the two MOS ICs are electrically connected through a gate connection structure for receiving the voltage control signal, and the drain electrodes of the two MOS ICs generate an output signal according to the received voltage control signal.