A display device includes a substrate having a first main surface on which a plurality of light emitting elements spaced apart from each other are provided and a second main surface located on a side opposite to the first main surface, a cooling unit having a third main surface and a fourth main surface located on a side opposite to the third main surface, a heat dissipation sheet located between the second main surface and the third main surface and in contact with the second main surface and the third main surface, and a connection portion arranged at a position sandwiching the heat dissipation sheet in a direction along the second main surface and bonded to each of the substrate and the cooling unit, and the connection portion is made of a heat shrinkable resin.

A monolithic array chip comprises a first semiconductor layer; a common electrode located on the first semiconductor layer; a first light-emitting unit with a first electrode located on the first semiconductor layer; a second light-emitting unit with a second electrode located on the first semiconductor layer; a third light-emitting unit with a third electrode located on the first semiconductor layer, wherein the first light-emitting unit, the second light-emitting unit, and the third light-emitting unit are separated from each other by a trench.

The present inventive concept relates to a stacked-RGB micro-light-emitting diode having corner mesa contact structures and a manufacturing method thereof. The stacked-RGB micro-light-emitting diode having corner mesa contact structures includes a first light-emitting structure, a first tunnel junction layer, a first anode layer, a second anode layer, a second tunnel junction layer, a second light-emitting structure, and a third light-emitting structure, which are sequentially stacked on a substrate. According to the present inventive concept, it is possible to increase the lifespan of the micro-light-emitting diode by forming the corner mesa contact structure on each of the light-emitting structures by etching a vertically-stacked structure.

In an output amplifier stage of an operational amplifier circuit, the first p-well of the first nMOSFET and the second p-well of the second nMOSFET are connected to the fourth node. Further, the first n-well of the first pMOSFET and the second n-well of the second pMOSFET are connected to the fifth node. At least one of the fourth node and the fifth node is connected to an output terminal VOUT.

A method of manufacturing a semiconductor device is provided. The method includes providing a substrate; forming a well region on the substrate; forming at least one first gate structure on the well region, wherein the first gate structure includes a gate insulating layer and a first gate electrode formed on the gate insulating layer, wherein the first gate electrode is formed having a first enclosed pattern on a surface of the well region; wherein an area inside the first enclosed pattern is defined as a first region, and an area outside the first enclosed pattern is defined as a second region; performing ion implantation on the first region such that the first region has a first conductivity type, and performing ion implantation on the second region such that the second region has a second conductivity type, wherein the first conductivity type and the second conductivity type are different.

A method for manufacturing a semiconductor device includes providing a substrate, performing an N-type dopant implantation into a first region of the substrate to form an N-well, removing a portion of the substrate to form a first set of fins on the N-well and a second set of fins on a second region of the substrate adjacent the N-well, filling gap spaces between the fins to form an isolation region, and performing a P-type dopant implantation into the second region to form a P-well adjacent the N-well. The N-well and the P-well are formed separately at different times. The loss of the P-type dopant ions due to the diffusion of P-type dopant ions in the P-well into the isolation region can be eliminated, and the damage to the fins caused by N-type dopant ions can be avoided.

A method of manufacturing a semiconductor device is provided. The method includes providing a substrate; forming a well region on the substrate; forming at least one first gate structure on the well region, wherein the first gate structure includes a gate insulating layer and a first gate electrode formed on the gate insulating layer, wherein the first gate electrode is formed having a first enclosed pattern on a surface of the well region; wherein an area inside the first enclosed pattern is defined as a first region, and an area outside the first enclosed pattern is defined as a second region; performing ion implantation on the first region such that the first region has a first conductivity type, and performing ion implantation on the second region such that the second region has a second conductivity type, wherein the first conductivity type and the second conductivity type are different.

A display device may include: a base layer including a display area and a non-display area; and a plurality of pixels provided on the display area, and each including a plurality of sub-pixels. Each of the sub-pixels may include a pixel circuit layer, and a display element layer including an emission area formed to emit light, and a non-emission area provided around a perimeter of the emission area. The display element layer may include: a partition wall provided on the emission area of each of the sub-pixels; a bank provided on the non-emission area of each sub-pixel, and disposed on a surface equal to a surface on which the partition wall is disposed; a first electrode and a second electrode provided on the partition wall and spaced apart from each other; and at least one light emitting element provided between the first and second electrodes in the emission area of each sub-pixel, and configured to emit the light.

A display device may include: a base layer including a display area and a non-display area; and a plurality of pixels provided on the display area, and each including a plurality of sub-pixels. Each of the sub-pixels may include a pixel circuit layer, and a display element layer including an emission area formed to emit light, and a non-emission area provided around a perimeter of the emission area. The display element layer may include: a partition wall provided on the emission area of each of the sub-pixels; a bank provided on the non-emission area of each sub-pixel, and disposed on a surface equal to a surface on which the partition wall is disposed; a first electrode and a second electrode provided on the partition wall and spaced apart from each other; and at least one light emitting element provided between the first and second electrodes in the emission area of each sub-pixel, and configured to emit the light.

Some embodiments relate to an integrated circuit (IC) device that includes a substrate including a P-well region and a dielectric structure. The dielectric structure is disposed at a surface of the substrate, extends downward into the substrate, and is located at a lateral perimeter of the P-well region. The IC device further includes a dielectric layer disposed over the P-well region and extends laterally over the dielectric structure. The IC device also includes an N+ gate structure disposed over the dielectric layer and includes at least one P+ region located over the P-well region of the substrate and the dielectric structure.