Logic devices and methods of manufacturing logic devices are provided. The semiconductor logic device includes an n-channel gate-all-around (n-GAA) field-effect transistor on a substrate integrated with a p-channel gate-all-around (p-GAA) field-effect transistor on the substrate adjacent to the n-channel gate-all-around (p-GAA) field-effect transistor. The n-channel gate-all-around (n-GAA) field effect-transistor has a structure including a plurality of layers comprising silicon and a corresponding plurality of layers comprising at least 25% germanium alternatingly arranged in stacked pairs extending between a source region and a drain region, and the p-channel gate-all-around (p-GAA) field-effect transistor has a plurality of layers comprising in a range of from 5% to 15% germanium and a corresponding plurality of layers comprising at least 25% germanium alternatingly arranged in stacked pairs.

An integrated circuit includes a plurality of active patterns including first and second active patterns each extending in a first direction and spaced apart from each other in a second direction intersecting with the first direction, a front wiring layer arranged above a front side of a substrate, a back wiring layer arranged on a backside of the substrate, and an island power tap cell arranged above the front side of the substrate. The island power tap cell includes first and second termination cells spaced apart from each other in the second direction, and a power tap cell arranged between the first and second termination cells and electrically connecting the back wiring layer to the front wiring layer. The first active pattern is cut above the first termination cell, and the second active pattern is cut above the second termination cell.

A semiconductor device is provided. The semiconductor device includes: first, second and third active patterns on a logic cell region of a substrate and are spaced apart from each other in a first direction; first and second gate electrodes, the first gate electrode crossing the first active pattern and the second gate electrode crossing the second active pattern; a first separation pattern provided between the first and second active patterns; a second separation pattern provided between the second and third active patterns; a first gate insulating layer interposed between the first gate electrode and the first active pattern; and a first gate cutting pattern interposed between the first and second gate electrodes, and in contact with a top surface of the first separation pattern. The first separation pattern is wider than the second separation pattern, and the first gate insulating layer extends between the first gate electrode and the first separation pattern, and contacts side and top surfaces of the first separation pattern.

A layout method is provided. A timing analysis is performed based on design data of a standard cell to classify a plurality of device units of the standard cell into a timing-critical group and a non-timing-critical group. A plurality of first sources regions in the device units of the non-timing-critical group are aligned with a plurality of second sources regions in the device units of the timing-critical group in a first direction in floorplan of the standard cell in a layout. The device units of the timing-critical group are arranged in a first row of a cell array and the device units of the non-timing-critical group are arranged in a second row of the cell array. The first and second rows of the cell array share a common power line. First active regions of the first row are wider than second active regions of the second row.

An integrated circuit device includes a first semiconductor substrate having a frontside surface and a backside surface opposite to each other, an FEOL structure on the frontside surface of the first semiconductor substrate, a first BEOL structure on the FEOL structure, a second BEOL structure on the backside surface of the first semiconductor substrate, and a second semiconductor substrate apart from the first semiconductor substrate in a vertical direction with the FEOL structure and the first BEOL structure The second semiconductor substrate is locally bonded to the first BEOL structure. The second semiconductor substrate includes a main surface facing the first BEOL structure, and the main surface of the second semiconductor substrate defines a local trench region in which trenches are defined in a regular pattern and local bonding areas bonded to the first BEOL structure.

A standard cell is formed between first and second power lines, lying astride a third power line. The spacing between the first and third power lines is greater than the spacing between the second and third power lines. The standard cell has a first logic circuit that receives an input A and outputs a signal to an internal node and a second logic circuit that receives the signal from the internal node and outputs an output Y. Transistors constituting the first logic circuit are formed in a region between the second and third power lines, and transistors constituting the second logic circuit are formed in a region between the first and third power lines.

A semiconductor device is provided. The semiconductor device includes: first, second and third active patterns on a logic cell region of a substrate and are spaced apart from each other in a first direction; first and second gate electrodes, the first gate electrode crossing the first active pattern and the second gate electrode crossing the second active pattern; a first separation pattern provided between the first and second active patterns; a second separation pattern provided between the second and third active patterns; a first gate insulating layer interposed between the first gate electrode and the first active pattern; and a first gate cutting pattern interposed between the first and second gate electrodes, and in contact with a top surface of the first separation pattern. The first separation pattern is wider than the second separation pattern, and the first gate insulating layer extends between the first gate electrode and the first separation pattern, and contacts side and top surfaces of the first separation pattern.

A semiconductor device includes a substrate including an N-stack cell, a buffer cell and an M-stack cell that are on the substrate, the buffer cell being between the N-stack and M-stack cells, an active pattern extending from the N-stack cell to the M-stack cell via the buffer cell, an N-stack channel pattern on the active pattern of the N-stack cell, an M-stack channel pattern on the active pattern of the M-stack cell, a dummy channel pattern on the active pattern of the buffer cell, an N-stack epitaxial pattern between the N-stack channel pattern and the dummy channel pattern, and an M-stack epitaxial pattern between the M-stack channel pattern and the dummy channel pattern. The N-stack channel pattern includes stacked N semiconductor patterns. The M-stack channel pattern includes stacked M semiconductor patterns. Each of N and M is an integer number of 2 or more, and M is greater than N.

A semiconductor device includes first cell transistors on a first cell region, second cell transistors on a second cell region spaced apart from the first cell region in a first direction, a first wiring group electrically connecting at least some of the first cell transistors to each other, a second wiring group electrically connecting at least some of the second cell transistors to each other. The first and second cell regions may be equal in size. The first wiring group may include a first through via and first wirings contacting upper and lower portions of the first through via. The second wiring group may include a second through via and second wirings contacting upper and lower portions of the second through via. Each of the first and second through vias may be on a center of a first interface region between the first and second cell regions.

A semiconductor structure and a method of fabricating thereof including a substrate having a device region and a dummy region. The device region includes a number of N-type device cells having a plurality of operational N-type transistors and a number of P-type device cells having a plurality of operational P-type transistors. The dummy region includes a number of N-type dummy cells having a plurality of non-operational N-type transistors and a number of P-type dummy cells having a plurality of non-operational P-type transistors, and a total number of the N-type device cells and P-type device cells is equal to a total number of the N-type dummy cells and P-type dummy cells.