H10D84/991

SEMICONDUCTOR LAYOUT IN FINFET TECHNOLOGIES
20260023912 · 2026-01-22 · ·

Systems, apparatuses, and methods for placing cells in an integrated circuit are described. In various embodiments, an integrated circuit is divided into many partitions. In a first set of partitions susceptible to transistor latch-up, the many transistor gate stripes are connected to one of the power rails rather than left floating. The lengths of the transistor gate stripes are shortened for well tap cells in the first partition, but increased in a second partition susceptible for poor signal integrity. One or more implant layers are formed underneath the transistor gate stripes in each of the first and second partitions to adjust an amount of protection against transistor latch-up and poor signal integrity. An electrostatic discharge transistor is included with at least one source region of multiple source regions formed in a well with a same doping polarity as the at least one source region.

SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
20260068317 · 2026-03-05 ·

A semiconductor device may include a substrate including a first well region comprising an impurity of a first conductivity type, first active patterns on the first well region and spaced apart from each other in a first direction parallel to a top surface of the substrate, second active patterns on the first well region and spaced apart from each other in the first direction, source/drain patterns on the first active patterns, the source/drain patterns comprising an impurity of a second conductivity type, and first impurity patterns on the second active patterns, the first impurity patterns comprising an impurity of the first conductivity type. A width of a top surface of each of the second active patterns in the first direction may be greater than a width of a top surface of each of the first active patterns in the first direction.

INTEGRATED CIRCUIT DEVICE
20260096207 · 2026-04-02 ·

An integrated circuit (IC) device includes a plurality of first taps arranged in a plurality of first columns and a plurality of first rows, and a plurality of second taps arranged in a plurality of second columns and a plurality of second rows. The plurality of second taps has a type different from the plurality of first taps. Each first tap of the plurality of first taps extends continuously across multiple rows of first active regions. Each second tap of the plurality of second taps extends continuously across multiple rows of second active regions. The second active regions have a type different from the first active regions. Along a column direction of the plurality of first columns and the plurality of second columns, no first tap among the plurality of first taps overlaps any second tap among the plurality of second taps.