A metal stack for templating the growth of AlN and ScAlN films is disclosed. The metal stack comprises one, two, or three layers of metal, each of which is compatible with CMOS post-processing. The metal stack provides a template that promotes the growth of highly textured c-axis {002} AlN and ScAlN films. The metal stacks include one or more metal layers with each metal layer having either a hexagonal {002} orientation or a cubic {111} orientation. If the metal stack includes two or more metal layers, the layers can alternate between hexagonal {002} and cubic {111} orientations. The use of ScAlN results in a higher piezoelectric constant compared to that of AlN for ScAlN alloys up to approximately 44% Sc. The disclosed metal stacks resulted in ScAlN films having XRD FWHM values of less than approximately 1.1° while significantly reducing the formation of secondary grains in the ScAlN films.

An ultrasonic transducer includes: two metal blocks; a plurality of piezoelectric elements having rectangular surfaces and stacked between the metal blocks; and bonding materials bonding the metal block and the piezoelectric element and the piezoelectric elements to each other. Thermal expansion coefficients in the diagonal directions from the center of the surface of the piezoelectric element to the four corners thereof are equal to each other.

The present invention is one which prevents the occurrence of cracks in piezo elements and reduces the thermal effects on the control board, and comprises a fluid control valve driven by a piezo actuator, a fluid sensor which measures the pressure or flow rate of the fluid, a control board which controls the fluid control valve based on the measured value measured by the fluid sensor, and a discharge resistor provided on a component different from the control board.

Provided is a method for inspecting a piezoelectric element in which voltage is applied to a piezoelectric element and evaluation of the electrical characteristics of the piezoelectric element is performed. The method includes a first step in which the piezoelectric element is held on a flat plate-shaped slightly adhesive sheet and a second step in which voltage is applied to the piezoelectric element held on the slightly adhesive sheet and evaluation of the electrical characteristics of the piezoelectric element is performed.

A piezoelectric multilayer component having a stack of sintered piezoelectric layers and inner electrodes arranged between the piezoelectric layers. A region which has poling cracks is present on the surface of at least one electrode, and the poling cracks are separated from a surface of at least one of the inner electrodes by the region having the poling cracks.

The piezoelectric element comprises a piezoelectric body extending in a lateral direction and a first and second electrodes that are provided on the piezoelectric body. The piezoelectric body has an active portion sandwiched between the first and second electrodes in a thickness direction that is vertical to the lateral direction, and an inactive portion connected to the active portion in the lateral direction. The first electrode has an active electrode portion disposed on the active portion. The active electrode portion includes an interface region that is adjacent to the interface of the active portion and the inactive portion in the lateral direction, and an inner region that is separated from the interface of the active portion and the inactive portion in the lateral direction. The cross sectional surface area per unit length of the interface region in the cross section of the active electrode portion is greater than the cross sectional area per unit length of the inner region.

An array of piezoelectric micromachined ultrasonic transducers (PMUTs) includes a first piezoelectric layer and a second piezoelectric layer, a dielectric layer positioned between the first piezoelectric layer and the second piezoelectric layer, and a plurality of conductive layers positioned on opposing surfaces of the first piezoelectric layer and opposing surfaces of the second piezoelectric layer. A plurality of isolation trenches extend through the dielectric layer and at least a portion of conductive layers of the plurality of conductive layers, where the plurality of isolation trenches are positioned between neighboring PMUTs of the array of PMUTs such that the neighboring PMUTs are electrically isolated, and wherein the plurality of isolation trenches relieve stress in the dielectric layer.

For a piezoelectric device, an optical characteristic and/or a piezoelectric characteristic is improved. A piezoelectric device has a first electrode layer, a second electrode layer, and a piezoelectric layer provided between the first electrode layer and the second electrode layer, wherein the piezoelectric layer is formed of a wurtzite crystal material as a main component, to which one or more elements is/are added, said one or more elements being transparent when turned into an oxide, and wherein a haze value is 3% or less, and transmittance with respect to light having a wavelength of 380 nm is 50% or more.

A method for producing a ceramic multilayer element is disclosed. In an embodiment the method includes forming a plurality of multilayer segments in a green state, wherein each multilayer segment is formed by pressing together a plurality of ceramic layers in the green state and pressing together the multilayer segments in the green state to form a multilayer element that is in the green state. The method further includes sintering the multilayer element that is in the green state to form a ceramic multilayer element that includes the ceramic layers and electrode layers arranged one on top of another, wherein at least one or more of a temperature at which the multilayer segments are pressed together, a pressing force applied during the pressing of the multilayer segments, and/or a duration of the pressing of the multilayer segments are adjusted.

Various embodiments of the present disclosure are directed towards an integrated chip including a dielectric structure sandwiched between a first electrode and a bottom electrode. A passivation layer overlies the second electrode and the dielectric structure. The passivation layer comprises a horizontal surface vertically below a top surface of the passivation layer. The horizontal surface is disposed above a top surface of the dielectric structure.