Broadband power coupling/decoupling network for PoDL

Abstract

A Power Over Data Lines (PoDL) system includes Power Sourcing Equipment (PSE) supplying DC power and Ethernet data over a single twisted wire pair to a Powered Device (PD). The PSE supplies the DC current and AC data through a cascaded coupling network including a series of AC-blocking inductor stages having different inductances to substantially filter out the AC component and pass the DC component. The data is supplied to the wires via capacitors. The PD may have a matched decoupling network for providing the separated DC power and data to a PD load.

Claims

1. A Power over Data Lines (PoDL) system for supplying power and data over a wire pair, the wire pair being a first wire and a second wire coupled to a powered device, the system comprising: a DC voltage source having a first voltage source terminal and a second voltage source terminal, where a DC voltage is across the first voltage source terminal and the second voltage source terminal; a first series combination of two or more inductors having a first terminal coupled to the first voltage source terminal, the series combination of inductors also having a second terminal outputting a first filtered DC voltage for coupling to the first wire, wherein the first series combination comprises a first inductor, having the first terminal, and a second inductor, having the second terminal, wherein the first inductor has a first inductance greater than a second inductance of the second inductor; a second series combination of two or more inductors having a third terminal coupled to the second voltage source terminal, the second series combination of inductors also having a fourth terminal outputting a second filtered DC voltage for coupling to the second wire, wherein the second series combination comprises a third inductor, having the third terminal, and a fourth inductor, having the fourth terminal, wherein the third inductor has an inductance approximately equal to the first inductance, and wherein the fourth inductor has an inductance approximately equal to the second inductance; a differential data transceiver having a first data terminal and a second data terminal; a first capacitor having a fifth terminal coupled to the first data terminal, the first capacitor having a sixth terminal for coupling to the first wire to combine data with the first filtered DC voltage; and a second capacitor having a seventh terminal coupled to the second data terminal, the second capacitor having an eighth terminal for coupling to the second wire to combine the data with the second filtered DC voltage.

2. The system of claim 1 further comprising a third capacitor coupled between the first series combination and the second series combination.

3. The system of claim 2 further comprising the third capacitor, in series with a first resistor, coupled between the first series combination and the second series combination.

4. The system of claim 1 wherein the differential data transceiver is coupled to the first capacitor and the second capacitor via termination resistors.

5. The system of claim 1 further comprising the powered device.

6. The system of claim 5 wherein the powered device is coupled to receive the data and voltage over the first wire and the second wire, the powered device having a decoupling network separating the DC voltage from the data on the first wire and the second wire, the decoupling network comprising inductors matched to the first series combination of two or more inductors and to the second series combination of two or more inductors, the decoupling network also comprising capacitors matched to the first capacitor and the second capacitor.

7. The system of claim 1 where two or more of the inductors in the first series combination and the second series combination are mutually coupled.

8. The system of claim 1 where one or more of the inductors are formed using traces on a printed circuit board.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 illustrates a conventional PoDL-enabled Ethernet system using a single wire pair for supplying power and data to the PD.

(2) FIG. 2 illustrates a known 4 stage broadband bias tee for use with coaxial cables, which is unsuitable for PoDL using a twisted wire pair.

(3) FIG. 3 illustrates a cascaded coupling network for a PSE for coupling DC (power) and wide bandwidth PHY AC data to a twisted wire pair, in accordance with one embodiment of the invention.

(4) FIG. 4 is a graph, obtained by simulation of the coupling/decoupling network of FIG. 3, showing return loss (with 100 Ωreference impedance) vs frequency.

(5) Elements that are the same or equivalent are labeled with the same numeral.

DETAILED DESCRIPTION

(6) FIG. 3 illustrates a cascaded coupling network 30 in a PSE 32 for coupling a DC power signal (e.g., 12 volts), generated by a DC voltage source 34, to a twisted wire pair 14, and for also coupling a differential AC data signal, generated by the PHY 36, to the wire pair 14. The PHY 36 includes a differential data transceiver that generates and receives the AC data at any frequency within the bandwidth of the system. Such transceivers may be conventional and need not be described. The DC signals are blocked from the PHY 36, and the AC signals are blocked from the DC source. The polarities of the signals may be the opposite shown since the circuitry is the same for each wire.

(7) Along the top conductor path, which may include printed circuit board traces or wires, the positive DC voltage (relative to the other DC voltage terminal) is applied to a 33 uH inductor L1, which may have, for example, a parasitic capacitance C.sub.L1 of 5.25 pF (picofarad). Downstream from the inductor L1 is a 1 uH inductor L3, which may have, for example, a lower parasitic capacitance C.sub.L3 of 262 fF (femtofarad). The self-resonant frequency (SRF) for the inductor L3 is much higher than that of the inductor L1.

(8) Along the bottom wire, which may include printed circuit board traces or wires, a circuit that is a minor image of the top wire circuit is provided. The mirrored inductors may have a common core to increase inductance and improve matching for better rejection of common mode current. Specifically, the negative DC voltage is applied to a 33 uH inductor L2, which may have, for example, a parasitic capacitance C.sub.L2 of 5.25 pF (picofarad). Downstream from the inductor L2 is a 1 uH inductor L4, which may have, for example, a parasitic capacitance C.sub.L4 of 262 fF (femtofarad).

(9) A 2 k ohm resistor R3 and 5 pF capacitor C3 are connected in shunt between the inductors L1 and L2 and the inductors L3 and L4 to damp out resonant interaction between the L1-L4 inductors.

(10) The inductors L1-L4 pass the DC voltage. The DC voltage is applied to the twisted wire pair 14 at the output terminals 38 of the PSE 32.

(11) The AC differential data signal, generated by the differential data transceiver in the PHY 36, is AC-coupled to the twisted wire pair 14 via the 1 uF capacitors C1 and C2. The capacitors C1 and C adequately block the DC voltage generated by the DC voltage source 34. The data may be coupled to the capacitors C1 and C2 via termination resistors, if required.

(12) FIG. 4 is a graph 40 of return loss (in dB with 100 Ωreference impedance) versus the frequency, obtained by simulating the coupling network 30 in the PSE 32. A 20 dB return loss is large, and the graph 40 shows that the data bandwidth of about 1 MHz-1 GHz incurs greater than a 20 dB return loss. In contrast, graph 42 shows what the return loss vs.

(13) frequency would be with only the 33 uH inductor used . Similarly, the graph 44 shows what the return loss vs. frequency would be with only the 1 uH inductor used. The graph 40 represents a much wider range of practical data frequencies.

(14) A PD connected to the wire pair 14 would have a decoupling network with the same components as the coupling network 30, with the DC power terminals of the PD load coupled to the outputs of the inductors L1 and L2 and the differential data terminals of the PD load coupled to the output terminals of the capacitors C1 and C2. The PD includes a differential data transceiver coupled to the capacitors C1 and C2. Termination resistors may be used as needed.

(15) Although the values shown in the figures are considered optimal for a particular application, other values may be optimal for other applications. Although the manufacturer should attempt to perfectly match the inductors for each of the wires for maximum rejection of common mode currents, it is understood that the inductors can only be approximately matched.

(16) Additional AC-blocking stages in the power path with descending inductor values may be connected to the right of the inductor L3/L4 to obtain a wider bandwidth. In one example, each stage has an inductance that is at least 1/10 that of the previous stage.

(17) The small 1 uH inductors L3/L4 may be formed by a trace pattern on a printed circuit board on which the remainder of the network is mounted. Using such traces for the inductor winding may reduce the parasitic capacitance to desirably increase the SRF beyond the highest expected frequency of the data signal.

(18) Where possible, opposing inductor pairs should be wound on a common core in order to conserve core material and improve matching for better rejection of common mode current in the twisted wire pair.

(19) While particular embodiments of the present invention have been shown and described, it will be obvious to those skilled in the art that changes and modifications may be made without departing from this invention in its broader aspects and, therefore, the appended claims are to encompass within their scope all such changes and modifications.