I/Q imbalance correction for the combination of multiple radio frequency frontends
09780991 · 2017-10-03
Assignee
Inventors
Cpc classification
H04L27/364
ELECTRICITY
International classification
Abstract
Aspects relate to correcting Inphase/Quadrature (I/Q) imbalances across multiple wireless elements such as multiple receive elements or multiple transmit elements. In one example implementation, I/Q imbalances can be corrected using a digital circuit provided within a digital portion of a direct conversion wireless element (upconversion or downconversion) that implements only two multiplications and one addition per pair of I and Q samples.
Claims
1. A method of receiving Inphase and Quadrature (I/Q) signal components in a Radio Frequency (RF) communication system, comprising: at each of a plurality of elements, receiving an RF signal to produce an analog signal comprising Inphase and Quadrature components, mixing an Inphase local oscillator signal with the received analog signal to produce an Inphase signal component, mixing a quadrature phase offset local oscillator signal with the received analog signal to produce a Quadrature signal component, and filtering each of the Inphase and Quadrature signal components; combining the respective filtered Inphase components and combining the respective filtered Quadrature components; digitizing each of the combined Inphase components and the combined Quadrature components; and applying a respective correction factor to each of the combined Inphase components and the combined Quadrature components, the correction factors calculated to compensate for an imbalance between the combined Inphase components and the combined Quadrature components, wherein each correction factor comprises a phase shift and scale factor, and wherein the applying includes no more than two multiplications and one addition for each pair of Inphase and Quadrature samples.
2. The method of claim 1, wherein the correction factors are determined by applying a phase rotation to the combined Inphase components and the combined Quadrature components to produce a 2×2 correction matrix with one entry having a value of 0 and another entry having a value of 1, and the applying comprises performing a matrix multiplication between the combined Inphase components and the combined Quadrature components and the 2×2 correction matrix.
3. The method of claim 1, wherein the 2×2 correction matrix is
4. The method of claim 3, wherein
5. The method of claim 3, wherein
6. The method of claim 1, wherein the 2×2 correction matrix is equivalent to
7. The method of claim 6, wherein the 2×2 correction matrix is
8. The method of claim 6, wherein the 2×2 correction matrix is
9. The method of claim 6, wherein the 2×2 correction matrix is
10. A method of transmitting a signal with Inphase and Quadrature (I/Q) signal components in a Radio Frequency (RF) communication system, comprising: applying a respective correction factor to Inphase (I) and Quadrature (Q) components of a digital signal, each correction factor calculated to compensate for an imbalance between the I component and the Q component, wherein each correction factor comprises a phase shift and scale factor, and wherein the applying includes no more than two multiplications and one addition total for each pair of I and Q samples; converting the corrected I and Q components to analog; splitting the corrected I component to a plurality of transmit paths with different analog I components; splitting the corrected Q component to a plurality of transmit paths with different analog Q components; mixing the different analog I components with an Inphase local oscillator signal, mixing the different analog Q components with a quadrature phase offsetted oscillator signal, and transmitting each of the mixed Q and I components from the plurality of transmit paths.
11. The method of claim 10, wherein the 2×2 correction matrix is
12. The method of claim 10, wherein the 2×2 correction matrix is equivalent to
13. A method of correcting imbalance between Inphase (I) and Quadrature (Q) (I/Q) signal components in an Radio Frequency (RF) communication system with multiple front ends, comprising: providing a correction matrix based on gain and phase differences between I and Q components of a digital signal, the correction matrix having two rows and two columns, wherein one entry is zero, one entry is 1, and the remaining values are constants that are pre-calculated based on an I/Q imbalance; matrix multiplying the correction matrix with I and Q sample components of the digital signal to produce corrected I and Q components; if transmitting the digital signal, converting the corrected I and Q components to analog components, mixing with a respective Local Oscillator to produce mixed I and Q components and transmitting the mixed I and Q components through multiple front ends, and if receiving, converting multiple versions of an analog signal received through multiple front ends into respective baseband I and Q components, digitizing the baseband I and Q components, combining the respective digitized baseband I and Q components, and performing the matrix multiplication on the combined baseband I and Q components.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
(1)
(2)
(3)
DETAILED DESCRIPTION
(4) To better use limited bandwidth in wireless communication, both amplitude and phase of a RF carrier can be modulated with data. Amplitude and phase information may be expressed in a complex number with Inphase (real part) and Quadrature (imaginary part) signal components. In a system with imbalance between I and Q paths, an input signal, s.sub.in=I+jQ, has a corresponding output signal s.sub.out=I′+jQ′ that may be different from the input signal. Such input and output relationship applies to both upconversion at a transmitter and downconversion at a receiver. Likewise aspects of the present disclosure apply to both upconversion and downconversion, and systems that perform one or more of upconversion and downconversion. For clarity of explanation, this disclosure focuses primarily on an example of correcting I/Q imbalances in downconversion and those of ordinary skill in the art would be able to use these teachings in the context of upconversion also. The upconversion and downconversion operations can be modeled as a matrix transpose from each other.
(5) In a downconverter, the relationship between input and output can be described by the transfer matrix (1), where g is gain imbalance (other than unity) and phase imbalance is θ:
(6)
(7) In an example upconverter, an input to output relationship can be described by the transfer matrix (2):
(8)
(9) In both (1) and (2), the amplitude gain of I/Q branches are g and 1/g, respectively, giving a gain imbalance of 40 log.sub.10 g in decibel scale, while the phase imbalance is θ. The transfer matrices in (1) and (2) are the transpose of each other.
(10) The I/Q imbalance can be corrected in both an upconverter- and in a downconverter. For an upconverter, other than a constant factor, the I/Q signals can be corrected using a correction matrix (3)
(11)
(12) The correction matrix (3) is similar to that in (1) with gain imbalance of 1/g and phase imbalance is −θ. A constant factor that is uncorrected does not affect the system performance. For upconverter, the matrix (3) should be used to correct the signal before the RF mixer. Preferably, such correction would be performed in a digital portion of the circuit (as opposed to an analog implementation but analog implementation may not be excluded). A correction matrix equivalent to correction matrix (3) can be used in an upconverter.
(13) For a downconverter, except for a constant factor, an I/Q signal imbalance can be corrected using correction matrix (4):
(14)
(15) In a downconverter according to
(16) In wireless communication, a shift of a constant phase does not affect the system performance. In the transfer matrices of (1) and (4), phase shift is equivalent to a rotation of the matrix. With phase rotation and/or scaling, the correction matrix (4) for a downcoverter is equivalent to any of the following simplifications:
(17)
where the coefficient of “0” does not require both addition and multiplication, and the coefficient of “1” does not require multiplication.
(18) In practical implementation, with known amplitude imbalance of g and phase imbalance of θ and some pre-calculations, I/Q imbalance correction in digital circuitry requires two multiplications and one addition for each pair of I and Q samples (samples produced by sampling each of the I and Q components). I/Q imbalance correction for the downconverter of
(19)
(20) Other choices are possible without increased implementation complexity. There are multiple choices that need two multiplications and one addition.
(21) As shown earlier, I/Q imbalance (and correction) for upconverter and downcoverter are transposes of each other in their corresponding matrix representation. The correction matrix (5) is applicable for both upconverter and downconverter with the correct matrix transpose.
(22)
(23) The combiner 320a/320b before each ADC may have difference in amplitude level, represented by respective amplitude gain levels γ.sub.k, for k=1, . . . , N. As such, the input and output relationship is (I′, Q′ correspond respectively to I and Q, with an imbalance.)
(24)
or, in general,
(25)
(26) For (8), I/Q correction can compensate the signal up to a phase shift and scale factor. First of all, up to a scale factor equal to AD−BC, the overall I/Q imbalance can be corrected using the correction matrix of
(27)
(28) If the output signal is rotated with a phase of ψ=−tan.sup.−1(C/D), the overall correction matrix (9) is equivalent to
(29)
(30) With this simplification, the I/Q imbalance can be corrected with
(31)
using the I/Q correction block of
(32) Other alternatives are possible with other pre-calculation steps. In additional to (10), the correction matrix (9) is also equivalent to each of the following matrices:
(33)
(34) Other than pre-calculations, all of these correction matrices can be implemented in a digital system using circuitry that implements only two multiplications and one addition. Such digital circuitry can be implemented as a Digital Signal Processor (DSP) programmed to execute a sequence of instructions to perform a process according to the disclosure. Such instructions can be obtained from a non-transitory machine readable medium. The DSP can receive data samples being operated through data path or from memory, for example.
(35) While not separately depicted, for multiple RF chips in an upconverter for a transmitter, a correction matrix that is a transpose to the correction matrix (8) can be used. In other implementations, a correction matrix that is a transpose to any of the correction matrices (12)-(14) also could be used.
(36)
(37)
(38) Embodiments of the invention may be implemented as (analog, digital, or a hybrid of both analog and digital) circuit-based processes, including possible implementation as a single integrated circuit (such as an ASIC or an FPGA), a multi-chip module, a single card, or a multi-card circuit pack. As would be apparent to one skilled in the art, various functions of circuit elements may also be implemented as processing blocks in a software program. Such software may be employed in, for example, a digital signal processor, micro-controller, general-purpose computer, or other processor.
(39) Integrated circuits have become increasingly complex. Entire systems are constructed from diverse integrated circuit sub-systems. Describing such complex technical subject matter at an appropriate level of detail becomes necessary. In general, a hierarchy of concepts is applied to allow those of ordinary skill to focus on details of the matter being addressed.
(40) Describing portions of a design (e.g., different functional units within an apparatus or system) according to functionality provided by those portions is often an appropriate level of abstraction, since each of these portions may themselves comprise hundreds of thousands, hundreds of millions, or more elements. When addressing some particular feature or implementation of a feature within such portion(s), it may be appropriate to identify substituent functions or otherwise characterize some sub-portion of that portion of the design in more detail, while abstracting other sub-portions or other functions.
(41) A precise logical arrangement of the gates and interconnect (a netlist) implementing a portion of a design (e.g., a functional unit) can be specified. How such logical arrangement is physically realized in a particular chip (how that logic and interconnect is laid out in a particular design) may differ in different process technologies and/or for a variety of other reasons. Circuitry implementing particular functionality may be different in different contexts, and so disclosure of a particular circuit may not be the most helpful disclosure to a person of ordinary skill. Also, many details concerning implementations are often determined using design automation, proceeding from a high-level logical description of the feature or function to be implemented. In various cases, describing portions of an apparatus or system in terms of its functionality conveys structure to a person of ordinary skill in the art. As such, it is often unnecessary and/or unhelpful to provide more detail concerning a portion of a circuit design than to describe its functionality.
(42) Functional modules or units may be composed of circuitry, where such circuitry may be fixed function, configurable under program control or under other configuration information, or some combination thereof. Functional modules themselves thus may be described by the functions that they perform, to helpfully abstract how some of the constituent portions of such functions may be implemented. In some situations, circuitry, units, and/or functional modules may be described partially in functional terms, and partially in structural terms. In some situations, the structural portion of such a description may be described in terms of a configuration applied to circuitry or to functional modules, or both.
(43) Configurable circuitry is effectively circuitry or part of circuitry for each different operation that can be implemented by that circuitry, when configured to perform or otherwise interconnected to perform each different operation. Such configuration may come from or be based on instructions, microcode, one-time programming constructs, embedded memories storing configuration data, and so on. A unit or module for performing a function or functions refers, in some implementations, to a class or group of circuitry that implements the functions or functions attributed to that unit. Identification of circuitry performing one function does not mean that the same circuitry, or a portion thereof, cannot also perform other functions concurrently or serially.
(44) Although circuitry or functional units may typically be implemented by electrical circuitry, and more particularly, by circuitry that primarily relies on transistors fabricated in a semiconductor, the disclosure is to be understood in relation to the technology being disclosed. For example, different physical processes may be used in circuitry implementing aspects of the disclosure, such as optical, nanotubes, micro-electrical mechanical elements, quantum switches or memory storage, magnetoresistive logic elements, and so on. Although a choice of technology used to construct circuitry or functional units according to the technology may change over time, this choice is an implementation decision to be made in accordance with the then-current state of technology.
(45) Embodiments according to the disclosure include non-transitory machine readable media that store configuration data or instructions for causing a machine to execute, or for configuring a machine to execute, or for describing circuitry or machine structures (e.g., layout) that can execute or otherwise perform, a set of actions or accomplish a stated function, according to the disclosure. Such data can be according to hardware description languages, such as HDL or VHDL, in Register Transfer Language (RTL), or layout formats, such as GDSII, for example.
(46) It should be appreciated by those of ordinary skill in the art that any block diagrams herein represent conceptual views of illustrative circuitry embodying the principles of the invention. Similarly, it will be appreciated that any flow charts, flow diagrams, state transition diagrams, pseudo code, and the like represent various processes which may be substantially represented in computer readable medium and so executed by a computer or processor, whether or not such computer or processor is explicitly shown.
(47) It will be further understood that various changes in the details, materials, and arrangements of the parts which have been described and illustrated in order to explain embodiments of this invention may be made by those skilled in the art without departing from embodiments of the invention encompassed by the following claims.