Methods and apparatus for level-shifting high speed serial data with low power consumption

Abstract

A driver circuit for driving a transmission line, such as a cable or a metal trace on a printed circuit board is described. The driver may be configured to drive lines with voltages exceeding the maximum voltage than a transistor can withstand for a given fabrication node. The driver may be configured to receive a supply voltage larger than that indicated by manufacturers. The driver may use a fast path and a slow path. Signals provided by the slow path and the fast path may be combine to adapt the input signals to levels that do cause stress to a transistor. A plurality of drivers of the type described herein may be used to provide digital-to-analog conversion.

Claims

1. A circuit comprising: a first transistor having a first control terminal and a first output terminal; a second transistor having a second control terminal and a second output terminal; a third transistor having a third output terminal coupled to the first output terminal; a fourth transistor having a fourth output terminal coupled to the second output terminal; a first driving stage connected to the first control terminal, the first driving stage comprising a first driver having a first speed and a second driver having a second speed slower than the first speed; and a second driving stage connected to the second control terminal, the second driving stage comprising a third driver having a third speed and a fourth driver having a fourth speed slower than the third speed.

2. The circuit of claim 1, wherein the first driver comprises at least one fifth transistor having a first gate dielectric, the first gate dielectric having a first thickness, and the second driver comprises at least one sixth transistor having a second gate dielectric, the second gate dielectric having a second thickness higher than the first thickness.

3. The circuit of claim 1, wherein the first driver is connected to the first control terminal through a first capacitor and the third driver is connected to the second control terminal through a second capacitor.

4. The circuit of claim 1, wherein the first and second transistors are PMOS transistors, and the third and fourth transistors are NMOS transistors.

5. The circuit of claim 1, wherein the first output terminal is configured to be coupled to a first input terminal of a transmission line and the second output terminal is configured to be coupled to a second input terminal of the transmission line.

6. The circuit of claim 5, wherein the first and the second output terminals are configured to provide a differential signal to the transmission line.

7. The circuit of claim 1, further comprising a fifth driver coupled to the third transistor and a sixth driver coupled to the fourth transistor.

8. The circuit of claim 1, wherein the first driver is configured to receive a first supply voltage and a second supply voltage lower than the first supply voltage, and the second driver is configured to receive a third supply voltage and a fourth supply voltage lower than the third supply voltage, wherein the third supply voltage is higher than the first supply voltage and the fourth supply voltage is higher than the second supply voltage.

9. The circuit of claim 8, wherein the first and second transistors are configured to receive the third supply voltage, and the third and fourth transistors are configured to receive the second supply voltage.

10. The circuit of claim 8, further comprising a fifth driver coupled to the third transistor and a sixth driver coupled to the fourth transistor, wherein the fifth and the sixth drivers are configured to receive the first supply voltage and the second supply voltage.

11. The circuit of claim 1, wherein the first driving stage in coupled to an input terminal and the second driving stage is coupled to the input terminal through an inverter.

12. The circuit of claim 1, wherein the second driver comprises latch circuit.

13. A circuit for driving a transmission line, the circuit comprising: a first transistor having a control terminal and a first output terminal; a second transistor having a second output terminal coupled to the first output terminal; and a driving stage connected to the control terminal, the driving stage comprising a first driver having a first speed and a second driver having a second speed slower than the first speed.

14. The circuit of claim 13, wherein the first driver and the second driver are configured to receive a common input signal.

15. The circuit of claim 13, wherein the first driver comprises at least one fifth transistor having a first gate dielectric, the first gate dielectric having a first thickness and the second driver comprises at least one sixth transistor having a second gate dielectric, the second gate dielectric having a second thickness higher than the first thickness.

16. The circuit of claim 13, wherein the first driver is connected to the control terminal through a capacitor.

17. The circuit of claim 13, wherein the first transistor is a PMOS transistor, and the second transistor is an NMOS transistor.

18. The circuit of claim 13, wherein the first driver is configured to receive a first supply voltage and a second supply voltage lower than the first supply voltage, and the second driver is configured to receive a third supply voltage and a fourth supply voltage lower than the third supply voltage, wherein the third supply voltage is higher than the first supply voltage and the fourth supply voltage is higher than the second supply voltage.

19. The circuit of claim 17, wherein the first transistor is configured to receive the third supply voltage, and the second transistor is configured to receive the second supply voltage.

20. The circuit of claim 17, further comprising a third driver coupled to the second transistor, wherein the third driver is configured to receive the first supply voltage and the second supply voltage.

Description

BRIEF DESCRIPTION OF DRAWINGS

(1) The accompanying drawings are not intended to be drawn to scale. In the drawings, each identical or nearly identical component that is illustrated in various figures is represented by a like numeral. For purposes of clarity, not every component may be labeled in every drawing.

(2) FIG. 1 is a circuit diagram illustrating a line driver.

(3) FIG. 2 is a circuit diagram illustrating a line driver, according to some embodiments.

(4) FIG. 3A is a plot illustrating an exemplary input signal, according to some embodiments.

(5) FIG. 3B is a plot illustrating an exemplary waveform provided at node A of the line driver of FIG. 2, according to some embodiments.

(6) FIG. 3C is a plot illustrating an exemplary waveform provided at node B of the line driver of FIG. 2, according to some embodiments.

(7) FIG. 3D is a plot illustrating an exemplary waveform provided at node C of the line driver of FIG. 2, according to some embodiments.

(8) FIG. 4A-4B are schematic diagrams illustrating exemplary transistors having different gate dielectric thicknesses, according to some embodiments.

(9) FIG. 5 is a circuit diagram illustrating an exemplary latch circuit, according to some embodiments.

(10) FIG. 6 is a block diagram illustrating an exemplary digital-to-analog converter (DAC), according to some embodiments.

DETAILED DESCRIPTION

(11) Voltage mode drivers have the advantage of consuming less power, compared to some other types of line drivers. Accordingly, voltage mode drivers are used to drive transmission lines in a variety of applications. However, the inventor has appreciated a challenge in the design of voltage mode drivers that has arisen as the size of integrated transistors decreases (e.g., at smaller transistor fabrication “nodes”). In particular, smaller transistors may be less able to handle the voltage stresses needed to drive the required voltages on a transmission line. Applying a voltage to the transistors greater than that which they are designed to withstand risks damage to the transistors and/or may cause unacceptably high leakage current. However, smaller fabrication nodes provide the opportunity to drive electronic circuits at higher data rates. Accordingly, as the demand for bandwidth increases, circuit designers have an incentive to migrate to smaller fabrication nodes.

(12) FIG. 1 shows an example of a voltage mode driver 100. Voltage mode driver 100 includes transistors M.sub.1, M.sub.2, M.sub.3 and M.sub.4 and four resistors R. Resistor R.sub.out represents the impedance of the transmission line driven by the voltage mode driver 100. The voltage used to drive a signal through a transmission line is often specified by a standard. A transmission line voltage level specified according to a standard will be referred to herein as the “line level.” As an example, a standard may specify a line level of 1V peak-to-peak (1Vpp). To supply a line level of 1Vpp, the voltage mode driver 100 needs to have the capability of producing a voltage of 1V across R.sub.out. To do so, the supply voltage of the voltage mode driver 100 needs to be at least 1V. However, fabrication nodes are decreasing in size to the point where the transistors are no longer capable of withstanding a supply voltage of 1V. As an example, a manufacturer may specify that the maximum voltage that can be supplied to a transistors fabricated using a 16 nm-fabrication node is 1.05V. As another example, a manufacturer may specify that the maximum voltage that can be supplied to a circuit fabricated using a 7 nm-fabrication node is 0.75V. Providing a voltage to the transistor (e.g., across the gate and source of a MOSFET) higher than the maximum specified by the manufacturer risks causing damage to the transistors and/or high leakage current. Reducing the supply voltage may not be an acceptable solution, as reducing the supply voltage of voltage mode driver 100 does not allow supplying a signal of 1Vpp.

(13) FIG. 1 illustrates applying a supply voltage of 0.75V to voltage mode driver 100. In this example, the resistance of resistors R is 50Ω and R.sub.out has an impedance of 100Ω. Transistors M.sub.1 and M.sub.2 are PMOS transistors, and M.sub.3 and M.sub.4 are NMOS transistors. The drain of each transistor is coupled to a terminal of R.sub.out through a resistor R. The sources of transistors M.sub.1 and M.sub.2 are provided with a 0.75V supply voltage, which is equal to the maximum supply voltage specified by the manufacturer, and the sources of transistors M.sub.3 and M.sub.4 are grounded. If the gates of transistors M.sub.1 and M.sub.3 are driven with zero voltage and transistors M.sub.2 and M.sub.4 are driven with 0.75V, the voltages appearing at the terminals of R.sub.out are equal to 0.5625V and 0.1875V respectively. In this case, the voltage difference at the terminals of R.sub.out is 0.5625V−0.1875V=0.375V. In case of driving a signal of opposite polarity, the voltage across the terminals of R.sub.out are equal to 0.1875V and 0.5625V respectively. In this case, the voltage difference at the terminals of R.sub.out is 0.1875V−0.5625V=−0.375V. Toggling between −0.375V and 0.375V, R.sub.out exhibits a 0.75Vpp.

(14) The present inventor has developed circuits and associated techniques that allow supplying the desired line voltage while keeping the voltage of the transistors(s) within their voltage limits. In some embodiments, the supply voltage can exceed the voltage limits of the transistors. To allow the transistors to withstand the supply voltage, a control signal is applied to a control terminal of a transistor through parallel control paths (e.g., fast and slow control paths) that respond to the control signal with different speeds. The way in which the parallel control paths allow the transistors to withstand the voltage will be described with reference to FIG. 2.

(15) FIG. 2 is a block diagram illustrating a line driver 200 with parallel control paths of different speeds, according to some embodiments. Line driver 200 includes transistors M.sub.1, M.sub.2, M.sub.3 and M.sub.4, resistors R.sub.1, R.sub.2, R.sub.3 and R.sub.4, drivers D.sub.1, D.sub.2, D.sub.1′, D.sub.2′, D.sub.3 and D.sub.4 and capacitors C.sub.1 and C.sub.2. Driver D.sub.1′ serves as slow control path 210, and driver D.sub.1 and capacitor C.sub.1 serve as fast control path 211. In some embodiments, transistor M.sub.1 and M.sub.2 are PMOS transistors, and M.sub.3 and M.sub.4 are NMOS transistors. However, the present invention is not limited to MOS transistors, and any other suitable type of transistor may be used, including bipolar junction transistors (BJT), heterojunction bipolar transistor (HBT), junction field effect transistor (JFET), etc. The transistors of line driver 200 may be fabricated using any suitable fabrication node, such as less than or equal to 45 nm, less than equal to 32 nm, less than equal to 22 nm, less than equal to 16 nm, less than equal to 14 nm, less than equal to 10 nm, less than equal to 7 nm or less than equal to 5 nm.

(16) Transistors M.sub.3 and M.sub.4 may be coupled to supply voltage V.sub.LL, for example, through the respective source terminals, while transistors M.sub.1 and M.sub.2 may be coupled to supply voltage V.sub.HH, through the respective source terminals, for example. In some embodiments, the drain of transistor M.sub.1 may be coupled to the output terminal labeled V.sub.out.sup.+ through resistor R.sub.1, and the drain of transistor M.sub.3 may be coupled to V.sub.out.sup.+ through resistor R.sub.3. In some embodiments, the drain of transistor M.sub.2 may be coupled to the output terminal labeled V.sub.out.sup.− through resistor R.sub.2, and the drain of transistor M.sub.4 may be coupled to V.sub.out.sup.− through resistor R.sub.4. Output terminals V.sub.out.sup.+ and V.sub.out.sup.− may be coupled to respective conductors of a transmission line. Examples of a transmission line that may be driven by the line driver 200 include the wires of a twinax cable, or a pair of metal traces disposed on a printed circuit board, by way of example and not limitation. In some embodiments, the transmission line may exhibit a impedance equal to 50Ω, 75Ω, 80Ω or 100Ω. However, transmission lines exhibiting any other suitable resistance may be coupled to line driver 200.

(17) Each driver may receive an input signal, and in response, may place the corresponding transistor in a on or off state. An “on state” is referred to herein to either indicate an NMOS transistor having a gate/source voltage V.sub.GS greater than or equal to the threshold voltage, or a PMOS transistor having a source/gate voltage V.sub.SG greater than or equal to the absolute value of the threshold voltage. Contrarily, an “off state” is referred to herein to either indicate an NMOS transistor having a gate/source voltage V.sub.GS less than the threshold voltage or a PMOS transistor having a source/gate voltage V.sub.SG less than the absolute value of the threshold voltage.

(18) The gate of transistor M.sub.1 may be coupled to the output of driver D.sub.1, through capacitor C.sub.1, and to the output of driver D.sub.1′, and the gate of transistor M.sub.2 may be coupled to the output of driver D.sub.2, through capacitor C.sub.2, and to the output of driver D.sub.2′. The gate of transistor M.sub.3 may be coupled to the output of driver D.sub.3 and the gate of transistor M.sub.4 may be coupled to the output of driver D4. Drivers D.sub.1, D.sub.1′ and D.sub.3 may be configured to receive input signal V.sub.in.sup.−, and drivers D.sub.2, D.sub.2′ and D.sub.4 may be configured to receive input signal V.sub.in.sup.+. Input signals V.sub.in.sup.+ and V.sub.in.sup.− may toggle between V.sub.LL and V.sub.H. Input signals V.sub.in.sup.+ and V.sub.in.sup.− may represent a differential signal in some embodiments. Drivers D.sub.1 and D.sub.2 may be configured to receive voltage supplies V.sub.H and V.sub.LL, while drivers D.sub.1′ and D.sub.2′ may be configured to receive voltage supplies V.sub.HH and V.sub.L.

(19) In some embodiments, fast control path 211 may have a first speed, and fast control path 210 may have a second speed, less than the first speed. For example, fast control path 211 may be configured to track signals that vary at a frequency up to 60 GHz, and slow control path 210 may be configured to track signals that vary at a frequency up to 1 GHz.

(20) In some embodiments, the line driver 200 may be configured to receive a supply voltage greater that the maximum voltage for the particular fabrication node utilized. As an example, line driver 200 may be fabricated using a fabrication node such that only voltages no greater than 0.75V can be withstood. Nevertheless, the line driver 200 may receive a 1V supply voltage, and may drive transmission lines with a 1Vpp. As will be described further below, the use of a fast control path and a slow control path to drive the signals allows the line driver to withstand the voltage in excess.

(21) By way of example and not limitation, V.sub.in.sup.− may exhibit a succession of logic 0s, represented by the voltage V.sub.H, and 1s, represented by the voltage V.sub.LL, as illustrated in FIG. 3A. In response to receiving V.sub.in.sup.−, driver D.sub.1 may output signal V.sub.A, illustrated in FIG. 3B. Driver D.sub.1 may be configured to output a signal that tracks V.sub.in.sup.−. Accordingly, signal V.sub.A may exhibit a succession of logic 0s, represented by the voltage V.sub.H, and 1s, represented by the voltage V.sub.LL, that tracks the succession provided by V.sub.in.sup.−. Having a lower speed, driver D.sub.1′ may not be fast enough to track V.sub.in.sup.−, and may output a signal V.sub.B that varies at a slower rate with respect to V.sub.A, as shown in FIG. 3C, which illustrates a non-limiting example of signal V.sub.B.

(22) In some embodiments, to provide a slower speed, driver D.sub.1′ may comprise transistor(s) having a gate dielectric layer that is thicker than the gate dielectric layer used in driver D.sub.1. Having a thicker gate dielectric, the transistor(s) of driver D.sub.1′ may be configured to withstand voltages greater than V.sub.H−V.sub.LL. FIG. 4A-4B are schematic diagrams illustrating two MOSFET transistors having different gate dielectric thicknesses. Transistor 400 of FIG. 4A, may be used within driver D.sub.1 while transistor 450 of FIG. 4B may be used within driver D.sub.1′.

(23) Transistor 400 may comprise substrate 401, source doped well 404, drain doped well 406, gate dielectric 402, source terminal 414, gate terminal 412 and drain terminal 416. Substrate 401 may be a common substrate shared by a plurality of transistors of the type of transistor 400. Source terminal 414 may be disposed in correspondence with source doped well 404 and drain terminal 416 may be disposed in correspondence with drain doped well 406. Gate dielectric 402 may be disposed between gate terminal 412 and substrate 401. Gate dielectric 402 may comprise silicon oxide in some embodiments. Gate dielectric 402 may have a thickness T.sub.D, which may be between 1 nm and 50 nm in some embodiments.

(24) Transistor 450 may comprise substrate 451, source doped well 454, drain doped well 456, gate dielectric 452, source terminal 464, gate terminal 462 and drain terminal 466. Substrate 451 may be a common substrate shared by a plurality of transistors of the type of transistor 450. Source terminal 464 may be disposed in correspondence with source doped well 454 and drain terminal 466 may be disposed in correspondence with drain doped well 456. Gate dielectric 452 may be disposed between gate terminal 462 and substrate 451. Gate dielectric 452 may comprise silicon oxide in some embodiments. Gate dielectric 452 may have a thickness T.sub.D′, which may be between 1 nm and 50 nm in some embodiments.

(25) In some embodiments, transistor 400 may be used within driver D.sub.1 and transistor 450 may be used within driver D.sub.1′. In such embodiments, the thickness T.sub.D of dielectric 402 may be lower than the thickness T.sub.D′ of dielectric 452. For example, T.sub.D may be at least two times lower than T.sub.D′, at least three times lower than T.sub.D′, at least five times lower than T.sub.D′, at least ten times lower than T.sub.D′, or at least twenty times lower than T.sub.D′.

(26) Referring back to FIG. 2, the capacitor C.sub.1 may be used to retain the charge provided by driver D.sub.1′, while providing a path for signal V.sub.A. Capacitor C.sub.1 may also block the direct current (DC) component of signal V.sub.A. Accordingly, signal V.sub.C may have a DC component provided by driver D.sub.1′ and time-varying frequency components provided by driver D.sub.1.

(27) By combining a fast signal V.sub.A, toggling between V.sub.LL and V.sub.H, and a slowly varying signal V.sub.B, the resulting signal V.sub.C may track V.sub.A while toggling between V.sub.L and V.sub.HH. FIG. 3D illustrates a non-limiting example of V.sub.C in response to V.sub.in.sup.−. As illustrated, capacitor C.sub.1, used in combination with drivers D.sub.1 and D.sub.1′, may effectively operate as a level shifter receiving V.sub.LL and V.sub.H as inputs, and providing V.sub.L and V.sub.HH as outputs.

(28) When V.sub.C is equal to V.sub.L, the source/gate voltage of transistor M.sub.1 may be equal V.sub.HH−V.sub.C=V.sub.HH−V.sub.L. Since V.sub.HH−V.sub.L is within the rating range of the transistor, transistor M.sub.1 may operate without experiencing stress.

(29) By way of example and not limitation, V.sub.LL=0, V.sub.L=0.25V, V.sub.H=0.75V and V.sub.HH=1V, and V.sub.in.sup.+ and V.sub.in.sup.− may toggle between V.sub.LL, representing a logic 0, and 0.75V, representing a logic 1. According to such example, the transistors M.sub.1-M.sub.4 of line driver 200 may be configured to withstand voltages between the gate and the source, having an absolute value equal to or less than 0.75V. When V.sub.in.sup.− is equal to 0, V.sub.A may be equal to 0 and V.sub.C may be equal to 0.25V. Accordingly, the source/gate voltage of transistor M.sub.1 is equal to 1V−0.25V=0.75V. In this case the source/gate voltage of transistor M.sub.1 is within the rating range of the transistor, and transistor M.sub.1 may operate without experiencing stress. Fast control path and a slow control path act as a level shifter, shifting a 0 logic from 0 to 0.25V, thus maintain the source/gate voltage of transistor M.sub.1 below 0.75V.

(30) When V.sub.in.sup.− is equal to 0.75V, V.sub.A may be equal to 0.75 and V.sub.C may be equal to 1V. Accordingly, the source/gate voltage of transistor M.sub.1 is equal to 1V−1V=0. In this case the source/gate voltage of transistor M.sub.1 may cause transistor M1 to be in an off state without experiencing current leakage. Fast control path and a slow control path act as a level shifter, shifting a 1 logic from 0.75 to 1V, thus maintain the source/gate voltage of transistor M.sub.1 to 0.

(31) Drivers D.sub.2, and D.sub.2′ and capacitor C.sub.2 may receive signal V.sub.in.sup.+ and may be configured to operate in the same manner as described in connection with drivers D.sub.1, and D.sub.1′ and capacitor C.sub.1.

(32) Line driver 200 may exhibit one of two possible states. The first state occurs when V.sub.in.sup.− is equal to a logic 0 and V.sub.in.sup.+ is equal to a logic 1. In such a circumstance, the gate of transistor M.sub.1 my receive a voltage equal to V.sub.L, thus placing transistor M.sub.1 in an on state. The gate of transistor M.sub.2 my receive a voltage equal to V.sub.HH, thus placing transistor M.sub.2 in an off state. The gate of transistor M.sub.3 my receive a voltage equal to V.sub.LL, thus placing transistor M.sub.3 in an off state. The gate of transistor M.sub.4 my receive a voltage equal to V.sub.H, thus placing transistor M.sub.4 in an on state. Since M.sub.1 and M.sub.4 are in an on state, a current may flow through transistor M.sub.1, resistor R.sub.1, resistor R.sub.out, resistor R.sub.4 and transistor M.sub.4. In some embodiments, resistors R.sub.1 and R.sub.4 may exhibit equal resistances, and such resistance may be equal to half of the resistance associated with R.sub.out. In such embodiments, the output voltage V.sub.out.sup.+−V.sub.out.sup.− may be equal to (V.sub.HH−V.sub.LL)/2. Referring back to the non-limiting example provided above, V.sub.out.sup.+−V.sub.out.sup.−=0.75V−0.25V=0.5V.

(33) The second state occurs when V.sub.in.sup.− is equal to a logic 1 and V.sub.in.sup.+ is equal to a logic 0. In such a circumstance, the gate of transistor M.sub.1 my receive a voltage equal to V.sub.HH, thus placing transistor M.sub.1 in an off state. The gate of transistor M.sub.2 my receive a voltage equal to V.sub.L, thus placing transistor M.sub.2 in an on state. The gate of transistor M.sub.3 my receive a voltage equal to V.sub.H, thus placing transistor M.sub.3 in an on state. The gate of transistor M.sub.4 my receive a voltage equal to V.sub.LL, thus placing transistor M.sub.4 in an off state. Since M.sub.2 and M.sub.3 are in an on state, a current may flow through transistor M.sub.2, resistor R.sub.2, resistor R.sub.out, resistor R.sub.3 and transistor M.sub.3. In some embodiments, resistors R.sub.2 and R.sub.3 may exhibit equal resistances, and such resistance may be equal to half of the resistance associated with R.sub.out. In such embodiments, the output voltage V.sub.out.sup.+−V.sub.out.sup.− may be equal to −(V.sub.HH−V.sub.LL)/2. Referring back to the non-limiting example provided above, V.sub.out.sup.+−V.sub.out.sup.−=−(0.75V−0.25V)=−0.5V, thus providing a 1Vpp as desired.

(34) In some circumstances, it may be desirable to implement drivers D.sub.1′ and D.sub.2′ without resorting to transistors having different gate dielectric thicknesses. For example, some fabrication processes may provide process design kits (PDK) having only one type of transistor, such that all the transistors have the same gate dielectric thickness.

(35) In some embodiments, driver D.sub.1′ (and/or D.sub.2′) may be implemented using a latch circuit. FIG. 5 illustrates an exemplary latch circuit, according to some embodiments. Latch circuit 500 may comprise transistors M.sub.51, M.sub.52, M.sub.53, M.sub.54, M.sub.55 and M.sub.56. In some embodiments, the transistors may be PMOS transistors. However, other types of transistors may be used. The drain terminals of transistors M.sub.51 and M.sub.52 may be coupled to a voltage supply V.sub.LL, such as a ground terminal. The source terminals of transistors M.sub.51 and M.sub.52 may be coupled to the drain terminals of transistors M.sub.53 and M.sub.54 respectively. The source terminals of transistors M.sub.53 and M.sub.54 may be coupled to a supply voltage V.sub.HH. The gate terminals of transistor M.sub.53 and M.sub.54 may be coupled to the source terminals of transistors M.sub.52 and M.sub.51 respectively. In some embodiments, the drain terminal of transistor M.sub.53 may be coupled to the drain terminal of transistor M.sub.55, and the drain terminal of transistor M.sub.54 may be coupled to the drain terminal of transistor M.sub.56. The gate terminals of transistors M.sub.55 and M.sub.56 may be coupled together. The source terminals of transistors M.sub.55 and M.sub.56 may be coupled to a supply voltage V.sub.HH.

(36) The gate terminal of transistor M.sub.51 may be driven by signal V.sub.in.sup.− through driver D.sub.51. The gate terminal of transistor M.sub.52 may be driven by an inverted version of signal V.sub.in.sup.− through inverter driver D.sub.52. When V.sub.in.sup.− switches from a logic 0 to a logic 1, transistor M.sub.51 may switch to an off state, and transistor M.sub.52 may switch to an on state. As a current flows through transistors M.sub.52 and M.sub.54, the voltage at the drain terminal of transistor M.sub.52 may charge the capacitance associated with the gate terminal of transistor M.sub.53. Consequently the voltage V.sub.B may slowly increase. Contrarily, when V.sub.in.sup.− switches from a logic 1 to a logic 0, transistor M.sub.51 may switch to an on state, and transistor M.sub.52 may switch to an off state. As a current flows through transistor M.sub.51 and M.sub.53, the voltage at the drain terminal of transistor M.sub.51 may charge the capacitance associated with the gate terminal of transistor M.sub.54. At the same time, the capacitance associated with the gate terminal of transistor M.sub.53 may discharge. Consequently the voltage V.sub.B may slowly decay. In some embodiments, latch circuit 500 may be configured to provide a voltage V.sub.B equal to the moving average of signal V.sub.in.sup.−.

(37) In some embodiments, a line driver of the type described herein may be used in a digital-to-analog converter (DAC). The DAC may comprise a plurality of cells. For example, the DAC may comprise one cell for each bit of a digital word to be converted. FIG. 6 is a block diagram illustrating an exemplary DAC, according to some embodiments. DAC 600 may comprise a plurality of line drivers LD.sub.1, LD.sub.2 . . . LD.sub.N-1. One or more such line drivers may be implemented using line driver 200. Each line driver may be configured to receive a corresponding digital signal, which may be represented by a series of bits b.sub.1, b.sub.2 . . . b.sub.N-1. Each line driver may be configured to drive resistor R.sub.out, which may represent the resistance of a transmission line. In some embodiments, a resistive ladder may be used to perform the digital-to-analog conversion. For example, for each line driver, the resistors R.sub.1, R.sub.2, R.sub.3 and R.sub.4 may be configured to provide an output having a desired weight. Alternatively, or additionally, a transistor ladder may be used. For example, for each line driver, the size of transistors M.sub.1, M.sub.2, M.sub.3 and M.sub.4, such as the width and/or length of the drain and/or source, may be configured to provide a weighted output.

(38) The embodiments described herein may be used to drive transmission lines with peak-to-peak voltages greater than the maximum voltage that a transistor can withstand for a given fabrication node. Thanks to such line drivers, designers of electronic circuits may have the freedom to choose fabrication nodes that can provide a data rate sufficient for the specific application. For example, the embodiments described herein may be used to drive transmission lines at data rates exceeding 20 Gbit/s, 25 Gbit/s, 30 Gbit/s, 35 Gbit/s, 40 Gbit/s, 45 Gbit/s, 50 Gbit/s, 55 Gbit/s or 60 Gbit/s.

(39) Various aspects of the apparatus and techniques described herein may be used alone, in combination, or in a variety of arrangements not specifically discussed in the embodiments described in the foregoing description and is therefore not limited in its application to the details and arrangement of components set forth in the foregoing description or illustrated in the drawings. For example, aspects described in one embodiment may be combined in any manner with aspects described in other embodiments.

(40) Use of ordinal terms such as “first”, “second”, “third”, etc., in the claims to modify a claim element does not by itself connote any priority, precedence, or order of one claim element over another or the temporal order in which acts of a method are performed, but are used merely as labels to distinguish one claim element having a certain name from another element having a same name (but for use of the ordinal term) to distinguish the claim elements.

(41) Also, the phraseology and terminology used herein is for the purpose of description and should not be regarded as limiting. The use of “including”, “comprising”, “having”, “containing” or “involving” and variations thereof herein, is meant to encompass the items listed thereafter and equivalents thereof as well as additional items.

(42) The use of “coupled” or “connected” is meant to refer to circuit elements, or signals, that are either directly linked to one another or through intermediate components.