VARIABLE SPEED DRIVE FOR DRIVING AN ELECTRIC MOTOR AND METHOD FOR DIAGNOSING THE DRIVE

Abstract

The present invention relates to a variable speed drive for driving an electric motor and providing a safe torque off (STO) function. The drive includes two parallel signal buffers connected to a safety controller and at least one IGBT gate driver circuit, wherein the signal buffers share the same IGBT gate control signals as inputs and feed them to the same IGBT gate driver circuits and wherein each signal buffer has an own STO control signal for activation and deactivation of outputs. The invention is also directed at a method for diagnosing a corresponding drive.

Claims

1. A variable speed drive for driving an electric motor and providing a safe torque off (STO) function, the drive comprising two parallel signal buffers connected to a safety controller and at least one IGBT gate driver circuit, wherein the signal buffers share the same IGBT gate control signal as inputs and feed them to the same IGBT gate driver circuits and wherein each signal buffer has an own STO control signal for activation and deactivation of outputs.

2. The variable speed drive according to claim 1, wherein the safety controller comprises a complex programmable logic device (CPLD) and/or a field programmable gate array (FPGA) and/or a microcontroller unit (MCU).

3. The variable speed drive according to claim 1, wherein outputs for a certain gate of the two buffers are connected to the same point through series diodes.

4. The variable speed drive according to claim 1, wherein all gate control signals to be cut off by the STO function are connected through series diodes.

5. The variable speed drive according to claim 1, wherein each buffer has four input channels, one for each gate control signal and a fourth for being constantly supplied with a logical high input.

6. The variable speed drive according to claim 5, wherein the fourth input channel sets a feedback normally high during zero-vector conditions where all gate control signals can be low simultaneously.

7. The variable speed drive according to claim 1, wherein either of the two buffers can be used to deliver signals to the IGBT gate driver circuits.

8. The variable speed drive according to claim 1, wherein diagnostics of the drive is performed by activating one of the two individual low-active control signals.

9. A method for diagnosing a variable speed drive according to claim 1, comprising the steps of: diagnosing the first buffer first, reading back its feedback to the safety controller, controlling the first buffer to conductive state, diagnosing the second buffer, reading back its feedback to the safety controller, and controlling the second buffer to conductive state.

10. The method according to claim 9, wherein a diagnosing test pulse length is only limited by a diagnostics sequence period, wherein a test pulse length of 500 ms±200 ms, in particular ±100 ms, is used for diagnosing each buffer.

11. The variable speed drive according to claim 2, wherein outputs for a certain gate of the two buffers are connected to the same point through series diodes.

12. The variable speed drive according to claim 2, wherein all gate control signals to be cut off by the STO function are connected through series diodes.

13. The variable speed drive according to claim 3, wherein all gate control signals to be cut off by the STO function are connected through series diodes.

14. The variable speed drive according to claim 2, wherein each buffer has four input channels, one for each gate control signal and a fourth for being constantly supplied with a logical high input.

15. The variable speed drive according to claim 3, wherein each buffer has four input channels, one for each gate control signal and a fourth for being constantly supplied with a logical high input.

16. The variable speed drive according to claim 4, wherein each buffer has four input channels, one for each gate control signal and a fourth for being constantly supplied with a logical high input.

17. The variable speed drive according to claim 2, wherein either of the two buffers can be used to deliver signals to the IGBT gate driver circuits.

18. The variable speed drive according to claim 3, wherein either of the two buffers can be used to deliver signals to the IGBT gate driver circuits.

19. The variable speed drive according to claim 4, wherein either of the two buffers can be used to deliver signals to the IGBT gate driver circuits.

20. The variable speed drive according to claim 5, wherein either of the two buffers can be used to deliver signals to the IGBT gate driver circuits.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The method may comprise additional steps corresponding to the features presently described with respect to the variable speed drive. Further details and advantages of the invention are described with reference to the following figures:

[0036] FIG. 1: schematic view of components of the drive according to the invention;

[0037] FIG. 2: schematic view of a STO function in a drive according to the state of the art; and

[0038] FIG. 3: schematic view of a STO function in a drive according to the invention.

DETAILED DESCRIPTION

[0039] FIG. 1 shows a schematic view of components of the variable speed drive according to the invention. The drive serves for driving an electric motor not shown in FIG. 1 and provides a safe torque off (STO) function. The STO function ensures that no torque is generated by the motor in e.g. emergency situations. The STO function may comprise further components or feature that are not visible in FIG. 1.

[0040] The drive comprises two parallel signal buffers 10, 11 that are connected to a safety controller and at least one IGBT gate driver circuit. The signal buffers 10, 11 share the same IGBT gate control signals as inputs 8 and feed them to the same IGBT gate driver circuits. Each signal buffer 10, 11 is connected to receive an own STO control signal for activation and deactivation of outputs 1, 2.

[0041] The safety controller is not shown in FIG. 1 and may comprise a complex programmable logic device (CPLD) and/or a field programmable gate array (FPGA) and/or a microcontroller unit (MCU).

[0042] The outputs for a certain gate of the two buffers 10, 11 are connected to the same point 9 through series diodes 12. In the example of FIG. 1, three outputs of each buffer 10, 11 are connected to three common points 9 via six series diodes 12, that is, all gate control signals to be cut off by the STO function are connected through said series diodes 12.

[0043] Each buffer 10, 11 has four channels, one for each gate control signal 8 and a fourth 5 for being constantly supplied with a logical high input. The fourth input channel 5 sets a feedback 3, 4 normally high during zero-vector conditions where all gate control signals can be low simultaneously. Either of the two buffers 10, 11 can be used to deliver signals to the IGBT gate driver circuit independently from the other buffer 10, 11.

[0044] Diagnostics of the drive is performed by activating one of the two individual low-active STO control signals 1, 2. Diagnosing the variable speed drive, or more precisely diagnosing the STO function output or the parallel PWM signal buffer circuit of the variable speed drive, may comprise the steps of

[0045] diagnosing the first buffer 10 first,

[0046] reading back its feedback 3 to the safety controller,

[0047] controlling the first buffer 10 to conductive state,

[0048] diagnosing the second buffer 11,

[0049] reading back its feedback 4 to the safety controller, and

[0050] controlling the second buffer 11 to conductive state.

[0051] It may be irrelevant which of the two buffers 10, 11 is diagnosed first. When diagnosing the buffers 10, 11, a diagnosing test pulse length may only be limited by a diagnostics sequence period, wherein a test pulse length of 500 ms±200 ms, in particular ±100 ms, is used for diagnosing each buffer 10, 11.

[0052] The structure of the present invention's drive is basically built on two signal buffer circuits/switch banks 10, 11 with a high-active “enable” input, connected to a safety controller such as a CPLD (Complex Programmable Logic Device). The “switch banks 10, 11” may also be referred to as “buffers 10, 11”, although their operation is closely similar to AND-gates.

[0053] Both buffers 10, 11 are sharing the same IGBT gate control signal inputs 8, but each buffer 10, 11 has an own STO control signal for activation/deactivation of the outputs 1, 2. The outputs for a certain gate of the two buffers 10, 11, related to the same shared IGBT gate control signal (one signal of the three IGBT gate control signals 8), are connected to the same point (9, to IGBT gate driver circuit) through series diodes 12 so that the common output measured at the gate driver circuit input 9 is high if either or both of the buffers 10, 11 is providing high output (at points 6, 7) on the related gate. The same structure applies to all the gate control signals to be cut off by STO.

[0054] Each buffer 10, 11 has four inputs, one for each gate control signal 8 and the fourth channel 5 for being constantly supplied with a logical high input. The fourth channel 5 is required to set the feedback 3, 4 normally high also during zero-vector conditions where all gate control signals can be low simultaneously. Without the fourth, constantly high input, the feedback would fall to low state during zero-vector, which would cause a diagnostics problem. The fourth channel 5 does not affect the gate control signals.

[0055] Therefore, either of the two buffers 10, 11 can be used to deliver the signals onwards to the IGBT gate driver circuit, thus making it possible to test the switching capability of the other buffer 10, 11 in the meantime. Diagnostics is performed by activating one of the two individual low-active STO control signals 1, 2 that sets the corresponding buffer 10, 11 to a high-impedance state or writes logical low to its output 6, 7, depending on the buffer type used. If all the four switches of one buffer 10, 11 are operating correctly and the outputs are written low or high-impedance, the common feedback 3, 4 falls to zero. If one or more of the gate control signal outputs is stuck at high or doesn't follow the STO control signal, the feedback stays high or starts to repeat the PWM modulation present in the incoming IGBT gate control signal from the modulator, which triggers a safety hardware fault.

[0056] If all the outputs of one buffer 10, 11 are stuck at low, the safety controller indicates that the system is at a safe state. If one or more buffer outputs for the IGBT gate control signals are stuck at low, this may not be detected and does not need to be detected by the safety controller as it can be regarded as a safe type of failure. The diagnostics can also be operated in safe state by monitoring the feedback signals. In safe state, the STO control signals are low and the expected feedback states are also low. If either or both feedback signals are for some reason showing high state, a fault can be assumed in the STO circuit and the redundant second safety channel for STO can be activated to set the system to a safe state.

[0057] After the first buffer 10 has been diagnosed and its feedback has been successfully read back to the safety controller, the first buffer 10 can be controlled to conductive state by setting STO control signal 1, 2 to logical high, and the other, second buffer 11 can then be diagnosed in turn. The order of the diagnosis of the buffers 10, 11 and the reference to the buffers as first and second buffers 10, 11 may be chosen arbitrarily and do not limit the scope of the invention. As the diagnostics test pulse length is only limited by the diagnostics sequence period (commonly around 1 s) that should be a time window to test both of the buffers 10, 11, a test pulse length of close to 500 ms can be used for each buffer 10, 11. This ensures that the several modulation patterns will be fed through the tested buffer 10, 11 when motor shaft is rotating.

[0058] Using two parallel buffers 10, 11 adds some more complexity to the diagnostics routine, but does not represent a major obstacle. Using two parallel buffers 10, 11 theoretically doubles the “dangerous detected” failure rate of the switching element block by doubling each signal switch on the gate control signal lines, but still offers better key values as the dangerous hardware faults are detected quickly. Detection is basically done well before the safety function is called for the next time. In safety systems with at least SIL3 rating, there is always at least a second independent way to perform the function in case the primary method fails or is diagnosed as inoperative.

[0059] Diagnostics can be designed to cover the complete STO safety function chain, thus offering better safety key values and leaving no dangerous undetected faults to the signal chain. This eases the certification process of the drive.

[0060] Since no time-critical diagnostics needs to be performed, component tolerances have less effect on the design. Diagnostics can be ran with e.g. a is period with 400 ms test pulse length, which gives more freedom for test sequence definition and makes the system less vulnerable to interference. No long HW filters are required according to the invention. In contrast, in prior implementations there have been issues with component tolerances that have caused the test pulses to affect the non-safety system behavior by causing random faults to the non-safety controller and stopping the drive.

[0061] When a safety controller (e.g. CPLD/FPGA/MCU) is used as a master operating and diagnostics device in the safety system, this implementation adds only minor additional costs to the board component costs compared to the prior implementations. A parallel PWM buffer also offers the possibility to monitor the switch condition in safe state, which may be required in some applications. Some safety function implementations (other than this invention) tend to be diagnosable only when they are in a non-safe state. This may cause problems in some applications, as the system must first enter a non-safe state to observe that the safety system is not working properly. In extreme cases, such actions could cause losing the system's capability to ensure user safety.

[0062] FIG. 2 is a schematic view of a STO function in a drive according to the state of the art. Here, the actual signal cut-off element i.e. the element named “gate signal cutoff” is not covered by the diagnostics in the shown STO safety function chain. As a result, undetected dangerous failure modes may occur.

[0063] As can be seen, in devices known from the art, the diagnostics test pulse feedback is read before the last switching element of the safety chain. Between the feedback-reading point and final switching element, a filter that prevents the test pulses from affecting the switch is provided. The final switching element would then only be controlled if the STO request were truly active, i.e. the activation time is long enough. Even more problematically, no feedback is gained from the signal chain after the final element of the of the safety chain. It is therefore not known if the signal cutoff was successful or not. This leaves a blind spot on the diagnostics, as a short circuit over the final switching element would not be detected. In the worst case, both independent STO channels could eventually fail without noticing, which could lead to undesired motor movement even when a safety function is called by actuating an emergency switch.

[0064] This weakens the characteristic safety key values for the drive and for the customer's system. Undetected dangerous failure modes left in product also always tend to cause problems with certification authorities/notified bodies, thus increasing risks for product development phase schedules.

[0065] FIG. 3 is a schematic view of a STO function in a drive according to the present invention. In contrast to the situation shown in FIG. 2, here, the actual signal cut-off elements i.e. the elements named “gate signal cutoff buffer 1” and “gate signal cutoff buffer 2” are covered by the diagnostics in the shown STO safety function chain. As a result, undetected dangerous failure modes are less likely to occur then according to the prior art.

[0066] The invention is not limited to one of the above-described embodiments but can be modified in many ways.

[0067] All the features and advantages arising from the claims, the description and the drawings, including constructive details, spatial arrangements and procedural steps, can be essential to the invention both individually and in the most varied of combinations.