WAFER-LEVEL MANUFACTURING METHOD FOR EMBEDDING PASSIVE ELEMENT IN GLASS SUBSTRATE

Abstract

A wafer-level manufacturing method for embedding a passive element in a glass substrate is disclosed. A highly doped silicon wafer is dry etched to form a highly doped silicon mould wafer, containing highly doped silicon passive component structures mould seated in cavity arrays; a glass wafer is anodically bonded to the highly doped silicon mould wafer in vacuum pressure to seal the cavity arrays; the bonded wafers are heated so that the glass melts and fills gaps in the cavity arrays, annealing and cooling are performed, and a reflowed wafer is formed; the upper glass substrate of the reflowed wafer is grinded and polished to expose the highly doped silicon passives; the passive component structure mould embedded in the glass substrate is fully etched; the blind holes formed in the glass substrates after the passive component structure mould has been etched is filled with copper by electroplating; the highly doped silicon substrate and unetched silicon between the cavity arrays are etched, and several glass substrates embedded with a passive element are obtained; to form electrodes for the passives, a metal adhesion layer is deposited, and a metal conductive layer is electroplated. The process is simple, costs are low, and the prepared passive elements have superior performance.

Claims

1. A wafer-level manufacturing method fur embedding a passive element in a glass substrate, comprising the following steps: step 1: dry etching a highly doped silicon wafer to form a highly doped silicon mould wafer, containing highly doped silicon passive component structures mould seated in cavity arrays, unetched silicon between the cavity arrays being used for subsequent component separation; step 2: anodically bonding a glass wafer to the highly doped silicon mould wafer obtained in step 1 in a vacuum, so as to enable the cavity arrays to be sealed in bonded wafers; step 3: heating the bonded wafers obtained in step 2 in air at a temperature higher than the softening point temperature of the glass, maintaining the temperature until the molten glass is reflowed to fill gaps in the cavity arrays due to a pressure difference inside and outside the cavities, and annealing and cooling to room temperature to form a reflowed wafer with a three-layer structure including a lower all-highly doped silicon substrate, a middle composite structure of the glass substrate embedded with the passive component structure mould of highly doped silicon and the unetched silicon, and an upper all-glass substrate; step 4: fully grinding and polishing the all-glass substrate of the reflowed wafer obtained in step 3, so as to expose an upper surface of the embedded passive component structure mould on an upper surface of the glass substrate; step 5: dry etching the passive component structure mould embedded in the glass substrate; step 6: using the all-highly doped silicon substrate as a seed layer, filling, via copper electroplating, blind holes in the glass substrate after the passive component structure mould has been etched, thereby forming a passive element embedded in the glass substrate; step 7: wet etching the all-highly doped silicon substrate and the unetched silicon between the cavity arrays to obtain several cutting-free and self-separating glass substrates embedded with the passive element; and step 8: performing surface processing on the glass substrates obtained in step 7 to form electrodes for the passives, by depositing a metal adhesion layer and electroplating a metal conductive layer.

2. The wafer-level manufacturing method for embedding a passive element in a glass substrate according to claim 1, wherein shapes of the embedded passive component structure mould in step 1 comprise cylinder, annularcylinder, and coaxial cylinder, or meander-shaped column, square spiral column, hexagonal spiral column, octagonal spiral column, and circular spiral column, or double cuboid.

3. The wafer-level manufacturing method for embedding a passive element in a glass substrate according to claim 1, wherein an impurity doped in the highly doped silicon wafer in step 1 is phosphorus (P) or arsenic (As), the resistivity is 0.001 to 0.005 Ω.Math.cm, and the thickness is 300 to 600 um; and the dry etching is DRIE, and the etching depth is less than the thickness of the highly doped silicon wafer by 100 um or more.

4. The wafer-level manufacturing method for embedding a passive element in a glass substrate according to claim 2, wherein an impurity doped in the highly doped silicon wafer in step 1 is phosphorus (P) or arsenic (As), the resistivity is 0.001 to 0.005 Ω.Math.cm, and the thickness is 300 to 600 um; and the dry etching is DRIE, and the etching depth is less than the thickness of the highly doped silicon wafer by 100 um or more.

5. The wafer-level manufacturing method for embedding a passive element in a glass substrate according to claim 1, wherein the glass wafer in step 2 is borosilicate glass with the thickness of 300 to 500 um, and the conditions of the anodic bonding process performed in the vacuum are that the temperature is 400° C., the voltage is 800 V, and the vacuum degree is less than 10.sup.−3 Pa.

6. The wafer-level manufacturing method for embedding a passive element in a glass substrate according to claim 2, wherein the glass wafer in step 2 is borosilicate glass with the thickness of 300 to 500 um, and the conditions of the anodic bonding process performed in the vacuum are that the temperature is 400° C., the voltage is 800 V, and the vacuum degree is less than 10.sup.−3 Pa.

7. The wafer-level manufacturing method for embedding a passive element in a glass substrate according to claim 1, wherein the conditions of the heating process in step 3 are that the heating temperature is 900° C. to 1100° C., and the heating holding time is 6 to 10 h; the conditions of the annealing process are that the annealing temperature is 510° C. to 560° C., and the annealing holding time is 30 min; and the cooling to room temperature is natural cooling.

8. The wafer-level manufacturing method for embedding a passive element in a glass substrate according to claim 2, wherein the conditions of the heating process in step 3 are that the heating temperature is 900° C. to 1100° C., and the heating holding time is 6 to 10 h; the conditions of the annealing process are that the annealing temperature is 510° C. to 560° C., and the annealing holding time is 30 min; and the cooling to room temperature is natural cooling.

9. The wafer-level manufacturing method for embedding a passive element in a glass substrate according to claim 1, wherein the grinding and polishing in step 4 is that: first, by an automatic grinding and polishing machine, the all-glass substrate is subjected to a grinding and thinning process until the all-glass substrate is substantially removed, and second, the surface of the glass is polished by using a cerium oxide polishing solution until the glass substrate is exposed, and at this time, the upper surface of the embedded passive component structure mould is exposed on the smooth upper surface of the glass substrate.

10. The wafer-level manufacturing method for embedding a passive element in a glass substrate according to claim 2, wherein the grinding and polishing in step 4 is that: first, by an automatic grinding and polishing machine, the all-glass substrate is subjected to a grinding and thinning process until the all-glass substrate is substantially removed, and second, the surface of the glass is polished by using a cerium oxide polishing solution until the glass substrate is exposed, and at this time, the upper surface of the embedded passive component structure mould is exposed on the smooth upper surface of the glass substrate.

11. The wafer-level manufacturing method for embedding a passive element in a glass substrate according to claim 1, wherein the dry etching in step 5 is DRIE; the determination to stop the etching is that the passive component structure mould is exactly completely etched, or the passive component structure mould is completely etched and the lower all-highly doped silicon substrate is etched for not greater than 20 um.

12. The wafer-level manufacturing method for embedding a passive element in a glass substrate according to claim 2, wherein the dry etching in step 5 is DRIE; the determination to stop the etching is that the passive component structure mould is exactly completely etched, or the passive component structure mould is completely etched and the lower all-highly doped silicon substrate is etched for not greater than 20 um.

13. The wafer-level manufacturing method for embedding a passive element in a glass substrate according to claim 1, wherein the conditions of the copper electroplating process in step 6 are that: in an acidic sulfate plating solution for the copper electroplating, the content of CuSO.sub.4.5H.sub.2O is 85 g/L, the content of H.sub.2SO.sub.4 is 200 g/L, the content of Cl.sup.− is 79 mg/L, and the current density is 30 mA/cm.sup.2.

14. The wafer-level manufacturing method for embedding a passive element in a glass substrate according to claim 2, wherein the conditions of the copper electroplating process in step 6 are that: in an acidic sulfate plating solution for the copper electroplating, the content of CuSO.sub.4.5H.sub.2O is 85 g/L, the content of H.sub.2SO.sub.4 is 200 g/L, the content of Cl.sup.− is 79 mg/L, and the current density is 30 mA/cm.sup.2.

15. The wafer-level manufacturing method for embedding a passive element in a glass substrate according to claim 1, wherein the conditions of the wet etching process in step 7 are that an etching solution is a 40 wt % potassium hydroxide solution, and the etching temperature is 70° C.

16. The wafer-level manufacturing method for embedding a passive element in a glass substrate according to claim 2, wherein the conditions of the wet etching process in step 7 are that an etching solution is a 40 wt % potassium hydroxide solution, and the etching temperature is 70° C.

17. The wafer-level manufacturing method for embedding a passive element in a glass substrate according to claim 1, wherein in step 8, the deposited metal adhesion layer is Ti or Cr, and the electroplated metal conductive layer is Au or Cu.

18. The wafer-level manufacturing method for embedding a passive element in a glass substrate according to claim 2, wherein in step 8, the deposited metal adhesion layer is Ti or Cr, and the electroplated metal conductive layer is Au or Cu.

19. The wafer-level manufacturing method for embedding a passive element in a glass substrate according to claim 2, wherein the coaxial cylinder is a coaxial dual-annular cylinder.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0041] FIG. 1 is a sectional view of a highly doped silicon mould wafer containing cavity arrays embedded in a passive component structure mould.

[0042] FIG. 2 is a sectional view of a bonded wafer obtained after a glass wafer is anodically bonded to the highly doped silicon mould wafer.

[0043] FIG. 3 is a sectional view of a reflowed wafer obtained after heating, refloweding, and annealing are carried out.

[0044] FIG. 4 is a sectional view of the reflowed wafer after being ground and polished.

[0045] FIG. 5 is a sectional view of the reflowed wafer after the passive component structure mould is dry etched.

[0046] FIG. 6 is a sectional view of the reflowed wafer embedded with a copper-made passive element.

[0047] FIG. 7 is a sectional view of self-separated glass substrates embedded with a passive element after silicon is wet etched.

[0048] FIG. 8 is a sectional view of the glass substrates undergoing a surface processing procedure.

[0049] FIG. 9 is a perspective view of a glass substrate embedded with conductive vias, a meander-shaped inductor, and a coplanar waveguide.

[0050] FIG. 10 is a perspective view of a glass substrate embedded with spiral inductors.

[0051] FIG. 11 is a perspective view of a glass substrate embedded with a capacitor.

DETAILED DESCRIPTION OF THE INVENTION

[0052] The present invention is further explained below with reference to embodiments and accompanying drawings. The following embodiments are merely intended to describe the present invention, but are not intended to limit the implementation scope of the present invention.

Embodiment 1

[0053] A wafer-level manufacturing method for embedding a passive element in a glass substrate, including the following steps:

[0054] step 1: dry etching a highly doped silicon wafer to form a highly doped silicon mould wafer 1, containing highly doped silicon passive component structures mould 2 seated in cavity arrays 3, as shown in FIG. 1, unetched silicon 4 between the cavity arrays 3 being used for subsequent component separation. An impurity doped in the highly doped silicon wafer is phosphorus (P), the resistivity is 0.001 Ω.Math.cm, and the thickness is 500 um. The dry etching is DRIE, and the etching depth is 200 um. Shapes of the embedded passive component structure mould 2 include cylinder, annular cylinder, coaxial cylinder, a cylinder array of 3 rows×2 columns for coplanar waveguide interconnection, and a 6-cylinder array for manufacturing an embedded meander-shaped inductor.

[0055] step 2: anodically bonding a glass wafer 5 to the highly doped silicon mould wafer 1 obtained in step 1 under conditions that the vacuum pressure is less than 10.sup.−3 Pa, the temperature is 400° C., and the voltage is 800 V, so as to enable the cavity arrays 3 to be sealed in bonded wafers, as shown in FIG. 2. The glass wafer 5 is a glass with model Pyrex7740, and with a thickness of 300 um.

[0056] step 3: heating the bonded wafers obtained in step 2 in air at a temperature of 900° C., maintaining the temperature for 6 h until the molten glass is reflowed to fill gaps in the cavity arrays 3 due to a pressure difference inside and outside the cavities, and annealing for 30 min at 560° C., and naturally cooling to room temperature to form a reflowed wafer with a three-layer structure including a lower all-highly doped silicon substrate 6, a middle composite structure 7 of the glass substrate embedded with the passive component structure mould 2 and the unetched silicon 4, and an upper all-glass substrate 8, as shown in FIG. 3.

[0057] step 4: first, using an automatic grinding and polishing machine, carrying out a grinding and thinning process on the all-glass substrate 8 until the all-glass substrate 8 is substantially removed, and second, using a cerium oxide polishing solution, polishing the surface of the glass until an upper surface of the embedded passive component structure mould 2 is exposed on an smooth upper surface of the glass substrate, as shown in FIG. 4.

[0058] step 5: carrying out DRIE on the passive component structure mould 2 embedded in the glass substrate, as shown in FIG. 5. The etching depth is 200 um.

[0059] step 6: using the all-highly doped silicon substrate 6 as a seed layer, filling, via copper electroplating, blind holes in the glass substrate after the passive component structure mould 2 has been etched, thereby forming a passive element 10 embedded in the glass substrate, as shown in FIG. 6. The conditions of the copper electroplating process are that: in an acidic sulfate plating solution for the copper electroplating, the content of CuSO.sub.4.5H.sub.2O is 85 g/L, the content of H.sub.2SO.sub.4 is 200 g/L, the content of is 79 mg/L, and the current density is 30 mA/cm.sup.2. To enhance the reliability of the glass embedded copper vias, it is also possible to deposit adhesion layer, barrier layer, wetting layer and some other functional layers as the traditional electroplating process.

[0060] step 7: wet etching the all-highly doped silicon substrate 6 and the unetched silicon 4 between the cavity arrays 3 to obtain several cutting-free and self-separating glass substrates 11 embedded with the passive element 10, as shown in FIG. 7. The conditions of the wet etching process are that an etching solution is a 40 wt % potassium hydroxide solution, and the etching temperature is 70° C.

[0061] step 8: performing surface processing on the glass substrates 11 obtained in step 7 to form electrodes for passive structures, by depositing a metal adhesion layer 12 Ti or Cr and electroplating a metal conductive layer 13 Au or Cu, as shown in FIG. 8, for use as a passive element single element or a 3D integrated glass adapter plate. The cylinder shape, annular cylinder shape, and coaxial-cylinder shape of the embedded passive component structure mould 2 are used to prepare a cylinder shaped conductive via 14, an annular cylinder shaped conductive via 15, and a coaxial-cylinder shaped conductive via 16 that are embedded in the glass substrate and applied to 3D component interconnection, for example, interconnection of a coplanar waveguide 17, or used to prepare a meander-shaped inductor 18 half-embedded in the glass substrate, as shown in FIG. 9. With regard to the copper cylinder array of 3 rows×2 columns, waveguide lines are prepared to connect lower surfaces of the cylinders, and two waveguide lines are prepared to respectively connect upper surfaces of each column of cylinders, so as to form a copper-cylinder-interconnected coplanar waveguide 17 structure. The preparation for the waveguide lines includes: depositing a metal adhesion layer 12 Ti or Cr, and electroplating a metal conductive layer 13 Au. With regard to the 6-cylinder array, wires are prepared to cover an upper surface of the first cylinder, five wires are prepared to respectively connect lower surfaces of the first cylinder and the second cylinder, upper surfaces of the second cylinder and the third cylinder, lower surfaces of the third cylinder and the fourth cylinder, upper surfaces of the thurth cylinder and the fifth cylinder, and lower surfaces of the fifth cylinder and the sixth cylinder; and a wire is prepared to cover an upper surface of the sixth cylinder, so as to form the meander-shaped inductor 18; the preparation for the wires includes: depositing a metal adhesion layer 12 Ti or Cr, and electroplating a metal conductive layer 13 Cu. Different types of coplanar waveguides and meander-shaped inductors can be formed through adding copper cylinders and preparing different shapes of wires.

Embodiment 2

[0062] Step 1: dry etching a highly doped silicon wafer to form a highly doped silicon mould wafer 1, containing highly doped silicon passive component structures mould 2 seated in cavity arrays 3, as shown in FIG. 1, unetched silicon 4 between the cavity arrays 3 being used for subsequent component separation. An impurity doped in the highly doped silicon wafer is arsenic (As), the resistivity is 0.003 Ω.Math.cm, and the thickness is 600 um. The dry etching is DRIE, and the etching depth is 300 um. Shapes of the embedded passive component structure mould 2 include meander-shaped column, square spiral column, hexagonal spiral column, octagonal spiral column, and circular spiral column, or double cuboid, and coaxial dual-annular cylinder.

[0063] Step 2: anodically bonding a glass wafer 5 to the highly doped silicon mould wafer 1 obtained in step 1 under conditions that the vacuum degree is less than 10.sup.−3 Pa, the temperature is 400° C., and the voltage is 800 V, so as to enable the cavity arrays 3 to be sealed in bonded wafers, as shown in FIG. 2. The glass wafer 5 is a glass with model Pyrex7740, and with a thickness of 500 um.

[0064] Step 3: heating the bonded wafers obtained in step 2 in air at a temperature of 1000° C., maintaining the temperature for 6 h until the molten glass is reflowed to till gaps in the cavity arrays 3 due to a pressure difference inside and outside the cavities, and annealing for 30 min at 560° C., and naturally cooling to room temperature to form a reflowed wafer with a three-layer structure including a lower all-highly doped silicon substrate 6, a middle composite structure 7 of the glass substrate embedded with the passive component structure mould 2 and the unetched silicon 4, and an upper all-glass substrate 8, as shown in FIG. 3.

[0065] Step 4: first, using an automatic grinding and polishing machine, carrying out a grinding and thinning process on the all-glass substrate 8 until the all-glass substrate 8 is substantially removed, and second, using a cerium oxide polishing solution, polishing the surface of the glass until an upper surface of the embedded passive component structure mould 2 is exposed on an smooth upper surface of the glass substrate, as shown in FIG. 4.

[0066] Step 5: carrying out DRIE on the passive component structure mould of highly doped silicon 2 embedded in the glass substrate, as shown in FIG. 5. The etching depth is 300 um.

[0067] Step 6: using the all-highly doped silicon substrate 6 as a seed layer, filling, via copper electroplating, blind holes in the glass substrate after the passive component structure mould 2 has been etched, thereby forming a passive element 10 embedded in the glass substrate, as shown in FIG. 6. The conditions of the copper electroplating process are that: in an acidic sulfate plating solution for the copper electroplating, the content of CuSO.sub.4.5H.sub.2O is 85 g/L, the content of H.sub.2SO.sub.4 is 200 g/L, the content of is 79 mg/L, and the current density is 30 mA/cm.sup.2.

[0068] Step 7: wet etching the all-highly doped silicon substrate 6 and the unetched silicon 4 between the cavity arrays 3 to obtain several cutting-free and self-separating glass substrates 11 embedded with the passive element 10, as shown in FIG. 7. The conditions of the wet etching process are that an etching solution is a 40 wt % potassium hydroxide solution, and the etching temperature is 70° C.

[0069] Step 8: performing surface processing on each of the glass substrates 11 obtained in step 7 to form electrodes for the passives, by depositing a metal adhesion layer 12 Ti or Cr and electroplating a metal conductive layer 13 Au, as shown in FIG. 8, for use as a passive element single element or a 3D integrated glass adapter plate, as shown in FIG. 11. The meander-shaped column, square spiral column, hexagonal spiral column, octagonal spiral column, and circular spiral column are used to prepare a meander-shaped spiral inductor 19, a square spiral inductor 20, a hexagonal spiral inductor 21, an octagonal spiral inductor 22, and a circular spiral inductor 23 that are fully embedded in the glass substrate, as shown in FIG. 10. The double cuboid is used to prepare a plate-shaped capacitor 24 that is fully embedded in the glass substrate, and the coaxial dual-annular cylinder is used to prepare an annular capacitor 25 that is fully embedded in the glass substrate. The inductors and the capacitors can be interconnected through metals on the surfaces, so as to form elements such as a filter and an amplifier.