High-Power Single-Stage LED Driver with Bipolar Ripple Cancellation

Abstract

Provided are circuits and methods for a power converter that converts AC input power into DC output power using a first output circuit that provides a first output comprising a DC voltage with a first AC voltage ripple and a second output circuit including a floating capacitor and one or more power switching device, and provides a second output comprising a second AC voltage ripple, wherein the first output and the second output are connected together in series, such that the first AC voltage ripple is substantially cancelled and substantially ripple-free DC output power is provided. Embodiments significantly reduce the total output capacitance requirement without sacrificing power factor, thus avoiding the need for electrolytic capacitors and enabling the use of long-life film capacitors. The circuits and methods are particularly suitable for use in applications where ripple-free high power and high reliability are required, such as in high power LED lighting.

Claims

1. A power converter that converts AC input power into DC output power, comprising: an input circuit that receives AC input power, the input circuit having one or more power switching device; a first output circuit that receives power from the input circuit and provides a first output comprising a DC voltage with a first AC voltage ripple; a second output circuit that receives power from a circuit comprising a floating capacitor and provides a second output comprising a second AC voltage ripple, the second output circuit having one or more power switching device; wherein the first output and the second output are connected together in series, such that the first AC voltage ripple is substantially cancelled; wherein substantially ripple-free DC output power is provided.

2. The power converter of claim 1, comprising a controller that controls the power switching devices of the input circuit and the second output circuit, and controls a voltage of the floating capacitor so that the first output circuit and the second output circuit alternatively rectify output current only once during one switching cycle of the power switching devices.

3. The power converter of claim 2, wherein the controller includes a slow PI control loop that controls the voltage of the floating capacitor.

4. The power converter of claim 1, wherein the AC voltage ripple has a frequency that is double a line frequency of the AC input power.

5. The power converter of claim 2, wherein the controller includes a power loss offset loop that allows the second output circuit to absorb more input energy than output energy in each double line frequency cycle; wherein energy loss resulting from the second output circuit is offset.

6. The power converter of claim 2, wherein the controller regulates the voltage of the floating capacitor at a reference value.

7. The power converter of claim 1, comprising a PFC converter selected from a flyback converter, a buck converter, a boost converter, an isolated boost converter, a LLC resonant converter, and a LCLC resonant converter.

8. The power converter of claim 1, further comprising a secondary power supply that provides input power to the second output circuit.

9. The power converter of claim 2, wherein the controller controls the one or more power switching device of the input circuit so that the input circuit achieves a high power factor.

10. A method for converting AC input power into DC output power, comprising: receiving AC input power using an input circuit having one or more power switching device; using a first output circuit to receive power from the input circuit and provide a first output comprising a DC voltage with a first AC voltage ripple; using a second output circuit including a floating capacitor and one or more power switching device to provide a second output comprising a second AC voltage ripple; connecting the first output and the second output together in series, such that the first AC voltage ripple is substantially cancelled; wherein the AC input power is converted into substantially ripple-free DC output power.

11. The method of claim 10, comprising controlling the power switching devices of the input circuit and the second output circuit, and controlling a voltage of the floating capacitor so that the first output circuit and the second output circuit alternatively rectify output current only once during one switching cycle of the power switching devices.

12. The method of claim 11, wherein controlling includes using a slow PI control loop to control the voltage of the floating capacitor.

13. The method of claim 10, wherein the AC voltage ripple has a frequency that is double a line frequency of the AC input power.

14. The method of claim 11, wherein controlling includes allowing the second output circuit to absorb more input energy than output energy in each double line frequency cycle; wherein energy loss resulting from the second output circuit is offset.

15. The method of claim 14, wherein controlling includes using a power loss offset loop to allow the second output circuit to absorb more input energy than output energy in each double line frequency cycle.

16. The method of claim 11, wherein controlling regulates the voltage of the floating capacitor at a reference value.

17. The method of claim 10, comprising using a PFC converter selected from a flyback converter, a buck converter, a boost converter, an isolated boost converter, a LLC resonant converter, and a LCLC resonant converter.

18. The method of claim 10, further comprising providing input power to the second output circuit using a secondary power supply.

19. The method of claim 11, including controlling the one or more power switching device of the input circuit so that the input circuit achieves a high power factor.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0020] For a better understanding of the invention, and to show more clearly how it may be carried into effect, embodiments will be described, by way of example, with reference to the accompanying drawings, wherein:

[0021] FIGS. 1A and 1B are block diagrams of conventional two stage and single stage high-power LED driver configurations, respectively.

[0022] FIG. 1C is a block diagram of a parallel ripple cancellation configuration according to the prior art.

[0023] FIG. 2A is a block diagram of an LED driver with a floating capacitor bipolar ripple cancellation stage, according to one embodiment.

[0024] FIG. 2B is a diagram showing voltage waveforms of the generalized embodiment of FIG. 2A.

[0025] FIG. 3A is a circuit diagram of an LED driver with floating capacitor, according to one embodiment.

[0026] FIG. 3B is a circuit diagram of an LED driver with floating capacitor, according to another embodiment.

[0027] FIG. 4A is a block diagram of a control strategy for the embodiment of FIG. 3A.

[0028] FIG. 4B is a block diagram of a control strategy according to another embodiment.

[0029] FIGS. 5A-5C are plots showing an under-cancellation phenomenon analysis, wherein FIG. 5A shows an ideal case; FIG. 5B shows a case without a loss offset loop in the control strategy; and FIG. 5C shows a case with a loss offset loop in the control strategy (e.g., as shown in FIG. 4A).

[0030] FIG. 6 is a plot showing PFC output capacitance vs. PFC output peak-to-peak ripple voltage with a LED current of 0.7 A.

[0031] FIG. 7 shows two operating modes of a bipolar ripple cancellation converter according to one embodiment.

[0032] FIG. 8 shows traces of key waveforms measured for a floating capacitor FBRCC experimental prototype, wherein V.sub.in=110 Vac. V.sub.LED≈150 V, I.sub.LED=0.7 A, and P.sub.O=100 W.

[0033] FIG. 9 shows traces of measured input current, input voltage, and output voltage of an experimental prototype wherein V.sub.in=110 Vac, V.sub.LED≈150 V, I.sub.LED=0.7 A, and P.sub.O=100 W.

[0034] FIGS. 10A and 10B show the measured performance of an experimental prototype and a conventional single stage LED driver configuration, respectively.

[0035] FIGS. 11A and 11B are plots showing the efficiency and power factor, respectively, as a function of input voltage, for an experimental prototype.

[0036] FIG. 12 is a plot showing the FBRCC stage loss and efficiency as a function of input voltage, for an experimental prototype.

[0037] FIGS. 13A and 13B are plots showing the efficiency and power factor, respectively, during dimming at two input voltages, for an experimental prototype.

[0038] FIG. 14 is a block diagram of an LED driver with a bipolar ripple cancellation stage, according to one embodiment.

[0039] FIG. 15 is a circuit diagram showing an implementation of the embodiment of FIG. 14.

DETAILED DESCRIPTION OF EMBODIMENTS

[0040] Described herein are ripple cancellation circuits and methods that produce a DC output that is substantially low frequency ripple-free, and minimize the output capacitance requirement, enabling the use of long-life film capacitors. The term “low frequency ripple” is intended to refer to the second harmonic of the AC input power (e.g., 120 Hz in North America or 100 Hz in China, Europe). Compared to existing technologies, the embodiments described herein minimize or substantially eliminate the low frequency current ripple through the LED lamps and achieve a high power factor and high efficiency. Embodiments are particularly well-suited to high power applications, such as high power LED lighting, because of their high power factor, high efficiency, and reduction or elimination of visible flickering of the light emitting from the LED lamps. Accordingly, embodiments are described herein with respect to such applications. However, it will be appreciated that the embodiments may be applied to other applications; e.g., applications where the load is not an LED lamp. Thus, throughout the description and drawings, the load may include one or more LEDs, or the load may not include any LEDs. In lighting applications, embodiments may be implemented in a LED lamp, or in a separate power supply used to drive one or more LED lamps.

[0041] Embodiments relate to a high power single-stage LED driver configuration with a bipolar (i.e., AC) ripple cancellation stage. The bipolar ripple cancellation circuits include a full bridge converter used to generate an AC voltage with zero DC bias which substantially cancels the low frequency voltage ripple of the PFC output. The full bridge ripple cancellation converter (FBRCC) stage allows the PFC output capacitance to be significantly reduced, so that long-life film capacitors may be used. The power converter PFC stage may be implemented with a flyback converter, or any other single-stage PFC stage, such as, but not limited to, buck converter, boost converter, isolated boost converter, LLC resonant converter, and LCLC resonant converter. The series bipolar ripple cancellation embodiments significantly reduce the total output capacitance of an LED driver without sacrificing the power factor, thus avoiding the need for electrolytic capacitors and enabling the use of long-life film capacitors.

[0042] The term “substantially” refers to the fact that the converter produces DC power with only very small low frequency ripple or no low frequency ripple, such that the DC power is suitable for use in sensitive applications such as LED lighting. However, as noted above, embodiments may be used in applications other than driving LEDs.

[0043] In the embodiments described herein, a floating capacitor is used as the input of the full bridge converter because the net power provided by the full bridge converter is zero under ideal conditions, and is very small if the power loss in the FBRCC is considered. The voltage of the floating capacitor may be regulated by a voltage control loop.

Operating Principle

[0044] FIG. 2A shows a block diagram of a LED driver configuration with a floating capacitor Full bridge ripple cancellation converter. It is noted that this bipolar ripple cancellation configuration is suitable for both isolated and non-isolated single-stage PFC topologies.

[0045] The main output voltage and the FBRCC output voltage are connected in series and the combined voltage is used to power the LED lamps. FIG. 2B shows the voltage waveforms of the main output (v.sub.main), ripple cancellation stage output (v.sub.FB) and the LED voltage (V.sub.LED).

[0046] The PFC output voltage V.sub.main includes both the AC and DC voltage components. The AC voltage ripple is at twice the line frequency, shown as the upper curve in FIG. 2B. The expression of the PFC output voltage is given in Equation (1)

v.sub.main=V.sub.DC+v.sub.ripple  (1)

[0047] where V.sub.DC is the DC component of the PFC output voltage, and v.sub.ripple is the AC component of PFC output voltage. The output voltage of the cancellation stage v.sub.FB is a substantially pure AC voltage, shown as the middle curve in FIG. 2B with zero DC voltage. In order to achieve a ripple-free output voltage across the LED lamps, the cancellation voltage v.sub.FB, must offset the voltage ripple, v.sub.ripple, as given in Equation (2).

v.sub.FB(t)=−v.sub.ripple(t)  (2)

[0048] The voltage across the LED lamp is the sum of the PFC output voltage and the cancellation stage output voltage, expressed in Equation (3).

V.sub.LED=v.sub.main+v.sub.FB  (3)

[0049] Substitution of Equations (1) and (2) into (3) yields (4).

V.sub.LED=V.sub.DC  (4)

[0050] The LED lamp sees only the DC component as shown in the lower line in FIG. 2B. It is noted that the peak-to-peak value of the double line frequency voltage ripple in the PFC output V.sub.ripple is proportional to the LED output current I.sub.LED as well as the PFC output capacitance C.sub.main, as shown in Equation (5).

[00001]$\begin{array}{cc}{V}_{\mathrm{ripple}}=\frac{P_{\mathrm{in}}}{\omega \times C_{\mathrm{main}}\times V_{\mathrm{LED}}}=\frac{I_{\mathrm{LED}}}{2.Math.\pi \times f\times C_{\mathrm{main}}}& \left(5\right)\end{array}$

[0051] A smaller value of C.sub.main may be used in order to remove the electrolytic capacitor from the configuration, as discussed below.

[0052] For applications where high-power LED lamps require electrical isolation, an isolated flyback topology may be used as the PFC stage. However, other topologies may be used for the power structure. An example of an architecture is shown in the embodiment of FIG. 3A. In this embodiment, a single-stage flyback circuit is used as the isolated PFC stage and the auxiliary bipolar ripple cancellation stage is a full-bridge ripple cancellation converter (FBRCC). The FBRCC includes four switches (Q.sub.1˜Q.sub.4), one inductor (L.sub.FB) and two capacitors (floating input capacitor C.sub.aux and output capacitor C.sub.FB). The flyback PFC provides all of the LED driving power, and the FBRCC only cancels the AC voltage ripple. It is noted that voltage across C.sub.aux (v.sub.Caux) contains the low frequency (120 Hz) ripple while C.sub.FB only filters out the high switching frequency noise as a part of the output filter. Therefore, C.sub.FB may have a small value (e.g., <5 μF). Design details for C.sub.aux are given below.

[0053] It is noted that when driving a DC (voltage/current) load (e.g., an LED load), the current is always passing through the body diodes of switches Q.sub.2 and Q.sub.3. Therefore, the circuit may be simplified by replacing Q.sub.2 and Q.sub.3 with two diodes D.sub.2 and D.sub.3, as shown in FIG. 3B. This reduces the bipolar ripple cancellation circuit cost by saving two switches and their driving circuits.

[0054] Examples of control strategies are shown in the block diagrams of FIGS. 4A and 4B. Referring to FIG. 4A, AC ripple cancellation control blocks, shown in dashed boxes, have a high bandwidth to provide a quick AC reference tracking ability. A significant difference between this control strategy and prior strategies is the method used to offset power loss in the FBRCC. In order to ensure a good ripple cancellation ability of the floating capacitor FBRCC, a power loss offset loop (shown in the box with solid lines in FIG. 4A) is provided, where the FBRCC floating capacitor voltage (v.sub.Caux) is regulated through a slow PI control loop. A slow PI control loop may have a bandwidth of, e.g., 1 kHz, or less. This control loops avoids an “under-cancellation” phenomenon described as follows.

[0055] When the voltage of the main output is higher than the LED DC output voltage, the FBRCC provides a negative voltage to cancel the ripple and the energy flows into the FBRCC. When the voltage of the main output is lower than the LED DC output voltage, the FBRCC provides a positive voltage to cancel the ripple and the energy flows out of the FBRCC. If the FBRCC is lossless, the sum of the input energy and the output energy in a half cycle of the line frequency will be equal, and thus the C.sub.aux voltage will be self-balancing and v.sub.FB presents a symmetrical AC curve, as shown in FIG. 5A. In this case, the FBRCC provides a pure AC voltage with zero DC bias.

[0056] However, the FBRCC has power loss in a practical implementation. If the C.sub.aux voltage is not regulated and there is no loss offset mechanism, the input energy to the FBRCC stage will be less than the output energy in a half-line cycle, then C.sub.aux will be discharged and the C.sub.aux voltage will drop. When the C.sub.aux voltage is sufficiently low, the FBRCC can no longer produce the peak voltage required to cancel the main stage's ripple at valley points, and under-cancellation may occur. This phenomenon is shown in FIG. 5B, where periodic bumps occur on the DC LED voltage at twice the line frequency.

[0057] To solve this problem, the average C.sub.aux voltage may be regulated as shown in the embodiment of FIG. 4A, using the power loss offset control loop. This loop allows the FBRCC to absorb slightly more input energy than the output energy in each double line frequency cycle, in order to offset the energy loss. As a result, the C.sub.aux voltage may be kept stable and its average value can be regulated at the reference value (V.sub.Caux.sub._.sub.ref).

[0058] To achieve ripple cancellation using the FBRCC topology, the inequality of Equation (6) must be satisfied:

V.sub.C.sub.aux≧V.sub.FB.sub._.sub.pk=½V.sub.ripple  (6)

[0059] where v.sub.Caux is the C.sub.aux voltage which contains a 120 Hz ripple voltage component on the average DC voltage. V.sub.FB.sub._.sub.pk is the peak value of the FBRCC output voltage (v.sub.FB), which is determined by the PFC output voltage ripple, V.sub.ripple.

[0060] To accommodate both feedback loops in the floating capacitor FBRCC controller (FIG. 4A), the controller handles the following two tasks separately: (i) tracking the shape and magnitude of the periodic AC ripple, and (ii) compensating the auxiliary stage loss. According to this control strategy, it is assumed that the FBRCC loss changes slowly (i.e., the FB RCC loss value is substantially flat) so that it can be considered as a DC value in one half-line cycle, which is practical for a fixed-load LED driver.

[0061] As shown in FIG. 4A, the fast PI loop tracks the AC ripple reference (v.sub.ripple.sub._.sub.main) and provides an ideal sinusoidal pulse width modulation (SPWM) control output (v.sub.spwm1), while the slow PI loop regulates the floating capacitor voltage (V.sub.Caux) which generates a DC control voltage (v.sub.spwm2). These two controlling outputs are added together as v.sub.spwm.sub._.sub.sum and then compared to a saw-tooth wave to generate SPWM driver signals for the four switches (Q.sub.1˜Q.sub.4) in the FBRCC. As a result, the FBRCC outputs an inverted AC voltage ripple with a very small negative DC voltage bias, as shown in FIG. 5C.

[0062] It should be noted that this negative DC voltage bias in the FBRCC output (v.sub.FB) will not affect the AC ripple reference (v.sub.ripple.sub._.sub.main) and the normal operation of the fast loop in the bipolar ripple cancellation because it is a DC signal (according to the assumption). All the DC information existing in the PFC output is blocked by the analog differential circuit before it becomes the reference for the fast loop. Therefore, the reference signals of the two loops are decoupled and both loops are able to operate stably and simultaneously.

FBRCC Input Capacitor C.SUB.aux .Design

[0063] To avoid the under-cancellation phenomenon shown in FIG. 5B, the C.sub.aux value is critical. Its voltage changes periodically at double the line frequency, corresponding to energy exchanging in the FBRCC. The design should ensure that the voltage across C.sub.aux is always higher than the auxiliary output voltage, v.sub.FB, at any time instant.

[0064] Under the assumption that the FBRCC is operating at a switching frequency much higher than the double line frequency, i.e., f.sub.xw>>2*f.sub.line), the C.sub.aux capacitance value is designed according to the LED current (I.sub.LED), the AC line voltage frequency (f.sub.line), the allowed input voltage ripple (V.sub.Caux.sub._.sub.ripple), the average input voltage (V.sub.Caux.sub._.sub.avg), as well as the peak-to-peak output voltage of the FBRCC (V.sub.ripple), as shown by Equation (7).

[00002]$\begin{array}{cc}{C}_{\mathrm{aux}}\ge \frac{I_{\mathrm{LED}}.Math.V_{\mathrm{ripple}}}{4.Math.\pi .Math.f_{\mathrm{line}}.Math.V_{C_{\mathrm{aux\_avg}}}.Math.V_{C_{\mathrm{aux\_ripple}}}}& \left(7\right)\end{array}$

[0065] The capacitor C.sub.aux selected based on Equation (7) ensures that the FBRCC output substantially or completely cancels the ripple component in the LED lamp current, I.sub.LED. A detailed derivation is shown in Example 2.

Design Procedure

[0066] In light of the analysis discussed above, an example of a design procedure for an LED driver with a floating capacitor bipolar ripple cancellation stage (FBRCC) may be carried out as follows:

A. Selection of Voltage Rating of the FBRCC Input Capacitor C.SUB.aux

[0067] A multi-layer ceramic capacitor is a good choice for the FBRCC input capacitor due to its small size and low cost as compared to a film capacitor. However, high-capacitance ceramic capacitors (e.g., >10 μF) become expensive or unavailable when the required DC voltage rating is over e.g., 50 V. Therefore, the design limitation of 50 V C.sub.aux voltage rating may be used in a practical design. The FBRCC switch ratings and the allowable PFC voltage ripple can be selected accordingly.

B. Selection of the FBRCC MOSFETs and Design of the Ripple Cancellation Circuit

[0068] The voltage stress of the full bridge switches is the voltage across C.sub.aux and is therefore less than 50 V, as discussed above. In order to reduce losses, MOSFETs with a low drain-to-source voltage V.sub.ds, low R.sub.ds(on), and low total gate charge Q.sub.g are preferred. For example, MOSFETs with a voltage rating of 30 V may be used. The parameters and rating values of the full bridge output inductor (L.sub.FB) and output capacitor (C.sub.FB) may be selected as 47 μH and 4.7 μF 50V.

C. Selection of PFC Stage Output Capacitance

[0069] The following three points should be taken into consideration when selecting the optimal PFC output capacitance:

[0070] i. The peak voltage of the double line frequency ripple should be limited to be less than the average output voltage of the LED load to ensure a high power factor for the PFC stage, as per Equation (8).

½V.sub.ripple≧V.sub.LED  (8)

[0071] ii. Although the double line frequency component is removed from the LED output current by the bipolar ripple cancellation stage, a high switching-frequency component is introduced. A higher PFC output capacitance helps to dampen this high frequency component.

[0072] iii. C.sub.main serves as an energy storage component in the main stage to buffer the power difference and mitigate the load current ripple. V.sub.ripple is inversely proportional to C.sub.main, according to Equation (5). Minimizing the PFC output capacitance and limiting the double line frequency voltage ripple is a trade-oft; which affects the maximum voltage stress on the PFC output capacitor as expressed in Equation (9) and the voltage stress on the switches in the FBRCC.

V.sub.main.sub._.sub.pk=V.sub.LED+½V.sub.ripple  (9)

[0073] Based on the foregoing, a LED driver may be designed to meet the specifications shown in Table 1.

TABLE-US-00001 TABLE 1 Specifications of LED driver V.sub.in V.sub.LED I.sub.LED P.sub.O f.sub.line 85~265 Vac ≈150 Vdc 0.7 A 100 W 60 Hz

[0074] With the specified LED current, the amplitude of the 120 Hz ripple of the PFC voltage depends on the output capacitance value, according to Equation (5), and increases dramatically when the output capacitance is less than 100 uF, as shown in FIG. 6.

[0075] In this example the peak-to-peak ripple voltage is 40 V (the peak value is 20 V) when the output capacitance is set to 44 μF. Therefore, two 22 μF film capacitors may be used in parallel resulting in a 120 Hz ripple of about 40 V peak-to-peak. The maximum PFC output voltage of the PFC stage is 150+20=170 V (less than the 250 V capacitor voltage rating).

D. Selection of FBRCC Input Capacitor C.SUB.aux

[0076] In order to satisfy the inequality of Equation (6), the average value of the input capacitor voltage, V.sub.Caux.sub._.sub.avg, may be selected as 35 V with a maximum 10 V peak-to-peak ripple, V.sub.Caux.sub._.sub.ripple so that the allowed minimum input voltage is 30 V, which is a reasonable value to ensure normal bipolar operation of the FBRCC. Parameters for C.sub.aux selection are listed in Table 2.

TABLE-US-00002 TABLE 2 C.sub.aux Design Parameters T.sub.sw V.sub.FB.sub.—.sub.pk V.sub.Caux.sub.—.sub.avg V.sub.Caux.sub.—.sub.ripple 1/156 kHz 20 V 35 V 10 V (peak-peak)

[0077] Substitution of the values in Table 2 into Equation (7) yields a minimal requirement (C.sub.aux≦106 μF) for the FBRCC input capacitor value to avoid the under-cancellation phenomenon. Therefore, C.sub.aux may be selected as 120 μF (e.g., 10 μF×12, 50V 1206 ceramic capacitors may used).

E. C.sub.FB and C.sub.aux Layout Considerations to Suppress Audible Noise

[0078] A ceramic capacitor expands when a voltage is applied and contracts when the voltage is reduced. The printed circuit board (PCB) flexes as the capacitor changes size because the ends of the capacitor are mechanically coupled to the PCB through solder. Applying the voltage ripple at an audible frequency makes the PCB operate as a transducer (i.e., a loudspeaker). In a practical design, both C.sub.FB and C.sub.aux may be processing power at 120 Hz. Particular measures may be taken to suppress the audible noise.

[0079] For example, the 12 ceramic capacitors selected according to the above description may soldered on both sides of the PCB, six on the top layer and six on the bottom layer, back to back. In this way, the tension caused by the capacitors at the top side is offset by the tension caused by the capacitors on the bottom side. Therefore, the audible noise may be suppressed. In addition, providing a slot on both sides of the PCB may also help to reduce the noise.

Analysis of Operation

[0080] Two operating modes of the ripple cancellation circuit are shown in FIG. 7. The four MOSFET's Q.sub.1˜Q.sub.4 conduct diagonally to provide paths for the LED current I.sub.LED. When the FBRCC output is higher than the reference, Q.sub.2 and Q.sub.3 are conducting while Q.sub.1 and Q.sub.4 are off; when the FBRCC stage output is lower, Q.sub.1 and Q.sub.4 are conducting while Q.sub.2 and Q.sub.1 are off. The PI loop (the fast PI in FIG. 4A) in the ripple cancellation section features high bandwidth to provide a quick AC reference tracking ability. Since the FBRCC output current is the LED current (a DC current), from a power flow point of view, the FBRCC stage is different from the traditional single-phase full bridge inverter in that the circuit does not contribute DC power to the LED load. It instead acts as a reservoir to buffer the power difference and completes an exchange of instantaneous power with the load once every half of a line cycle. The power loss of the bipolar ripple cancellation stage is offset by absorbing the energy from output side of the FBRCC to the floating capacitor (and the control strategy described above with reference to FIG. 4A), so that the input voltage of the FBRCC is always higher than its output voltage.

Advantages of the Embodiments

[0081] The embodiments described herein may provide one or more of the following advantages, relative to conventional single-stage approaches.

[0082] 1. Low-Voltage-Rating Components in the Cancellation Stage

[0083] The four MOSFETs Q.sub.1˜Q.sub.4 conduct diagonally to provide paths for the output current I.sub.LED as shown in FIG. 7. According to features of the FBRCC topology, it sees the component stress equal to half of the double line frequency ripple, shown in (10).

V.sub.FB,max≧½V.sub.ripple  (10)

[0084] where V.sub.FB, max is the voltage stress of the switches in the FBRCC.

[0085] Therefore, the embodiments present a double voltage ripple cancellation ability (given the components voltage stress in the additional stage are the same), compared to existing unipolar cancellation methods. The embodiments are therefore more beneficial for high power, high voltage LED driver applications, where low cost of auxiliary circuits is required.

[0086] 2. Applicable to Both Isolated and Non-Isolated PFC Topologies

[0087] The offset control loop ensures that cancellation stage loss is offset from the output side of the FBRCC. Therefore, no auxiliary winding is required to provide power for the FBRCC with a floating capacitor. Therefore, the embodiments provide a more cost effective and more flexible solution applicable for both isolated and non-isolated LED driver applications.

[0088] 3. Suitable for Variable Output Voltage LED Drivers

[0089] The embodiments may be adapted to different LED-load combinations, to provide drivers that can handle a wide output voltage range under the rated output current. For example, the ratio of the highest specification over the lowest specification may be higher than 2 times (e.g., V.sub.LED=60˜150V). With the prior ripple cancellation technologies, given that the auxiliary transformer winding turn ratio is fixed, the component voltage rating has to be overdesigned under low output voltage operation (e.g., V.sub.LED<150 V) to fit the voltage stress at the highest output voltage operation (e.g., V.sub.LED=150 V), resulting a non-optimal solution.

[0090] For the floating capacitor ripple cancellation method, the minimal C.sub.aux voltage of the FBRCC, v.sub.Caux, should be higher than the peak ripple voltage at the main output, 0.5 V.sub.ripple (e.g., by about 10%) to ensure full cancellation of the double line frequency voltage ripple, according to Equation (6).

[0091] Equation (5) shows that the peak to peak value of the double line frequency voltage ripple in PFC output, V.sub.ripple, is only proportional to the LED output current I.sub.LED as well as the PFC output capacitance C.sub.main, given the line frequency f.sub.line is fixed. Therefore, the voltage stress of the floating capacitor (C.sub.aux) is designed based on the highest LED current I.sub.LED as the worst case.

[0092] Compared to the prior cancellation technologies where the input capacitor voltage is determined by the LED driver DC output voltage (because the input capacitor is connected by an auxiliary winding from the PFC stage), the floating capacitor FBRCC embodiments feature significantly reduced component voltage stress and energy loss. As a result, the embodiments solve the existing overdesigning problem on the component voltage rating in the FBRCC at low output voltage operation for variable-output-voltage LED drivers, and reduce component costs in the auxiliary circuits.

[0093] 4. High Efficiency

[0094] The embodiments provide high efficiency, since the FBRCC does not contribute DC power to the load and does not suffer from power losses due to an auxiliary winding and diode.

[0095] Embodiments will be further described by way of the following Examples. For the sake of brevity, certain practical design considerations, such as power loss and parasitic elements, are ignored in the Examples.

Example 1. Experimental Prototype

[0096] A single-stage flyback LED driver with a bipolar ripple cancellation converter stage and floating capacitor was built according to the design procedure described above and the following specifications: V.sub.LED≈150 V, I.sub.LED=0.7 A, P.sub.O=100 W.

[0097] The PFC output capacitance C.sub.main was 56 μF, thus the 120 Hz ripple of the PFC output voltage V.sub.ripple was 34 V (peak-to-peak) according to Equation (5).

[0098] The circuit parameters are given in Table 3 below.

TABLE-US-00003 TABLE 3 Circuit parameters of the experimental prototype Specifications of LED driver Line input voltage (v.sub.in) 85~265 V LED output voltage (V.sub.LED) ≈150 V LED output current (I.sub.LED) 0.7 A Output power (P.sub.O) 100 W Line frequency (f) 60 Hz Active Clamp Single-Stage Flyback PFC Output Capacitor (C.sub.main) 56 μF (250 V film) Switches (Q.sub.main Q.sub.aux) SPP11N80C3 Diode (D) C3D16060 Turns Ratio (N.sub.p:N.sub.s) 1.2:1 Magnetizing Inductance (L.sub.m) 1300 μH Internal Leakage Inductor (L.sub.lek) 33 μH External Leakage Inductor (L.sub.ext) 15 μH Active Clamp Capacitor (C.sub.clamp) 68 nF × 4 (400 V film) Single-stage PFC Controller NCP1652A FBRCC stage Switching Frequency (f.sub.sw) 156 KHz Floating Input Capacitor (C.sub.aux) 100 μF (10 μF × 10, 50 V 1206 ceramic) Output Inductor (L.sub.FB) 50 μH Output Capacitor (C.sub.FB) 4.7 μF (50 V 1206 ceramic) MOSFETs (Q.sub.1~Q.sub.4) FDS5692ZCT-NDx4 (50 V, 24 mΩ) LED String Load LED Chip Part Number XMLEZW-02-0000-0B00T527Fx27 Forward Voltage/pcs (V.sub.j) Typ 6 V Max Current (I.sub.max) 2 A Luminous Flux/pcs @ 670 mA 270 lm

[0099] In order to satisfy the inequality (6), the average value of the floating capacitor voltage, V.sub.Caux.sub._.sub.avg, was selected as 35 V with a maximum 10 V peak-to-peak ripple, V.sub.Caux.sub._.sub.ripple, so that the allowed minimum input voltage is 30 V which is a reasonable value to ensure bipolar ripple cancellation of the FBRCC.

[0100] Design parameters for C.sub.aux are listed in Table 4.

TABLE-US-00004 TABLE 4 C.sub.aux design parameters T.sub.sw V.sub.ripple V.sub.Caux.sub.—.sub.avg V.sub.Caux.sub.—.sub.ripple 1/156 kHz 34 V 35 V 10 V

[0101] Substituting the values in Table 4 into Equation (7) yields a minimal requirement (C.sub.aux≧91 μF) for FBRCC input capacitance (C.sub.aux) to avoid under compensation. C.sub.aux was selected as 100 μF in the (10 μF×10, 50 V 1206 ceramic capacitors).

[0102] FIG. 8 shows that the FBRCC stage input voltage v.sub.Caux is regulated at 35±5 V by the loss offset loop. The FBRCC stage exhibits a slight negative DC voltage bias of 1.2 V at the FBRCC stage output voltage. This experimental result validates the previous analysis for FIG. 5C.

[0103] FIG. 9 shows the input voltage and input current waveforms, and that the embodiment achieved a high PF of 0.994.

[0104] FIGS. 10A and 10B compare the performance of the experimental prototype and a conventional single stage LED driver configuration, respectively. FIG. 10A shows that the embodiment produces a smaller LED driving current ripple at 120 Hz (7.8 mA RMS) with only 60.7 μF total output capacitance (C.sub.main+C.sub.FB), compared to a higher 8.2 mA RMS current ripple in the conventional single-stage LED driver, where 4700 μF output capacitance is required, as shown in FIG. 10B. Therefore, the total required output capacitance of the conventional signal-stage approach was reduced by 98.7% by the experimental prototype. Also, it should be noted that only C.sub.main is of a high voltage rating, while both C.sub.FB and C.sub.aux are low-voltage-rating components.

[0105] FIGS. 11A and 11B show the efficiency and power factor, respectively, as a function of input voltage. It can be seen that the experimental prototype had an efficiency of 91% when v.sub.in=110 Vac, and a peak efficiency of 92.5%. The power factor was greater than 0.95 for the entire input voltage range. The FBRCC stage loss is generally less than 1% under the range of input voltage, as shown in FIG. 12.

[0106] Dimming performance of the LED driver was measured and is shown in FIG. 13. The results show that the half-load (P.sub.O=50 W, V.sub.LED≈150 V) system efficiency is generally higher than 88.5% and the PF is over 0.9 under both the nominal input voltages (110 Vac and 220 Vac).

Example 2. FBRCC Floating Capacitor C.SUB.aux .Design Rule Derivation

[0107] The C.sub.aux input voltage comprises a DC average voltage and a changing double-line-frequency voltage ripple resulting from the charging and discharging of the capacitor by the LED current, I.sub.LED.

[00003]$\begin{array}{cc}{v}_{C_{\mathrm{aux}}}=V_{C_{\mathrm{aux}.Math..Math.\_.Math..Math.\mathrm{avg}}}+v_{C_{\mathrm{aux}.Math..Math.\_.Math..Math.\mathrm{ripple}}}& \left(11\right)\end{array}$

[0108] According to the operation modes of the ripple cancellation converter, the input capacitor C.sub.aux is charged when Q.sub.2 and Q.sub.3 are conducting (Q.sub.1 and Q.sub.4 are off) and it is discharged when Q.sub.1 and Q.sub.4 are conducting (Q.sub.2 and Q.sub.3 are off). These two intervals are shown in the following equations.

T.sub.charge=T.sub.sw.Math.(1−D)  (12)

T.sub.discharge=T.sub.sw.Math.D  (13)

[0109] where T.sub.sw is the switching period of the ripple cancellation converter and D is the duty cycle of the driving signals for Q.sub.1 and Q.sub.4, as shown in the following equation.

D(t)=½+½.Math.M.Math.sin(2ωt)  (14)

[0110] where ω is the angular frequency of the line voltage and M is the modulation index of the SPWM, expressed as (15).

[00004]$\begin{array}{cc}M=\frac{\frac{1}{2}.Math.V_{\mathrm{ripple}}}{V_{C_{\mathrm{aux\_avg}}}}& \left(15\right)\end{array}$

[0111] Since the average current going through the switches is fixed by the load, the difference between the charging time and the discharging time of each switching cycle determines the behaviour of the input current, leading to the increase or decrease of the input voltage. The charge for each switching cycle can be expressed by the following equation.

[00005]$\begin{array}{cc}\begin{array}{c}{Q}_{\mathrm{discharge}}\left(t\right)=.Math.I_{\mathrm{LED}}.Math.\left(T_{\mathrm{discharge}}\left(t\right)-T_{\mathrm{change}}\left(t\right)\right)\\ =.Math.I_{\mathrm{LED}}.Math.T_{\mathrm{sw}}.Math.M.Math.\sin \left(2.Math.\omega .Math..Math.t\right)\end{array}\hspace{1em}& \left(16\right)\end{array}$

[0112] The sum of discharge is expressed by the following equation.

[00006]$\begin{array}{cc}\begin{array}{c}{Q}_{\mathrm{discharge\_sum}}\left({\mathrm{nT}}_{\mathrm{sw}}\right)=.Math.\underset{i=0}{\overset{{\mathrm{nT}}_{\mathrm{sw}}}{.Math.}}.Math.Q_{\mathrm{discharge}}\left(t\right)\\ =.Math.\underset{k=1}{\overset{n}{.Math.}}.Math.I_{\mathrm{LED}}.Math.T_{\mathrm{sw}}.Math.M.Math.\sin \left(2.Math.\omega .Math.{\mathrm{kT}}_{\mathrm{sw}}\right)\end{array}\hspace{1em}& \left(17\right)\end{array}$

[0113] According to the characteristics of the two-level SPWM modulation strategy, the discharging time is always longer than the charging time during the first half cycle of the line frequency before it enters the next half cycle. Therefore, the input capacitor C.sub.aux keeps discharging over each switching cycle and the voltage keeps decreasing until it reaches the valley at the half cycle point. Then the largest voltage drop can be calculated using the following equation.

[00007]$\begin{array}{cc}{V}_{C_{\mathrm{aux\_ripple}}}=\frac{Q_{\mathrm{discharge\_sum}}\left(\frac{T_{\mathrm{line}}}{4}\right)}{C_{\mathrm{aux}}}& \left(18\right)\end{array}$

[0114] This is the worst case because the output voltage is on the peak value simultaneously.

[0115] Q.sub.discharge.sub._.sub.sum(T.sub.line/4) in (18) can be simplified into (19) after mathematical deduction.

[00008]$\begin{array}{cc}\begin{array}{c}{Q}_{\mathrm{discharge\_sum}}\left(\frac{T_{\mathrm{line}}}{4}\right)=.Math.\underset{k=1}{\overset{\frac{T_{\mathrm{line}}}{4.Math.T_{\mathrm{sw}}}}{.Math.}}.Math.I_{\mathrm{LED}}.Math.M.Math.T_{\mathrm{sw}}.Math.\sin \left(\frac{4.Math.\pi .Math..Math.T_{\mathrm{sw}}}{T_{\mathrm{line}}}.Math.k\right)\\ =.Math.\frac{I_{\mathrm{LED}}.Math.M.Math.T_{\mathrm{sw}}}{\tan \left(\frac{2.Math.\pi .Math..Math.T_{\mathrm{sw}}}{T_{\mathrm{line}}}\right)}\end{array}& \left(19\right)\\ \mathrm{Since}.Math..Math.T_{\mathrm{sw}}.Math.<<T_{\mathrm{line}.Math.}.Math.\left(f_{\mathrm{sw}}>>f_{\mathrm{line}}\right),\tan \left(\frac{2.Math.\pi .Math..Math.T_{\mathrm{sw}}}{T_{\mathrm{line}}}\right)\approx \frac{2.Math.{\mathrm{\pi T}}_{\mathrm{xw}}}{T_{\mathrm{line}}}& \left(20\right)\end{array}$

[0116] Then (19) can be further simplified, as shown in (21).

[00009]$\begin{array}{cc}{Q}_{\mathrm{discharge\_sum}}\left(\frac{T_{\mathrm{line}}}{4}\right)=\frac{I_{\mathrm{LED}}.Math.M}{2.Math.\pi .Math.f_{\mathrm{line}}}& \left(21\right)\end{array}$

[0117] where f.sub.line is the AC line voltage frequency.

[0118] Therefore, the FBRCC is able to work normally for the whole line cycle as long as the input valley voltage is set higher than the peak output voltage. The final floating capacitor C.sub.aux design rule is shown in (22).

[00010]$\begin{array}{cc}\begin{array}{c}{C}_{\mathrm{aux\_min}}\ge .Math.\frac{Q_{\mathrm{discharge\_sum}}\left(\frac{1}{4}.Math.T_{\mathrm{line}}\right)}{V_{C_{\mathrm{aux\_ripple}}}}\\ =.Math.\frac{I_{\mathrm{LED}}.Math.V_{\mathrm{ripple}}}{4.Math.\pi .Math.f_{\mathrm{line}}.Math.V_{C_{\mathrm{aux\_avg}}}.Math.V_{C_{\mathrm{aux\_ripple}}}}\end{array}\hspace{1em}& \left(22\right)\end{array}$

Example 3. Alternative Embodiment

[0119] In the above embodiments, the voltage of the floating capacitor may be regulated by a slow voltage control loop. Under certain conditions, the use of the floating capacitor may introduce a low frequency disturbance through the slow voltage control loop, making the control loop more challenging to be designed under a light load.

[0120] The floating capacitor in the bipolar ripple cancellation converter may be powered by an external or secondary DC power supply whose output voltage is higher than the peak value of the double line frequency (e.g., 120 Hz) voltage ripple of the PFC stage. This secondary power supply only offsets the small power lost in the bipolar ripple cancellation converter.

[0121] For example, some power supplies, such as LED drivers, may include a secondary or “house-keeping” power supply to provide regulated power before the main power comes on.

[0122] Such a house-keeping power supply can be used as the power supply for the bipolar ripple cancellation converter as long as its output voltage is regulated to be higher than the peak value of the voltage ripple of the PFC stage at the rated output current. FIG. 14 shows one example of such an embodiment.

[0123] It is noted that such a secondary power supply for the bipolar ripple cancellation converter is not limited to a house keeping power supply. For example, it can be another isolated or non-isolated power converter whose output voltage is DC and is higher than the peak value of the double line frequency voltage ripple of the PFC stage. For instance, the external power supply may be another isolated converter (e.g., a flyback converter), such as the circuit shown in FIG. 15.

[0124] All cited publications are incorporated herein by reference.

EQUIVALENTS

[0125] Those skilled in the art will recognize or be able to ascertain variants of the embodiments described herein. Such variants are within the scope of the invention and are covered by the appended claims.