FIN STRUCTURE FOR FIN FIELD EFFECT TRANSISTOR AND METHOD FOR FABRICATION THE SAME

Abstract

The invention provides a fin structure for a fin field effect transistor, including a substrate. The substrate includes a plurality of silicon fins, wherein a top of each one of the silicon fins is a round-like shape in a cross-section view. An isolation layer is disposed on the substrate between the silicon fins at a lower portion of the silicon fins while an upper portion of the silicon fins is exposed. A stress buffer layer is disposed on a sidewall of the silicon fins between the isolation layer and the lower portion of the silicon fins. The stress buffer layer includes a nitride portion.

Claims

1. A fin structure for a fin field effect transistor, comprising: a substrate, including a plurality of silicon fins, wherein a top of each one of the silicon fins is a round-like shape in a cross-section view; an isolation layer, disposed on the substrate between the silicon fins at a lower portion of the silicon fins while an upper portion of the silicon fins is exposed; and a stress buffer layer, disposed on a sidewall of the silicon fins between the isolation layer and the lower portion of the silicon fins, wherein the stress buffer layer includes a nitride portion, wherein a material of the nitride portion is silicon nitride, wherein the nitride portion is a single layer.

2. The fin structure as recited in claim 1, wherein the substrate includes a silicon wafer or a silicon on insulator (SOI) substrate.

3. The fin structure as recited in claim 1, wherein the isolation layer includes a flowable chemical vapor deposition (FCVD) dielectric layer.

4. The fin structure as recited in claim 3, wherein the FCVD dielectric layer includes flowable oxide.

5. The fin structure as recited in claim 1, wherein the nitride portion of the stress buffer layer is a nitriding part of the stress buffer layer.

6. The fin structure as recited in claim 5, wherein the stress buffer layer includes an amorphous silicon layer.

7. The fin structure as recited in claim 1, further comprising an atomic layer deposition (ALD) layer between the stress buffer layer and each of the silicon fins.

8. A method for fabricating a fin structure for fin field effect transistor, comprising: providing a substrate, including a fin structure having a silicon fin and a single mask layer just on a top of the silicon fin, the single mask layer being as a top portion of the fin structure; forming a stress buffer layer on the substrate and conformally covering over the fin structure; performing a nitridation treatment on the stress buffer layer to have a nitride portion; perform a flowable deposition process to form a flowable dielectric layer to cover over the fin structures; annealing the flowable dielectric layer; and polishing the flowable dielectric layer, wherein the nitride portion of the stress buffer layer is used as a polishing stop.

9. The method for fabricating the fin structure as recited in claim 8, further comprising performing an etching back process on the flowable dielectric layer, the single mask layer and the stress buffer layer, to expose an upper part of the silicon fin.

10. The method for fabricating the fin structure as recited in claim 8, wherein the flowable deposition process is a flowable chemical vapor deposition (FCVD) process for flowable oxide material.

11. The method for fabricating the fin structure as recited in claim 8, wherein the substrate includes a silicon wafer or a silicon on insulator (SOI) substrate.

12. The method for fabricating the fin structure as recited in claim 8, wherein the single mask layer includes an oxide mask layer.

13. The method for fabricating the fin structure as recited in claim 8, wherein the nitride portion in the stress buffer layer is a nitriding part of the stress buffer layer due to a partial nitridation on the stress buffer layer.

14. The method for fabricating the fin structure as recited in claim 8, wherein the nitride portion is a silicon nitride portion and the stress buffer layer is an amorphous silicon layer.

15. The method for fabricating the fin structure as recited in claim 8, further comprising an atomic layer deposition (ALD) layer between the stress buffer layer and each of the silicon fins.

16. The method for fabricating the fin structure as recited in claim 8, further comprising: performing a dielectric etching process to expose an upper portion of the silicon fins, wherein a top of each of the silicon fins is a round-like shape in a cross-section view due to the dielectric etching process.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to make the aforementioned and other objectives and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

[0024] FIGS. 1A-1D are drawings, schematically illustrating a fabrication flow as looking into for forming a fin structure on a substrate in a cross-section view, according to an embodiment of the invention.

[0025] FIGS. 2A-2I are drawings, schematically illustrating a fabrication flow for forming a fin structure on a substrate in a cross-section view, according to an embodiment of the invention.

DESCRIPTION OF THE EMBODIMENTS

[0026] The invention provides the manner to fabricate the FinFETm in which the silicon fin may be fabricated by perform partial nitridation treatment on the stress buffer film (SBF) to convert into nitride. The nitride from the stress buffer film may provide a polishing stop, so that some mask layers to protect fin may be omitted.

[0027] Multiple embodiments are provided for describing the invention but the invention is not just limited to the embodiments.

[0028] FIGS. 1A-1D are drawings, schematically illustrating a fabrication flow as looking into for forming a fin structure on a substrate in a cross-section view, according to an embodiment of the invention.

[0029] Referring to FIG. 1A, as looked into by the invention, to form the thin fins at the upper portion of the substrate 50, multiple dielectric protecting layers, including a pad oxide layer 52, a pad nitride layer 54 and an oxide mask layer 56 are sequentially formed on the substrate 50. The substrate 50 for forming the fin is silicon in an embodiment. The pad oxide layer 52, the pad nitride layer 54 and the oxide mask layer 56 in the usual manner are preliminarily formed and would be involved in the mechanism for the subsequent fin polishing and etching processes.

[0030] Referring to FIG. 1B, the pad oxide layer 52, the pad nitride layer 54, the oxide mask layer 56 and the substrate 50 are patterned to form the silicon fins 80, on which a residual portion of the pad oxide layer 52, the pad nitride layer 54, the oxide mask layer 56 as a stack remain on the top of the silicon fins 80. At current stage, the silicon fins 80 with the stack dielectric at top form as a fin structure. A stress buffer film (SBF) 58 is then form the formed on the substrate 50 and is conformally covering over the fin structure. In addition, before forming the SBF 58 is formed, an atomic layer deposition (ALD) layer as an option may also be formed conformally covering over the fin structures.

[0031] A flowable dielectric layer 60 is formed over the substrate to cover the fin structure, which includes the pad oxide layer 52, the pad nitride layer 54, the oxide mask layer 56 and the silicon fin 80. The flowable dielectric layer 60 in an example is formed by flowable chemical vapor deposition (FCVD) process with the suitable material of oxide. The flowable dielectric layer 60 usually is annealed for curing and increasing density into a hard isolation dielectric with higher density. The SBF 58 as form of amorphous silicon may protect the silicon fin 80 from oxidation in an example and also provide the stress buffer effect to the silicon fin 8o which is thin as viewed in the cross-section structure.

[0032] Referring to FIG. 1C, the flowable dielectric layer 60 after annealing process for curing and increasing density is polished by chemical mechanical polishing (CMP) process. In this polishing process, the nitride layer 54 may serve as the polishing stop.

[0033] Referring to FIG. 1D, to expose the silicon fin 80, a dielectric etching process is performed to remove the upper portion of the flowable dielectric layer 60. Then, the upper portion of the silicon fin 80 is exposed to provide the fin to form the FinFET in the subsequent processes. Here, the descriptions for the subsequent fabrication processes to form the FinFET are omitted and the invention does not limit the subsequent fabrication processes.

[0034] As looked into in the invention, the pad oxide layer 52, the pad nitride layer 54, and the oxide mask layer 56 are involved, so as to provide the fin polishing stop and resist the dielectric etching process to expose the silicon fin 80.

[0035] As investigated in the invention when looking into the procedure in FIG. 1A to FIG. 1D, the the pad oxide layer 52 and the pad nitride layer 54 may be skipped with slightly modification. As a result, the fabrication may be simplified and the fabrication cost may be reduced.

[0036] FIGS. 2A-2I are drawings, schematically illustrating a fabrication flow for forming a fin structure on a substrate in a cross-section view, according to an embodiment of the invention.

[0037] Referring to FIG. 2A, a substrate 100, such as a silicon wafer or a silicon on insulator (SOI) substrate is provided. The substrate 100 provide the semiconductor property to form the channel latter for the FinFET. In an embodiment, the mask layer 102 as a single layer is preliminarily formed on the substrate 100. As noted in viewing to FIG. 1A, a single mask layer is formed. The mask layer 102 is an oxide layer in an embodiment.

[0038] To form the thin fins in an embodiment, a plurality of mandrels 104 with the intended width is formed on the mask layer 102. A spacer 106 is formed on the sidewall of the mandrels 104. There, the thickness of the spacer 106 is reserved, corresponding to the width of the fin as to be formed form the FinFET.

[0039] Referring to FIG. 2B, the mandrels 104 are removed while the spacer 106 remains. At this stage, a portion of the mask layer 102 as previously cover by the mandrels 104 is exposed.

[0040] Referring to FIG. 2D, the spacer 106 is used as the etching mask to etch the substrate 100 through the mask layer 102. Due to the etching selectivity as set, the substrate 100 in silicon and the spacer 106 in oxide are etched. After etching process, the silicon fins 110 are formed at the upper portion of the substrate 100. A residual portion of the mask layer 102 is still disposed on top of the silicon fin 110. The gap between the fins form the trench 108 to expose the substrate 100 and the sidewall of the silicon fin 110.

[0041] Referring to FIG. 2E, a SBF 112 is formed conformally covering over the fin structure as composed of the silicon fin 110 and the mask layer 102 at the top. As also previously stated, an ALD layer as an option may be formed before forming SBF 112. The material of the SBF 112 is amorphous silicon to protect the silicon fin 110 in the subsequent annealing process at the high temperature. As noted, the thickness of the SBF 112 is actually rather thinner than the fin width. The drawing is not at the actual scale as should be noted.

[0042] In an embodiment of the invention, after the SBF 112 is formed, a nitridation treatment 114 is performed on the SBF 112. Due to the property of the amorphous silicon of the SBF 112, the SBF 112 may be partially nitridation to partially form nitride in the SBF 112.

[0043] Referring to FIG. 2F, here, the SBF 112 in an embodiment is not in full nitridation to completely convert into silicon nitride. At the stage, the previous SBF 112 is then changed to the SBF 112′, which partially include the nitride portion. This nitride portion may provide as the polishing stop and the silicon material as remined may resist oxidation layer to the silicon fin 110 for protection effect as to be described.

[0044] Referring to FIG. 2G, a flowable dielectric layer 116, such as flowable oxide, is formed over the substrate 100 to fully fill into the trench 108 and cover the SBF 112′. An annealing process is performed on the flowable dielectric layer 116 for curing and increasing density. The silicon material in the SBF 112′ may provide the stress buffering effect on the silicon fin 110. In addition, the annealing process may also cause oxidation on the silicon material. However, the silicon fin 110 is protected by the SBF 112′, which still contains silicon material. The annealing process may be oxidized the SBF 112′ but significantly not on the silicon fin 110.

[0045] Referring to FIG. 2H, after annealing process for curing and increasing density on the flowable dielectric layer 116, the polishing process is performed over the substrate 100. It should be noted that the SBF 112′ contains nitride portion due to the nitridation treatment 114 in FIG. 2E. The nitride portion may serve as the polishing stop to replace the nitride layer 54 as stated in FIG. 1C although the nitride layer 54 is not actually formed in the embodiment.

[0046] Referring to FIG. 2I, a dielectric etching process is performed to the flowable dielectric layer 116 to remove its upper portion. Also, the mask layer 102 and the SBF 112′ are also removed in the same etching process. As a result, the upper portion of the silicon fin 110 is exposed to provide the fin for forming the FinFET in the subsequent fabrication process.

[0047] As noted in the fabrication procedure, the nitride layer 54 and the pad oxide layer 52, referring to FIG. 1A, are saved in the invention. In addition, the nitridation treatment 114 as referring to FIG. 2E is additionally performed on the SBF 112 to change into the SBF 112′ with nitride portion to provide the polishing stop instead of the nitride layer 54.

[0048] As also noted, the SBF 112′ at the lower sidewall of the silicon fin 110 contains the nitride portion. The top of the silicon fin 110 in the embodiment just has the single mask layer 102, which may be relatively weak to resist the dielectric etching process to expose the silicon fin 110. As a result, the top of the silicon fin 110 is a round-like shape as viewed in cross-section while comparing to FIG. 1D in an example. However, the round-like shape at the cross-section view does not significantly affect the channel function for the FinFET when the gate line perpendicularly crossing over the silicon fin 110, which is actually a fin line in structure as formed.

[0049] Although the invention is described with reference to the above embodiments, the embodiments are not intended to limit the invention. A person of ordinary skill in the art may make variations and modifications without departing from the spirit and scope of the invention. Therefore, the protection scope of the invention should be subject to the appended claims.