DELAY-COMPENSATING POWER MANAGEMENT CIRCUIT

Abstract

A delay-compensating power management circuit is provided. The power management circuit includes a power management integrated circuit (PMIC) configured to generate a time-variant voltage(s) based on a time-variant target voltage(s) for amplifying an analog signal(s) associated with a time-variant power envelope(s). A voltage processing circuit is provided in the power management circuit to determine a temporal offset, which can be positive or negative, between the time-variant power envelope(s) and the time-variant target voltage(s). Accordingly, the voltage processing circuit modifies the time-variant target voltage(s) to substantially reduce the determined temporal offset and thereby realign the time-variant target voltage(s) with the time-variant power envelope(s). By realigning the time variant target voltage(s) with the time-variant power envelope(s), it is possible to align the time-variant voltage(s) with the time-variant power envelope(s) to reduce distortions (e.g., amplitude clipping) during amplification of the analog signal.

Claims

1. A power management circuit comprising: a voltage processing circuit configured to: determine a temporal offset between a time-variant power envelope of an analog signal and a time-variant target voltage corresponding to the time-variant power envelope; and generate a time-variant modified target voltage that is time-adjusted relative to the time-variant power envelope to thereby substantially reduce the determined temporal offset between the time-variant target voltage and the time-variant power envelope; and a power management integrated circuit (PMIC) configured to generate a time-variant voltage based on the time-variant modified target voltage for amplifying the analog signal.

2. The power management circuit of claim 1 wherein: the time-variant target voltage is delayed from the time-variant power envelope by the temporal offset; and the voltage processing circuit is further configured to: determine a positive temporal offset between the time-variant power envelope and the time-variant target voltage; and generate the time-variant modified target voltage based on the determined positive temporal offset to time-advance the time-variant target voltage to thereby substantially reduce the determined positive temporal offset.

3. The power management circuit of claim 1 wherein: the time-variant power envelope is delayed from the time-variant target voltage by the temporal offset; and the voltage processing circuit is further configured to: determine a negative temporal offset between the time-variant power envelope and the time-variant target voltage; and generate the time-variant modified target voltage based on the determined negative temporal offset to time-delay the time-variant target voltage to thereby substantially reduce the determined negative temporal offset.

4. The power management circuit of claim 1 wherein the voltage processing circuit is further configured to receive the time-variant target voltage from a transceiver circuit coupled to the voltage processing circuit via a communication bus.

5. The power management circuit of claim 4 wherein the voltage processing circuit is further configured to receive the temporal offset from the transceiver circuit.

6. The power management circuit of claim 1 wherein the voltage processing circuit is further configured to receive the time-variant target voltage and the time-variant power envelope from a transceiver circuit coupled to the voltage processing circuit via a communication bus.

7. The power management circuit of claim 6 further comprises a delay detector circuit configured to: dynamically determine the temporal offset between the time-variant target voltage and the time-variant power envelope; and provide the determined temporal offset to the voltage processing circuit.

8. The power management circuit of claim 1 wherein the voltage processing circuit is further configured to generate the time-variant modified target voltage as a function of a modulated modifier.

9. The power management circuit of claim 8 wherein the voltage processing circuit is further configured to generate the time-variant modified target voltage based on an equation expressed as:
V.sub.TGT-R(t)=V.sub.TGT(t)+K.sub.MOD(t)*(V.sub.TGTMAX−V.sub.TGT(t)); wherein: V.sub.TGT-R(t) represents the time-variant modified target voltage; V.sub.TGT(t) represents the received time-variant target voltage; K.sub.MOD(t) represents the modulated modifier; and V.sub.TGTMAX represents an estimated maximum value of the received time-variant target voltage V.sub.TGT(t).

10. The power management circuit of claim 8 wherein the voltage processing circuit is further configured to determine the modulated modifier as a function of a linear term and a nonlinear term.

11. The power management circuit of claim 10 wherein the voltage processing circuit is further configured to determine the modulated modifier based on an equation expressed as:
K.sub.MOD(t)=K.sub.MODLINEAR(t)*NL.sub.GAIN(dV.sub.TGT(t)/dt); wherein: K.sub.MOD(t) represents the modulated modifier; K.sub.MODLINEAR(t) represents the linear term; and NL.sub.GAIN(dV.sub.TGT(t)/dt) represents the nonlinear term.

12. The power management circuit of claim 10 wherein the voltage processing circuit is further configured to determine the linear term as a function of a temporal offset and a voltage offset corresponding to the temporal offset.

13. The power management circuit of claim 12 wherein the voltage offset is predetermined based on the temporal offset and stored in the voltage processing circuit.

14. The power management circuit of claim 13 wherein the voltage processing circuit is further configured to determine the linear term based on an equation expressed as:
K.sub.MODLINEAR(t)=K.sub.OFFSET(dT)+[dV.sub.TGT(t)/dt]*dT; /[V.sub.TGTMAX−V.sub.TGT(t)]; wherein: K.sub.MODLINEAR(t) represents the linear term; dT represents the temporal offset; K.sub.OFFSET(dT) represents the voltage offset corresponding to the temporal offset; V.sub.TGT(t) represents the received time-variant target voltage; and V.sub.TGTMAX represents an estimated maximum value of the received time-variant target voltage V.sub.TGT(t).

15. The power management circuit of claim 12 wherein: the time-variant power envelope of the analog signal comprises a plurality of amplitude peaks; the time-variant modified target voltage comprises a plurality of voltage peaks each corresponding to a respective one of the plurality of amplitude peaks; and the voltage offset is selected to cause each of the plurality of voltage peaks to be higher than the respective one of the plurality of amplitude peaks.

16. A power management apparatus comprising: a transceiver circuit configured to generate a time-variant power envelope of an analog signal and a time-variant target voltage corresponding to the time-variant power envelope; a power management circuit comprising: a voltage processing circuit configured to: determine a temporal offset between the time-variant power envelope and the time-variant target voltage; and generate a time-variant modified target voltage that is time-adjusted relative to the time-variant power envelope to thereby substantially reduce the determined temporal offset between the time-variant target voltage and the time-variant power envelope; and a power management integrated circuit (PMIC) configured to generate a time-variant voltage based on the time-variant modified target voltage; and a power amplifier configured to amplify the analog signal based on the time-variant voltage.

17. The power management apparatus of claim 16 wherein: the time-variant target voltage is delayed from the time-variant power envelope by the temporal offset; and the voltage processing circuit is further configured to: determine a positive temporal offset between the time-variant power envelope and the time-variant target voltage; and generate the time-variant modified target voltage based on the determined positive temporal offset to time-advance the time-variant target voltage to thereby substantially reduce the determined positive temporal offset.

18. The power management apparatus of claim 16 wherein: the time-variant power envelope is delayed from the time-variant target voltage by the temporal offset; and the voltage processing circuit is further configured to: determine a negative temporal offset between the time-variant power envelope and the time-variant target voltage; and generate the time-variant modified target voltage based on the determined negative temporal offset to time-delay the time-variant target voltage to thereby substantially reduce the determined negative temporal offset.

19. The power management apparatus of claim 16 wherein the voltage processing circuit is further configured to receive the time-variant target voltage and the temporal offset from the transceiver circuit.

20. The power management apparatus of claim 16 wherein: the voltage processing circuit is further configured to receive the time-variant target voltage and the time-variant power envelope from the transceiver circuit coupled to the voltage processing circuit; and the power management circuit further comprises a delay detector circuit configured to: dynamically determine the temporal offset between the time-variant target voltage and the time-variant power envelope; and provide the determined temporal offset to the voltage processing circuit.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The accompanying drawings incorporated in and forming a part of this specification illustrate several aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.

[0012] FIG. 1A is a schematic diagram of an exemplary existing power management circuit that may cause amplitude distortion in an analog signal;

[0013] FIG. 1B is a graphic diagram providing an exemplary illustration of a positive temporal offset between a time-variant power envelope of the analog signal and a time-variant target voltage that may occur in the existing power management circuit of FIG. 1A;

[0014] FIG. 1C is a graphic diagram providing an exemplary illustration of a negative temporal offset between a time-variant power envelope of the analog signal and a time-variant target voltage that may occur in the existing power management circuit of FIG. 1A;

[0015] FIG. 1D is a graphic diagram providing an exemplary illustration as to how the positive temporal offset in FIG. 1B can cause amplitude distortion to the analog signal in FIG. 1A;

[0016] FIG. 2 is a schematic diagram of an exemplary power management circuit configured according to embodiments of the present disclosure to realign a time-variant target voltage with a time-variant power envelope of an analog signal;

[0017] FIG. 3 is a graphic diagram providing an exemplary illustration of a modified target voltage that is time-adjusted relative to the time-variant power envelope in FIG. 2 to substantially reduce a positive temporal offset between the time-variant target voltage and the time-variant power envelope; and

[0018] FIG. 4 is a graphic diagram providing an exemplary illustration of a voltage headroom between the time-variant modified target voltage and the time-variant power envelope of FIG. 3.

DETAILED DESCRIPTION

[0019] The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

[0020] It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

[0021] It will be understood that when an element such as a layer, region, or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being “over” or extending “over” another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly over” or extending “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.

[0022] Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.

[0023] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including” when used herein specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

[0024] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0025] Aspects disclosed in the detailed description include a delay-compensating power management circuit. The power management circuit includes a power management integrated circuit (PMIC) configured to generate a time-variant voltage(s) based on a time-variant target voltage(s) for amplifying an analog signal(s) associated with a time-variant power envelope(s). A voltage processing circuit is provided in the power management circuit to determine a temporal offset, which can be positive or negative, between the time-variant power envelope(s) and the time-variant target voltage(s). Accordingly, the voltage processing circuit modifies the time-variant target voltage(s) to substantially reduce the determined temporal offset and thereby realign the time-variant target voltage(s) with the time-variant power envelope(s). By realigning the time variant target voltage(s) with the time-variant power envelope(s), it is possible to align the time-variant voltage(s) with the time-variant power envelope(s) to reduce distortions (e.g., amplitude clipping) during amplification of the analog signal.

[0026] Before discussing a power management circuit of the present disclosure, starting at FIG. 2, a brief overview of an existing power management circuit that may cause amplitude distortion in an analog signal as a result of misalignment between a time-variant target voltage and a time-variant power envelope of the analog signal is first provided with reference to FIGS. 1A-1D.

[0027] FIG. 1A is a schematic diagram of an exemplary existing power management circuit 10 that that may cause amplitude distortion in an analog signal 12. The existing power management circuit 10 is configured to provide a time-variant voltage V.sub.CC(t) to a power amplifier 14 for amplifying the analog signal 12. The analog signal 12 may be generated by a transceiver circuit 16 and provided to a signal processing circuit 18 in an intermediate frequency (IF). The signal processing circuit 18 may upconvert the analog signal 12 from the IF to a carrier frequency and provide the analog signal 12 to the power amplifier 14 for amplification.

[0028] The analog signal 12 is associated with a time-variant power envelope 20 that rises and falls over time. Thus, to prevent potential amplitude distortion in the analog signal 12 and ensure higher operating efficiency of the power amplifier 14, it is necessary for the existing power management circuit 10 to generate the time-variant voltage V.sub.CC(t) to closely track the time-variant power envelope 20. In other words, the time-variant voltage V.sub.CC(t) needs to be time aligned with the time-variant power envelope 20 as closely as possible. Herein, a signal is said to be time aligned with another signal when a time difference between the two signals is neglectable (e.g., <±1 μs).

[0029] As such, the transceiver circuit 16 is configured to generate a time-variant target voltage V.sub.TGT(t) that is time aligned with the time-variant power envelope 20 of the analog signal 12. The transceiver circuit 16 then provides the time-variant target voltage V.sub.TGT(t) and the analog signal 12 substantially concurrently to the existing power management circuit 10 and the signal processing circuit 18, respectively. Accordingly, a power management integrated circuit (PMIC) 22 can generate the time-variant voltage V.sub.CC(t) based on the time-variant target voltage V.sub.TGT(t). In this regard, if the time-variant target voltage V.sub.TGT(t) is time aligned with the time-variant power envelope 20, then the time-variant voltage V.sub.CC(t) is expected to be time aligned with the time-variant power envelope 20 as well.

[0030] However, a variety of factors may cause the time-variant target voltage V.sub.TGT(t) to become misaligned from the time-variant power envelope 20 when the time-variant target voltage V.sub.TGT(t) arrives at the PMIC 22, even if the transceiver circuit 16 communicates the time-variant target voltage V.sub.TGT(t) and the analog signal 12 substantially concurrently. For example, the transceiver circuit 16 may communicate the time-variant target voltage V.sub.TGT(t) via a serial bus, such as a radio frequency front-end (RFFE) bus, and communicate the analog signal 12 via a parallel bus, such as a general-purpose input/output (GPIO) bus, or vice versa. The difference in bus speeds may cause the time-variant target voltage V.sub.TGT(t) to fall behind or lead the time-variant power envelope 20 at the PMIC 22.

[0031] In one example, as shown in FIG. 1B, the time-variant target voltage V.sub.TGT(t) can lag behind the time-variant power envelope 20 by a positive temporal offset ΔT when the time-variant target voltage V.sub.TGT(t) arrives at the PMIC 22. In this regard, FIG. 1B is a graphic diagram providing an exemplary illustration of a positive temporal delay ΔT between the time-variant power envelope 20 of the analog signal 12 and the time-variant target voltage V.sub.TGT(t) that may occur in the existing power management circuit 10 of FIG. 1A. As such, to realign the time-variant target voltage V.sub.TGT(t) with the time-variant power envelope 20, it is necessary to delay the time-variant power envelope 20 and/or time-advance the time-variant target voltage V.sub.TGT(t) to eliminate the positive temporal offset ΔT between the time-variant power envelope 20 and the time-variant target voltage V.sub.TGT(t).

[0032] In another example, as shown in FIG. 1C, the time-variant target voltage V.sub.TGT(t) can lead the time-variant power envelope 20 when the time-variant target voltage V.sub.TGT(t) arrives at the PMIC 22. In other words, the time-variant target voltage V.sub.TGT(t) can be said to lag behind the time-variant power envelope 20 by a negative temporal offset −ΔT.

[0033] In this regard, FIG. 1C is a graphic diagram providing an exemplary illustration of a negative temporal delay −ΔT between the time-variant power envelope 20 of the analog signal 12 and the time-variant target voltage V.sub.TGT(t) that may occur in the existing power management circuit 10 of FIG. 1A. As such, to realign the time-variant target voltage V.sub.TGT(t) with the time-variant power envelope 20, it is necessary to delay the time-variant target voltage V.sub.TGT(t) and/or time-advance the time-variant power envelope 20 to eliminate the negative temporal offset −ΔT between the time-variant power envelope 20 and the time-variant target voltage V.sub.TGT(t).

[0034] As a result of the misalignment between the time-variant target voltage V.sub.TGT(t) and the time-variant power envelope 20, the time-variant voltage V.sub.CC(t) is likely misaligned from the time-variant power envelope 20 at the power amplifier 14. As illustrated in FIG. 1D, the misalignment between the time-variant voltage V.sub.CC(t) and the time-variant power envelope 20 can cause amplitude distortion in the analog signal 12.

[0035] In this regard, FIG. 1D is a graphic diagram providing an exemplary illustration as to how the positive temporal offset ΔT in FIG. 1B can cause amplitude distortion to the analog signal 12 in FIG. 1A.

[0036] If the time-variant power envelope 20 and the time-variant voltage V.sub.CC(t) are perfectly aligned, an instantaneous amplitude of the analog signal 12 (not shown), which is represented by a voltage V.sub.S, would substantially equal the time-variant voltage V.sub.CC(t) at time t.sub.x. However, as shown in FIG. 1C, the time-variant voltage V.sub.CC(t) lags behind the time-variant power envelope 20 by a temporal delay At. As such, at time t.sub.x, the power amplifier 14 (not shown) receives a lower voltage V′cc, instead of the time-variant voltage V.sub.CC(t). In this regard, the time-variant voltage V.sub.CC(t) deviates from the time-variant power envelope 20 by a voltage differential Av at time t.sub.x. Consequently, the power amplifier 14 may clip the analog signal 12 to cause an amplitude distortion.

[0037] Although FIG. 1D illustrates the amplitude distortion resulted from the time-variant target voltage V.sub.TGT(t) lagging behind the time-variant power envelope 20 by the positive temporal offset ΔT, it should be understood that such amplitude distortion may also be caused by the time-variant target voltage V.sub.TGT(t) lagging behind the time-variant power envelope 20 by the negative temporal offset −ΔT. As such, it is desirable to reduce the positive temporal offset ΔT and/or the negative temporal offset −ΔT between the time-variant target voltage V.sub.TGT(t) and the time-variant power envelope 20 to help align the time-variant voltage V.sub.CC(t) with the time-variant power envelope 20 at the power amplifier 14.

[0038] In this regard, FIG. 2 is a schematic diagram of an exemplary power management circuit 24 configured according to embodiments of the present disclosure to realign a time-variant target voltage V.sub.TGT(t) with a time-variant power envelope 26 of an analog signal 28. In a non-limiting example, the power management circuit 24 can be provided in a power management apparatus 30 that further includes a power amplifier 32, a transceiver circuit 34, and a signal processing circuit 36.

[0039] The power management circuit 24 is configured to provide a time-variant voltage V.sub.CC(t) to the power amplifier 32 for amplifying the analog signal 28. The analog signal 28 may be generated by the transceiver circuit 34 and provided to the signal processing circuit 36 in IF. The signal processing circuit 36 may upconvert the analog signal 28 from the IF to a carrier frequency and provide the analog signal 28 to the power amplifier 32 for amplification. The analog signal 28 is associated with the time-variant power envelope 26 that rises and falls over time. Thus, to prevent potential amplitude distortion in the analog signal 28 and ensure higher operating efficiency of the power amplifier 32, it is necessary to generate the time-variant voltage V.sub.CC(t) to closely track the time-variant power envelope 26.

[0040] In this regard, the power management circuit 24 is configured to include a voltage processing circuit 38 and a PMIC 40. The voltage processing circuit 38, which can be a field-programmable gate array (FPGA) as an example, is configured to receive the time-variant target voltage V.sub.TGT(t) from the transceiver circuit 34. As previously discussed in FIGS. 1B and 1C, the time-variant target voltage V.sub.TGT(t) may lag behind the time-variant power envelope 26 by a positive temporal offset ΔT or a negative temporal offset −ΔT. As discussed in detail below, the voltage processing circuit 38 is configured to determine the positive temporal offset ΔT and/or the negative temporal offset −ΔT between the time-variant power envelope 26 and the time-variant target voltage V.sub.TGT(t). Accordingly, the voltage processing circuit 38 can generate a time-variant modified target voltage V.sub.TGT-R(t) that is time-adjusted relative to the time-variant power envelope 26 to thereby substantially reduce the determined positive temporal offset ΔT and/or the negative temporal offset −ΔT. Herein, a first signal is said to be time-adjusted relative to a second signal when the first signal is moved forward or backward in time to eliminate the positive temporal offset ΔT or the negative temporal offset −ΔT from the second signal.

[0041] By substantially reducing the determined positive temporal offset ΔT and/or the negative temporal offset −ΔT, it is possible to realign the time-variant modified target voltage V.sub.TGT-R(t) with the time-variant power envelope 26. As a result, it is possible to keep the time-variant voltage V.sub.CC(t) aligned with the time-variant power envelope 26, thus helping to prevent amplitude distortion to the analog signal 28 at the power amplifier 32.

[0042] FIG. 3 is a graphic diagram providing an exemplary illustration of the modified target voltage V.sub.TGT-R(t) that is time-adjusted relative to the time-variant power envelope 26 in FIG. 2 to substantially reduce the positive temporal offset ΔT between the time-variant target voltage V.sub.TGT(t) and the time-variant power envelope 26. Common elements between FIGS. 2 and 3 are shown therein with common element numbers and will not be re-described herein.

[0043] As shown in FIG. 3, the target voltage V.sub.TGT(t) as originally received from the transceiver circuit 34 lags behind the time-variant power envelope 26 by the positive temporal ΔT. In contrast, the modified target voltage V.sub.TGT-R(t) is time-adjusted to substantially reduce the positive temporal offset ΔT to thereby be better aligned with the time-variant power envelope 26. Herein, the modified target voltage V.sub.TGT-R(t) is said to substantially reduce the positive temporal offset ΔT when a temporal gap ΔT between the modified target voltage V.sub.TGT-R(t) and the time-variant power envelope 26 is less than 10% of the positive temporal delay ΔT. As a result of improved alignment with the time-variant power envelope 26, it is possible to reduce or even avoid amplitude distortion at the power amplifier 32.

[0044] With reference back to FIG. 2, in one embodiment, the positive temporal offset ΔT and/or the negative temporal offset −ΔT can be determined by the transceiver circuit 34 and provided to the voltage processing circuit 38. The transceiver circuit 34 may provide the positive temporal offset ΔT and/or the negative temporal offset −ΔT periodically (e.g., per symbol, mini slot, or slot).

[0045] In another embodiment, the power management circuit 24 can be configured to further include a delay detector circuit 42. The delay detector circuit 42 can be configured to dynamically detect the positive temporal offset ΔT or the negative temporal offset −ΔT between the time-variant power envelope 26 and the time-variant target voltage V.sub.TGT(t) and provide the detected positive temporal offset ΔT or the detected negative temporal offset −ΔT to the voltage processing circuit 38. The delay detector circuit 42 may detect the positive temporal offset ΔT and/or the negative temporal offset −ΔT periodically (e.g., per symbol, mini slot, or slot).

[0046] The voltage processing circuit 38 can be configured to generate the modified target voltage V.sub.TGT-R(t) from the time-variant target voltage V.sub.TGT(t) and as a function of a modulated modifier K.sub.MOD(t). In a non-limiting example, the modified target voltage V.sub.TGT-R(t) can be described by the equation (Eq. 1) below.

V.sub.TGT-R(t)=V.sub.TGT(t)+K.sub.MOD(t)*(V.sub.TGTMAX−V.sub.TGT(t))   (Eq. 1)

[0047] In the equation (Eq. 1) above, K.sub.MOD(t) represents the modulated modifier and V.sub.TGTMAX represents an estimated maximum value of the time-variant target voltage V.sub.TGT(t). The voltage processing circuit 38 can be configured to generate the modulated modifier K.sub.MOD(t) as a function of a linear term K.sub.MODLINEAR(t) and a nonlinear term NL.sub.GAIN(dV.sub.TGT(t)/dt). In a non-limiting example, the modulated modifier K.sub.MOD(t) can be described by the equation (Eq. 2) below.

K.sub.MOD(t)=K.sub.MODLINEAR(t)*NL.sub.GAIN(dV.sub.TGT(t)/dt)   (Eq. 2)

[0048] The voltage processing circuit 38 can be configured to determine the linear term K.sub.MODLINEAR(t) as a function of a delay budget dT and a voltage offset K.sub.OFFSET(dT) corresponding to the delay budget dT. In this regard, to realign the time-variant target voltage V.sub.TGT(t) with the time-variant power envelope 26, the delay budget dT may be equal to the positive temporal offset ΔT (dT=ΔT) if the time-variant target voltage V.sub.TGT(t) lags behind the time-variant power envelope 26, or be equal to the negative temporal offset −ΔT (dT=−ΔT) if the time-variant target voltage V.sub.TGT(t) leads the time-variant power envelope 26. In this regard, the delay budget dT can be positive or negative. In a non-limiting example, the linear term K.sub.MODLINEAR(t) can be described by the equation (Eq. 3) below.

K.sub.MODLINEAR(t)=K.sub.OFFSET(dT)+[dV.sub.TGT(t)/dt]*dT/[V.sub.TGTMAX−V.sub.TGT(t)]  (Eq. 3)

[0049] In one embodiment, the delay budget dT and the voltage offset K.sub.OFFSET(dT) corresponding to the delay budget dT can be predetermined and stored in the voltage processing circuit 38. As shown in FIG. 4, the voltage offset K.sub.OFFSET(dT) may be so determined to provide a voltage headroom ΔV between peaks of the modified target voltage V.sub.TGT-R(t) and peaks of the time-variant power envelope 26 of the analog signal 28. FIG. 4 is a graphic diagram providing an exemplary illustration of the voltage headroom ΔV as created by the voltage offset K.sub.OFFSET(dT) in the equation (Eq. 3).

[0050] Notably, the time-variant power envelope 26 can have a number of amplitude peaks 44 and the time-variant modified target voltage V.sub.TGT-R(t) can have a number of voltage peaks 46 each corresponding to a respective one of the amplitude peaks 44. In this regard, the voltage offset K.sub.OFFSET(dT) is determined to cause each of the voltage peaks 46 to be higher than the respective one of the amplitude peaks 44 by the voltage headroom ΔV. By creating the voltage headroom ΔV between the time-variant modified target voltage V.sub.TGT-R(t) and the time-variant power envelope 26, it is possible to ensure that the PMIC 40 can always generate the time-variant voltage V.sub.CC(t) sufficient enough to avoid amplitude distortion in the analog signal 28.

[0051] With reference back to FIG. 2, the nonlinear term NL.sub.GAIN(dV.sub.TGT(t)/dt) is introduced in the equation (Eq. 2) to ensure that the voltage headroom ΔV created by the voltage offset K.sub.OFFSET(dT) in the linear term K.sub.MODLINEAR(t) is not excessively high to cause linearity degradation in the power amplifier 32. In a non-limiting example, the nonlinear term NL.sub.GAIN(dV.sub.TGT(t)/dt) is a function that is equal to one (1) for most dV.sub.TGT(t)/dt or less than 1 when dV.sub.TGT(t)/dt approaches a maximum or a minimum. As a result, the voltage headroom ΔV can be maintained when the nonlinear term NL.sub.GAIN(dV.sub.TGT(t)/dt) is equal to 1 or reduced when the nonlinear term NL.sub.GAIN(dV.sub.TGT(t)/dt) is less than 1.

[0052] Simulations have shown that the time-variant modified target voltage V.sub.TGT-R(t) generated based on the equations (Eq. 1 to 3) can have a very similar waveform as the time-variant target voltage V.sub.TGT(t) for different delay budgets dT, despite being time-adjusted. This means that the time-variant modified target voltage V.sub.TGT-R(t) can reduce the positive temporal offset ΔT and the negative temporal offset −ΔT without much deviation and distortion from the time-variant target voltage V.sub.TGT(t). In this regard, the embodiments disclosed in the present disclosure are advantageous over the use of a traditional low-pass filter to create a group delay in that the low-pass filter may generate group delay ripple within modulation bandwidth and may be difficult to implement for reducing a larger group delay.

[0053] Those skilled in the art will recognize improvements and modifications to the embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.