FREQUENCY DOUBLER USING RECIRCULATING DELAY CIRCUIT AND METHOD THEREOF

Abstract

A method of frequency doubling includes receiving a first clock that has a fifty percent duty cycle and is a two-phase clock having a first phase and a second phase; outputting a second clock using a multiplexer by selecting one of the first phase and the second phase of the first clock in accordance with a third clock; delaying the second clock into a fourth clock using a recirculating delay circuit; and using a divide-by-two circuit to output the third clock in accordance with the fourth clock.

Claims

1. A frequency doubler comprising: a multiplexer configured to receive a first clock and output a second clock in accordance with a third clock, wherein the first clock has a fifty percent duty cycle and is a two-phase clock comprising a first phase and a second phase; a recirculating delay circuit configured to receive the second clock and output a fourth clock and a fifth clock; and a divide-by-two circuit configured to receive the fourth clock and output the third clock, wherein the recirculating delay circuit comprises a logic gate and a delay chain comprising a plurality of clock buffers including an intermediate clock buffer and a last clock buffer, said logic gate being configured to receive the second clock and the fifth clock and output a sixth clock, said plurality of clock buffers being cascaded and configured to receive the sixth clock and output the fourth clock from the intermediate clock buffer and output the fifth clock from the last clock buffer.

2. The frequency doubler of claim 1, further including a control signal configured to control a delay of the delay chain.

3. The frequency doubler of claim 2 further comprising: a duty cycle detector configured to receive the second clock and output a duty cycle error signal, a controller configured to receive the duty cycle error signal, and a power supply circuit configured to establish a voltage level of a power supply node of the delay chain.

4. The frequency doubler of claim 3, wherein the controller is an integrator.

5. The frequency doubler of claim 4, wherein the duty cycle error is a logical signal that indicates whether a duty cycle of the second clock is higher than a target duty cycle value.

6. The frequency doubler of claim 5, wherein the control signal is a digital signal and the power supply circuit comprises a digital-to-analog converter and a source follower, the digital-to-analog converter being configured to receive the digital signal and output a control voltage, the source follower being configured to receive the control voltage and establish the voltage level of the power supply node of the delay chain.

7. The frequency doubler of claim 4, wherein the duty cycle error is a current signal proportional to a difference between a duty cycle value of the second clock and a target duty cycle value.

8. The frequency doubler of claim 7, wherein the controller comprises a capacitor configured to receive the duty cycle error signal and establish a control voltage.

9. The frequency doubler of claim 8, wherein the power supply circuit comprises a source follower configured to receive the control voltage and establish a voltage level of a power supply node of the delay chain.

10. The frequency doubler of claim 1, wherein the divide-by-two circuit comprises a data flip-flop configured in a negative feedback topology.

11. A method of frequency doubling comprising: receiving a first clock that has a fifty percent duty cycle and is a two-phase clock comprising a first phase and a second phase; outputting a second clock using a multiplexer by selecting one of the first phase and the second phase of the first clock in accordance with a third clock; delaying the second clock into a fourth clock using a recirculating delay circuit; and using a divide-by-two circuit to output the third clock in accordance with the fourth clock.

12. The method of frequency doubling of claim 11, wherein the recirculating delay circuit comprises a logic gate and a delay chain comprising a plurality of clock buffers including an intermediate clock buffer and a last clock buffer clock buffer, said logic gate being configured to receive the second clock and a fifth clock and output a sixth clock and said plurality of clock buffers being cascaded and configured to receive the sixth clock and output the fourth clock from the intermediate clock buffer and output the fifth clock from the last clock buffer

13. The method of frequency doubling of claim 12, further comprising controlling a delay of the delay chain by a power supply circuit controlled by a control signal.

14. The method of frequency doubling of claim 13 further comprising: outputting a duty cycle error signal in accordance with a difference between a duty cycle value of the second clock and a target duty cycle value, establishing the control signal by integrating the duty cycle error signal.

15. The method of frequency doubling of claim 14, wherein the duty cycle error is a logical signal that indicates whether a duty cycle of the second clock is higher than a target duty cycle value.

16. The method of frequency doubling of claim 15, wherein the control signal is a digital signal and the power supply circuit comprises a digital-to-analog converter and a source follower, the digital-to-analog converter being configured to receive the digital signal and output a control voltage, the source follower being configured to receive the control voltage and establish a voltage level of a power supply node of the delay chain.

17. The method of frequency doubling of claim 14, wherein the duty cycle error is a current signal proportional to a difference between a duty cycle value of the second clock and a target duty cycle value.

18. The method of frequency doubling of claim 17, wherein integrating the duty cycle error signal comprises using a capacitor to integrate the control signal into a control voltage.

19. The method of frequency doubling of claim 18, wherein the power supply circuit comprises a source follower configured to receive the control voltage and establish a voltage level of a power supply node of the delay chain.

20. The method of frequency doubling of claim 11, wherein the divide-by-two circuit comprises a data flip-flop configured in a negative feedback topology.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0007] FIG. 1A shows a schematic diagram of frequency doubler in accordance with an embodiment of the present disclosure.

[0008] FIG. 1B shows an exemplary timing diagram of the frequency doubler of FIG. 1A.

[0009] FIG. 2A shows a schematic diagram of a duty cycle detector.

[0010] FIG. 2B shows a schematic diagram of an alternative duty cycle detector.

[0011] FIG. 3 shows a schematic diagram of a power supply circuit.

[0012] FIG. 4 shows a schematic diagram of a controller and a power supply circuit in accordance with an analog control scheme.

[0013] FIG. 5 shows a flow diagram of a method of frequency doubling in accordance with an embodiment of the present disclosure.

DETAILED DESCRIPTION OF THIS DISCLOSURE

[0014] The present disclosure is directed to frequency doubler. While the specification describes several example embodiments of the disclosure considered favorable modes of practicing the invention, it should be understood that the invention can be implemented in many ways and is not limited to the particular examples described below or to the particular manner in which any features of such examples are implemented. In other instances, well-known details are not shown or described to avoid obscuring aspects of the disclosure.

[0015] Persons of ordinary skill in the art understand terms and basic concepts related to microelectronics that are used in this disclosure, such as “voltage,” “current,” “signal,” “power supply,” “ground,” “CMOS (complementary metal oxide semiconductor),” “NMOS (n-channel metal oxide semiconductor),” “PMOS (p-channel metal oxide semiconductor),” “resistor,” “capacitor,” “comparator,” “transconductance amplifier,” “inverter,” “logical signal,” “multiplexer,” “switch,” “data flip-flop,” “logic gate,” “NAND gate,” “low-pass filter,” “digital,” “analog,” and “duty cycle.” Terms like these are used in a context of microelectronics, and the associated concepts are apparent to those of ordinary skills in the art and thus will not be explained in detail here.

[0016] Those of ordinary skill in the art can recognize a resistor symbol and can recognize a MOS (metal-oxide semiconductor) transistor symbol, for both PMOS transistor and NMOS transistor, and identify the “source,” the “gate,” and the “drain” terminals thereof. Those of ordinary skill in the art can read schematics of a circuit comprising resistors, NMOS transistors, and PMOS transistors, and do not need a verbose description about how one transistor or resistor connects with another in the schematics.

[0017] This present disclosure is disclosed in terms of an engineering sense. For instance, regarding two variables X and Y, when it is said that “X is equal to Y,” it means that “X is approximately equal to Y,” i.e. “a difference between X and Y is smaller than a specified engineering tolerance.” When it is said that “X is zero,” it means that “X is approximately zero,” i.e. “X is smaller than a specified engineering tolerance.” When it is said that “X is substantially smaller than Y,” it means that “X is negligible with respect to Y,” i.e. “a ratio between X and Y is smaller than an engineering tolerance and therefore X is negligible when compared to Y.”

[0018] Throughout this disclosure, “V.sub.DD” denotes a power supply node. Note that a power supply node is a node at which a voltage level is substantially stationary. In this disclosure, depending on a context that is apparent to those of ordinary skill in the art, sometimes V.sub.DD refers to the voltage level at the power supply node V.sub.DD. For instance, it is apparent that when it is said that “V.sub.DD is 1.05V” it means that the voltage level at the power supply node V.sub.DD is 1.05V. A ground node is a node at which a voltage level is substantially zero.

[0019] In this present disclosure, a signal is either a voltage or a current of a variable level that can vary with time, or a number with a value that can vary with time. When a signal is a voltage, it is called a voltage signal and a level of the signal at a moment represents a state of the signal at that moment. When a signal is a number, it is called a numerical signal, also known as a digital signal, and a value of the signal at a moment represents a state of the signal at that moment.

[0020] A logical signal is a voltage signal of two states: a low state and a high state. The low state is also known as a “0” state, while the high stage is also known as a “1” state. Regarding a logical signal Q, when we say, “Q is high” or “Q is low,” what we mean is “Q is in the high state” or “Q is in the low state.” Likewise, when it is said that “Q is 1” or “Q is 0,” what is meant is that “Q is in the 1 state” or “Q is in the 0 state.”

[0021] When a logical signal toggles from low to high, it undergoes a low-to-high transition and exhibits a rising edge. When a logical signal toggles from high to low, it undergoes a high-to-low transition and exhibits a falling edge.

[0022] When a MOS transistor is used to embody a switch, it is controlled by a control signal that is a logical signal applied at a gate of the MOS transistor. A switch embodied by a NMOS transistor is in an “on” state when the control signal is high, and in an “off” state when the control signal is low.

[0023] A first logical signal is said to be a logical inversion of a second logical signal, if the first logical signal and the second logical signal are always in opposite states. That is, when the first logical signal is low, the second logical signal is high; when the first logical signal is high, the second logical signal is low. When a first logical signal is said to be a logical inversion of a second logical signal, the first logical signal and the second logical signal are said to be complementary to each other.

[0024] A two-phase clock is a clock that has two phases including a first phase and a second phase, wherein the second phase is a logical inversion of the first phase and thus complementary to the first phase; when both the first phase and the second phase have a fifty percent duty cycle, the two-phase clock is said to have a fifty percent duty cycle.

[0025] A clock buffer is a circuit that receives a first clock as an input and outputs a second clock as output, wherein the second clock is substantially the same as the first clock except for a timing delay that is substantially smaller than a period of the first clock. By way of example but not limitation, the timing delay is one hundredth of the period of the first clock.

[0026] A NAND gate is a logic gate that receives a first logical signal and a second logical signal and output a third logical signal that is low if both the first logical signal and the second logical signal are high, and low otherwise. Those of ordinary skill in the art can recognize a circuit symbol of a NAND gate and understand its function without a need for explanation.

[0027] A digital word is a numerical signal of an integer value that can be embodied by a collection of a plurality of logical signals in accordance with a certain encoding scheme.

[0028] A transconductance amplifier is a circuit that receives a voltage signal and output a current signal that is proportional to the voltage signal.

[0029] A circuit is a collection of transistors, resistors, and/or other electronic devices inter-connected in a certain manner to embody or carry out a certain function.

[0030] A schematic diagram of a frequency doubler 100 in accordance with an embodiment of the present disclosure is shown in FIG. 1A. The frequency doubler 100 comprises: a multiplexer 110 configured to receive a first clock S.sub.1, which has a 50% duty cycle and is a two-phase clock comprising a first phase S.sub.1[0] and a second phase S.sub.1[1], and output a second clock S.sub.2 in accordance with a third clock S.sub.3; a recirculating delay circuit (RDC) 120 configured to receive the second clock S.sub.2 and output a fourth clock S.sub.4 and a fifth clock S.sub.5; and a divide-by-two circuit 130 configured to receive the fourth clock S.sub.4 and output the third clock S.sub.3. The RDC 120 comprises a NAND gate 121 configured to receive the second clock S.sub.2 and the fifth clock S.sub.5 and output a sixth clock S.sub.6, and a delay chain 122 comprising a plurality of clock buffers 122A, 122B, . . . , 122C, and 122D configured in a cascade topology to receive the sixth clock S.sub.6 and output the fourth clock S.sub.4 and the fifth clock S.sub.5, wherein clock buffer 122D is a last clock buffer configured to output the fifth clock S.sub.5 and clock buffer 122C is an intermediate clock buffer configured to output the fourth clock S.sub.4.

[0031] For brevity, hereafter: the first clock S.sub.1 is simply referred to as S.sub.1; the first phase S.sub.1[0] of the first clock S.sub.1 is simply referred to as S.sub.1[0]; the second phase S.sub.1[1] of the first clock S.sub.1 is simply referred to as S.sub.1[1]; the second clock S.sub.2 is simply referred to as S.sub.2; the third clock S.sub.3 is simply referred to as S.sub.3; the fourth clock S.sub.4 is simply referred to as S.sub.4; the fifth clock S.sub.5 is simply referred to as S.sub.5; and the sixth clock S.sub.6 is simply referred to as S.sub.6.

[0032] In an embodiment, each of clock buffers 122A, 122B, . . . , 122C, and 122D comprises two inverters cascaded to form a non-inverting buffer. As shown in call-out box COB122D, clock buffer 122D comprises two inverters INV1 and INV2 that are configured in a cascade topology to receive the fourth clock S.sub.4 and output the fifth clock S.sub.5 that is logically the same as S.sub.4 but has a delay in timing when a toggling of state of S.sub.4 occurs, i.e., a rising (falling) edge of S.sub.4 will lead to a rising (falling) edge of S.sub.5 with a delay in timing. Inverter INV1 comprises NMOS transistor M1 and PMOS transistor M2, while inverter INV2 comprises NMOS transistor M3 and PMOS transistor M4. Here, “V.sub.SP” denotes a power supply node for the delay chain 122. The delay in timing of clock buffer 122D depends on a voltage level at the power supply node “V.sub.SP”: a higher (lower) voltage level leads to a shorter (longer) delay because MOS transistors react faster when the supply voltage are higher; this is clear to those of ordinary skill in the art and thus no further explanation is needed.

[0033] In an embodiment, clock buffers 122A, 122B, . . . , and 122C are embodied by the same circuit as that shown in call-out box COB122D.

[0034] Multiplexer 110 outputs S.sub.2 by selecting either S.sub.1[0] or S.sub.1[1] to be S.sub.2 in accordance with S.sub.3, and its function can be described as follows:

[00001]$\begin{array}{cc}{S}_2=\{\begin{array}{cc}{S}_1\left[0\right]& \mathrm{if}{S}_3\mathrm{is}0\\ S_1\left[1\right]& \mathrm{if}{S}_3\mathrm{is}1\end{array}& \left(1\right)\end{array}$

[0035] A multiplexer, such as one that can embody multiplexer 110 of FIG. 1A in accordance with equation (1), is well known in the prior art and thus not described in detail here.

[0036] RDC 120 receives S.sub.2 and outputs S.sub.4 and S.sub.5. When S.sub.2 is low, S.sub.6 will be high regardless of S.sub.5, and RDC 120 will stay in a halted state, wherein outputs of clock buffers 122A, 122B, and so on, including S.sub.4 and S.sub.5, are all high. Upon a rising edge of S.sub.2, RDC 120 enters a recirculating state and stays in the recirculating state as long as S.sub.2 stays high, wherein NAND gate 121 effectively behaves as an inverter (since S.sub.6 will be a logical inversion of S.sub.5) and NAND gate 121 and the delay chain 122 form a negative feedback loop to allow a recirculation of clock, wherein a falling edge of S.sub.6 will propagate through the delay chain 121 and lead to a falling edge of S.sub.4 followed by a falling edge of S.sub.5, and then lead to a rising edge of S.sub.6, while a rising edge of S.sub.6 will propagate through the delay chain 121 and lead to a rising edge of S.sub.4 followed with a rising edge of S.sub.5, and then lead to a falling edge of S.sub.6 if S.sub.2 still stays high. This way, a delay function is fulfilled such that a rising edge of S.sub.2 can trigger a rising edge of S.sub.4 with a timing delay determined by a propagation delay of delay chain 122, which is an aggregate of delay in timing of all clock buffers 122A, 122B, . . . , 122C, and 122D.

[0037] Divide-by-two circuit 130 comprises a data flip-flop 131 triggered by S.sub.4 and configured in a negative feedback topology to embody a divide-by-two function such that a rising edge of S.sub.4 triggers S.sub.3 to toggle state, resulting in either a rising edge or a falling edge of S.sub.3; if one assigns a sequential number for each rising edge of S.sub.4, then an even-numbered rising edge of S.sub.4 triggers a toggling of S.sub.3 from low to high, i.e. a rising edge of S.sub.3, while an odd-numbered rising edge of S.sub.4 triggers a toggling of S.sub.3 from high to low, i.e. a falling edge of S.sub.3; every two rising edges of S.sub.4 trigger only one rising edge of S.sub.3, therefore S.sub.3 is said to be a divide-by-two clock of S.sub.4. Data flip-flop 131 has an input pin labeled by “D,” an output pin labeled by “Q,” a complementary output pin labeled by “QB,” and a trigger pin illustrated by a wedge and is obvious to those of ordinary skill in the art and no need for further explanation.

[0038] S.sub.1 is a two-phase clock that has a 50% duty cycle. Let a period of S.sub.1 be T. A purpose of the frequency doubler 100 is to make S.sub.2 a clock of a double frequency. That is, a period of S.sub.2 is equal to T/2, since a frequency doubling means a period halving. S.sub.4 is a delay of S.sub.2 and therefore also has the same period T/2. S.sub.3 is a divide-by-two clock of S.sub.4, and therefore a period of S.sub.3 is twice of the period of S.sub.4, and thus is equal to T.

[0039] An exemplary timing diagram of frequency doubler 100 is shown in FIG. 1B. Here, S.sub.1[0], S.sub.1[1], S.sub.2, S.sub.3, S.sub.4, S.sub.5, and S.sub.6 are all clocks that are logical signals that are either high (at V.sub.DD, V.sub.SP, or whatever voltage level of the supply voltage) or low (at 0V). As shown, S.sub.1[0] and S.sub.1[1] are complementary. A period of S.sub.1[0] is T, as demonstrated by a time difference of T between a rising edge 190a (at time t.sub.a), and a subsequent rising edge 190g (at time t.sub.9). A duty cycle of S.sub.1[0] is 50%, as demonstrated by a time difference of T/2 between the rising edge 190a and a subsequent falling edge 190d (at time t.sub.d), showing that S.sub.1[0] stays high for 50% of the time of a clock cycle. It is obvious that a period of S.sub.1[1] is T and a duty cycle of S.sub.1[1] is 50%. Initially, S.sub.1[0] is low, S.sub.1[1] is high, S.sub.3 is low, multiplexer 110 selects S.sub.1[0] as S.sub.2 and thus S.sub.2 is low, consequently RDC 120 is in a halted state, wherein S.sub.6, S.sub.4, and S.sub.5 are all high. At time t.sub.a, rising edge 190a of S.sub.1[0] leads to rising edge 192a of S.sub.2, causing RDC 120 to enter in a recirculation state by launching a falling edge 196a of S.sub.6 (due to NAND gate 121), which propagates through delay chain 122 and results in falling edge 195b of S.sub.5 at time t.sub.b and consequently rising edge 196b of S.sub.6 (due to NAND gate 121), which propagates through delay chain 122 and results in rising edge 194c of 5.sub.4 at time t.sub.c, which triggers divide-by-two circuit 130 to toggle S.sub.3 to high, causing the multiplexer 110 to select S.sub.1[1] as S.sub.2, resulting in a falling edge 192c of S.sub.2, and consequently causing RDC 120 to enter in a halted state, wherein S.sub.6, S.sub.4, and S.sub.5 are all high. At time t.sub.d, rising edge 191d of S.sub.1[1] leads to rising edge 192d of S.sub.2, causing RDC 120 to enter in a recirculation state by launching a falling edge 196d of S.sub.6 (due to NAND gate 121), which propagates through delay chain 122 and results in falling edge 195e of S.sub.5 at time t.sub.e and consequently rising edge 196e of S.sub.6 (due to NAND gate 121), which propagates through delay chain 122 and results in rising edge 194f of 5.sub.4 at time t.sub.f, which triggers divide-by-two circuit 130 to toggle S.sub.3 to low, causing the multiplexer 110 to select S.sub.1[0] as S.sub.2, resulting in a falling edge 192f of S.sub.2, and consequently causing RDC 120 to enter in a halted state, wherein S.sub.6, S.sub.4, and S.sub.5 are all high. This completes a cycle of operation, awaiting a next cycle that starts with rising edge 190g of S.sub.1[0] at time t.sub.9. As a result, S.sub.2 is a clock of a double frequency with a duty cycle determined by a propagation delay of RDC 120 that depends on the voltage at the power supply node V.sub.SP.

[0040] An advantage of using a recirculating delay circuit to introduce a timing delay is efficiency due to circuit reuse. By recirculating a clock, a delay can be approximately doubled, and therefore a totally number of clock buffers can be reduced approximately by half.

[0041] In an embodiment, a voltage level at the power supply node V.sub.SP is fixed; this embodiment is useful in an application that does not have a strict requirement on a duty cycle of S.sub.2.

[0042] In a further embodiment that includes a duty cycle corrector and is useful in an application that requires a specific and precise duty cycle of S.sub.2, the frequency doubler 100 further comprises a duty cycle detector 140 configured to receive the second clock S.sub.2 and output a duty cycle error signal E.sub.dc; a controller 150 configured to receive the duty cycle error signal E.sub.dc and output a control signal S.sub.ctl; and a power supply circuit 160 configured to establish a voltage level at the power supply node V.sub.SP in accordance with the control signal S.sub.ctl. For brevity, hereafter the duty cycle error signal E.sub.dc is simply referred to as E.sub.dc and the control signal S.sub.ctl is simply referred to as S.sub.ctl. In an embodiment, a higher (lower) value of S.sub.ctl leads to a higher (lower) voltage level at the power supply node V.sub.SP and thus causes a shorter (longer) delay of RDC 120. E.sub.dc represents a result of a comparison between D.sub.out with D.sub.tgt, where D.sub.out is a duty cycle value of S.sub.2 and D.sub.tgt is a target duty cycle value. If E.sub.dc indicates that D.sub.out is greater (smaller) than D.sub.tgt and needs to be decreased (increased), the controller 150 will increment (decrement) a value of S.sub.ctl and consequently shorten (lengthen) a delay of RDC 120 and lead to a decrement (increment) of duty cycle of S.sub.2. This way, a duty cycle of S.sub.2 is adjusted in a closed loop manner to make the duty cycle of S.sub.2 equal to the target duty cycle.

[0043] The further embodiment can be based on either a digital control scheme or an analog control scheme. A digital control scheme will be presented first, followed by an analog control scheme.

[0044] In an embodiment in accordance with a digital control scheme, E.sub.dc is a logical signal, and duty cycle detector 140 outputs E.sub.dc in accordance with the following equation:

[00002]$\begin{array}{cc}{E}_{\mathrm{dc}}=\{\begin{array}{cc}1& \mathrm{if}{D}_{\mathrm{out}}>D_{\mathrm{tgt}}\\ 0& \mathrm{otherwise}\end{array}& \left(2\right)\end{array}$

[0045] When E.sub.dc is 1, it indicates the duty cycle of S.sub.2 is larger than the target duty cycle value D.sub.tgt and thus needs to be decreased. When E.sub.dc is 0, it indicates the duty cycle of S.sub.2 is smaller than the target duty cycle value D.sub.tgt and thus needs to be increased.

[0046] In an embodiment in accordance with a digital control scheme, S.sub.ctl is an integer, and a greater value of S.sub.ctl leads to a smaller propagation delay of RDC 120. In an embodiment, the controller 150 periodically updates a value of S.sub.ctl in accordance with:

[00003]$\begin{array}{cc}{S}_{\mathrm{ctl}}^{\left(\mathrm{new}\right)}=\{\begin{array}{cc}{S}_{\mathrm{ctl}}^{\left(\mathrm{old}\right)}+1& \mathrm{if}{E}_{\mathrm{dc}}=1\\ S_{\mathrm{ctl}}^{\left(\mathrm{old}\right)}-1& \mathrm{if}{E}_{\mathrm{dc}}=0\end{array}& \left(3\right)\end{array}$

[0047] Here, S.sub.ctl.sup.(old) denotes an old value of S.sub.ctl before an update, while S.sub.ctl.sup.(new) denotes a new value of S.sub.ctl after the update. When the duty cycle of S.sub.2 is too large (i.e. D.sub.out>D.sub.tgt), E.sub.dc is 1, the controller 150 increments the value of S.sub.ctl, leading to a smaller propagation delay of RDC 120 and thus decreasing the duty cycle of S.sub.2; when the duty cycle of S.sub.2 is too small (i.e. D.sub.out<D.sub.tgt), E.sub.dc is 0, the controller 150 decrements the value of S.sub.ctl, leading to a larger propagation delay of RDC 120 and thus increasing the duty cycle of S.sub.2.

[0048] Note that equation (3) describes an integrator function, wherein S.sub.ctl is an integration of E.sub.dc, provided a level represented by the second state of E.sub.dc (E.sub.dc=0) is an inversion of a level represented by the first state of E.sub.dc (E.sub.dc=1).

[0049] A schematic diagram of a duty cycle detection circuit 200A that can be used to embody duty cycle detector 140 in accordance with a digital control scheme is shown in FIG. 2A. Duty cycle detection circuit 200A comprises a low-pass filter 210 comprising resistor 211 and capacitor 212, a resistive voltage divider 220 comprising resistor 221 and resistor 222, and a comparator 230. Low-pass filter 210 receives S.sub.2 and output an average voltage V.sub.a that is approximately D.sub.outV.sub.DD, wherein V.sub.DD is a power supply voltage for S.sub.2 and thus a voltage level of S.sub.2 when S.sub.2 is high. For instance, if the duty cycle of S.sub.2 is 40%, V.sub.a will be approximately 0.4.Math.V.sub.DD, since S.sub.2 stays high at V.sub.DD for 40% of the time. Resistive voltage divider 220 outputs a target voltage V.sub.tgt that presents D.sub.tgt, the target duty cycle value for S.sub.2. Let resistances of resistor 221 and resistor 222 be R.sub.221 and R.sub.222, respectively. R.sub.221 is chosen in accordance with

[00004]$\begin{array}{cc}{R}_{221}=R_{222}.Math.\left(\frac{1}{D_{\mathrm{tgt}}}-1\right)& \left(4\right)\end{array}$

[0050] The target voltage V.sub.tgt is established in accordance with a voltage division of V.sub.DD across resistors 221 and 222, i.e.

[00005]$\begin{array}{cc}{V}_{\mathrm{tgt}}=\frac{R_{222}}{R_{221}+R_{222}}.Math.V_{\mathrm{DD}}=D_{\mathrm{tgt}}{V}_{\mathrm{DD}}& \left(5\right)\end{array}$

[0051] Here, equation (4) is applied. Comparator 230 compares V.sub.a with V.sub.tgt and outputs E.sub.dc, indicating whether V.sub.a is higher than V.sub.tgt. When V.sub.a is higher (lower) than V.sub.tgt, E.sub.dc is 1 (0), and it indicates D.sub.outV.sub.DD is larger (smaller) than D.sub.tgtV.sub.DD, thus D.sub.out is larger (smaller) than D.sub.tgt. When D.sub.out is larger (smaller) than D.sub.tgt, E.sub.dc is 1 (0), controller 150 increments (decrements) the value of S.sub.ctl, resulting in a decrement (increment) of the propagation delay of RDC 120 and the duty cycle of S.sub.2. The duty cycle of S.sub.2 is thus adjusted in a closed loop manner towards being equal to D.sub.tgt.

[0052] In a special case where the target duty cycle value D.sub.tgt is 50%, an alternative duty cycle detector 200B shown in FIG. 2B can be used to embody duty cycle detector 140 of FIG. 1A in accordance with a digital control scheme. Duty cycle detector 200B comprises: a first low-pass filter 240 comprising resistor 241 and capacitor 242, an inverter 270, a second low-pass filter 250 comprising resistor 251 and capacitor 252, and a comparator 260. Inverter 270 receives S.sub.2 and outputs a complementary signal S′.sub.2, which is a logical inversion of S.sub.2. Since the duty cycle of S.sub.2 is D.sub.out, the duty cycle of S′.sub.2 is 1−D.sub.out, because S′.sub.2 is complementary to S.sub.2. The first low-pass filter 240 receives S.sub.2 and output a first average voltage V.sub.p that is approximately D.sub.outV.sub.DD. For instance, if the duty cycle of S.sub.2 is 40%, V.sub.p will be approximately 0.4.Math.V.sub.DD, since S.sub.2 stays high at V.sub.DD for 40% of the time. The second low-pass filter 250 receives S′.sub.2 and output a second average voltage V.sub.n that is approximately (1−D.sub.out)V.sub.DD. For instance, if the duty cycle of S.sub.2 is 40%, V.sub.n will be approximately 0.6.Math.V.sub.DD, since S′.sub.2 stays high at V.sub.DD for 60% of the time due to being complementary to S.sub.2. Comparator 260 compares V.sub.p with V.sub.n and outputs E.sub.dc, indicating whether V.sub.p is higher than V.sub.n. When V.sub.p is higher/lower than V.sub.n, E.sub.dc is 1 (0), it indicates that D.sub.outV.sub.DD is larger/smaller than (1−D.sub.out)V.sub.DD, thus D.sub.out is larger/smaller than (1−D.sub.out), and that indicates that D.sub.out is larger/smaller than 50%. Therefore, duty cycle detector 200B can perform a duty cycle detection for S.sub.2 if the target duty cycle value D.sub.tgt is 50%.

[0053] A comparator, such as comparator 230 in FIG. 2A or comparator 260 in FIG. 2B, is a circuit that receives two voltages and outputs a logical signal indicates which one of the two voltages is higher, and can be implemented using whatever circuit known in the prior art at a discretion of a circuit designer. An inverter such as inverter 270 performs a logical inversion and is well known in the prior art and thus not described in detail here.

[0054] A schematic diagram of a power supply circuit 300 that can be used to embody power supply circuit 160 in accordance with a digital control scheme is shown in FIG. 3. Power supply circuit 300 comprises a digital-to-analog converter (DAC) 310 configured to convert S.sub.ctl into a control voltage V.sub.ctl, and a NMOS transistor 320 configured as a source follower to establish a voltage level at the power supply node V.sub.SP in accordance with the control voltage V.sub.ctl. Here, “V.sub.DDH” denotes a power supply node of a voltage level that is at least 200 mV higher than a voltage level at the power supply node V.sub.SP. Both DAC and source follower are well known in the prior art and there is no need for further explanation.

[0055] In an analog control scheme, E.sub.ci is a current signal proportional to D.sub.out−D.sub.tgt, and S.sub.ctl is an analog voltage signal that does not have discrete states. The duty cycle detection circuit 200A of FIG. 2A can be modified to be used in an analog control scheme by replacing the comparator 230 with a transconductance amplifier, so that E.sub.dc will be a current proportional to V.sub.a−V.sub.tgt and consequently proportional to D.sub.out−D.sub.tgt, instead of being either logical signal of either high or low. Likewise, the duty cycle detection circuit 200B of FIG. 2B can be modified to be used in an analog control scheme by replacing the comparator 260 with a transconductance amplifier. In an analog control scheme, the controller 150 and the power supply circuit 160 can be consolidated into a control circuit 400 depicted in FIG. 4. Control circuit 400 comprises a capacitor 410 configured as a load for receiving E.sub.dc and establish S.sub.ctl, and a NMOS transistor 420 configured as a source follower to establish a voltage level at the power supply node V.sub.SP in accordance with S.sub.ctl. Capacitor 410 embodies an integration function that is analogous to equation (3).

[0056] As illustrated by a flow diagram shown in FIG. 5, a method of frequency doubling comprises: (step 510) receiving a first clock that has a fifty percent duty cycle and is a two-phase clock comprising a first phase and a second phase; (step 520) outputting a second clock using a multiplexer by selecting one of the first phase and the second phase of the first clock in accordance with a third clock; (step 530) delaying the second clock into a fourth clock using a recirculating delay circuit; and (step 540) using a divide-by-two circuit to output the third clock in accordance with the fourth clock.

[0057] Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the disclosure. Accordingly, the above disclosure should not be construed as limited only by the metes and bounds of the appended claims.