Abstract
The disclosure relates to an inverter for supplying a power provided as a DC voltage at a DC input to an AC mains connectable to an AC output. In this case, the inverter includes a switching network with a plurality of semiconductor switches and a digital control unit for producing a digital switching pattern for digitally operated semiconductor switches of the switching network that are able to be used to produce a first output voltage (U.sub.out,dig). The inverter additionally includes a linear control unit for producing signals for actuating at least one semiconductor switch of the switching network in a linear mode, wherein the linear control unit is set up to produce a voltage drop (U.sub.out,lin) across and/or a current (I.sub.out,lin) through the at least one linearly operated semiconductor switch to a target value that is dependent on an instantaneous difference between the first output voltage (U.sub.out,dig) and a voltage (U.sub.AC) of the AC mains. The disclosure additionally relates to a control method for such an inverter and a photovoltaic (PV) installation having such an inverter.
Claims
1. An inverter for supplying a power provided as a DC voltage at a DC input to an AC mains connectable to an AC output, comprising: a switching network comprising a plurality of semiconductor switches comprising a first set of one or more semiconductor switches to be operated digitally and a second set of one or more semiconductor switches to be operated linearly; a digital control unit configured to produce a digital switching pattern for the first set of one or more semiconductor switches of the switching network that produce a first output voltage (U.sub.out,dig); and a linear control unit configured to produce signals for actuating the second set of one or more semiconductor switches of the switching network in a linear mode, wherein the linear control unit is configured to produce a voltage drop (U.sub.out,lin) across and/or a current (I.sub.out,lin) through at least one of the one or more linearly operated semiconductor switches to a target value that is dependent on an instantaneous difference between the first output voltage (U.sub.out,dig) and a voltage (U.sub.AC) of the AC mains.
2. The inverter according to claim 1, wherein the switching network comprises a DC/AC converter with at least one half-bridge.
3. The inverter according to claim 2, wherein the at least one half-bridge comprises a multilevel half-bridge.
4. The inverter according to claim 2, wherein the switching network comprises a DC/DC converter that is connected to the DC/AC converter via a link circuit.
5. The inverter according to claim 4, wherein the DC/DC converter contains the at least one linearly operated semiconductor switch.
6. The inverter according to claim 4, wherein the DC/DC converter is configured to produce a pulsed DC voltage, particularly a half-cycle-sinusoidal DC voltage, and wherein the DC/AC converter comprises a polarity reverser.
7. The inverter according to claim 2, wherein the DC/AC converter comprises at least one linearly operated semiconductor switch.
8. The inverter according to claim 1, wherein the at least one linearly operated semiconductor switch comprises a first and a second semiconductor switch operated in linear mode simultaneously.
9. The inverter according to claim 1, wherein the at least one linearly operated semiconductor switch is part of a connection between the half-bridges and the link circuit, or is part of a connection between a centre tap of the half-bridges and the AC output, or both.
10. The inverter according to claim 1, wherein the at least one semiconductor switch operated in a linear is arranged in a current path, in which current path the current (I.sub.out) to be supplied to the AC-mains is flowing, and wherein optionally the at least one linearly operated semiconductor switch comprises a first and a second semiconductor switch operated in a linear mode, wherein the voltage drop (U.sub.out,lin) is formed by the first and the second semiconductor switch in linear mode collectively.
11. The inverter according to claim 1, wherein the at least one semiconductor switch operated in a linear mode is arranged aside a current path, through which current path the current (I.sub.out) to be supplied to the AC-mains is flowing, and wherein the at least one semiconductor switch operated in a linear mode provides a current bypass relative to the AC-output of the inverter, so that the current flowing through the at least one semiconductor switch operated in a linear mode is bypassed away from the AC-output.
12. The inverter according to claim 1, wherein the at least one semiconductor switch operated in a linear mode comprises a bipolar transistor, an Insulated Gate Bipolar Transistor (IGBT) or a Metal Oxide Semiconductor Field Effect Transistor (MOSFET).
13. The inverter according to claim 1, wherein the inverter comprises no passive filter between the DC/AC converter and the AC output.
14. A control method for an inverter for supplying a power provided as a DC voltage at a DC input to an AC mains connectable to the AC output, wherein the inverter comprises a switching network with a plurality of semiconductor switches comprising a first set of one or more semiconductor switches to be operated digitally and a second set of one or more semiconductor switches to be operated linearly, and a digital control unit for digitally operating the first set of semiconductor switches of the switching network, wherein the control method comprises: actuating the first set of semiconductor switches of the switching network using a digital switching pattern produced in the digital control unit, determining a difference between a first output voltage (U.sub.out,dig) of the switching network, produced by the digital switching pattern, and an AC voltage (U.sub.AC) of the AC mains, and producing a voltage drop (U.sub.out,lin) across and/or a current (I.sub.out,lin) through at least one of the one or more semiconductor switches in the second set of semiconductor switches operated in a linear mode, of the switching network, by actuating the at least one semiconductor switch in the second set operated in a linear mode using a linear control unit, to a target value determined on the basis of the difference.
15. The control method according to claim 14, wherein the current (I.sub.out) to be supplied to the AC-mains is flowing through the at least one semiconductor switch operated in a linear mode.
16. The control method according to claim 14, wherein a current flowing through the at least one semiconductor switch operated in linear mode is bypassed from and not flowing through the AC-output of the inverter.
17. The control method according to claim 14, wherein the at least one semiconductor switch operated in linear mode comprises a first and a second semiconductor switch operated in a linear mode concurrently.
18. The control method according to claim 17, wherein ohmic resistances of the first and the second linearly operated semiconductor switch are varied synchronously with respect to one another over time in order to reduce a differential-mode interference signal that is overlaid on a current (I.sub.out) to be supplied to the AC mains.
19. The control method according to claim 17, wherein ohmic resistances of the first and the second linearly operated semiconductor switch are varied inversely with respect to one another over time in order to reduce a common-mode interference signal that is overlaid on a current (I.sub.out) to be supplied to the AC-mains.
20. The control method according to claim 14, wherein a current amplitude of the current (I.sub.out) to be supplied to the AC mains is controlled by means of a voltage amplitude (U.sub.0,LNK) of a pulsed DC voltage produced by a DC/DC converter across a link circuit of the inverter, particularly a half-cycle-sinusoidal DC voltage.
21. A photovoltaic (PV) installation (26) comprising an inverter according to claim 1 designed as a PV inverter, and a photovoltaic generator connected to the DC input of the inverter.
Description
BRIEF DESCRIPTION OF THE FIGURES
[0043] The disclosure is explained and described to a further degree below on the basis of preferred exemplary embodiments that are depicted in the figures.
[0044] FIG. 1a shows a schematic depiction of a photovoltaic (PV) installation according to the disclosure with an inverter according to the disclosure as a photovoltaic (PV) inverter.
[0045] FIG. 1b shows a PV installation with a first embodiment of the inverter according to the disclosure as a PV inverter in a more detailed depiction.
[0046] FIG. 2a illustrates a PV installation with a current profile for the current to be supplied at a time in a second embodiment of the inverter.
[0047] FIG. 2b illustrates a PV installation from FIG. 2a with a current profile for the current to be supplied at another time.
[0048] FIG. 3a shows part of the switching network using the example of a third embodiment of the inverter according to the disclosure.
[0049] FIG. 3b shows part of the switching network using the example of a fourth embodiment of the inverter according to the disclosure.
[0050] FIG. 3c shows part of the switching network using the example of a fifth embodiment of the inverter according to the disclosure.
[0051] FIG. 3d shows part of the switching network using the example of a sixth embodiment of the inverter according to the disclosure.
[0052] FIG. 4a shows voltage/time profiles for different voltages using the example of the embodiment of the inverter according to the disclosure shown in FIG. 3d.
[0053] FIG. 4b shows voltage/time profiles for different voltages using the example of the embodiment of the inverter according to the disclosure shown in FIG. 1b.
[0054] FIG. 5a shows a PV-installation with a current profile of the current to be supplied at a time in a seventh embodiment of the inverter.
[0055] FIG. 5b illustrates a PV-installation with a current profile of the current to be supplied at another time in a seventh embodiment of the inverter.
DETAILED DESCRIPTION
[0056] FIG. 1a illustrates a schematic depiction of a photovoltaic (PV) installation (26) according to the disclosure with an inverter (1) according to the disclosure as a photovoltaic (PV) inverter. The inverter has a DC input (4) to which a DC source (2), in this case a photovoltaic (PV) generator (25), is connected. The inverter (1) has an AC output (5) connected to an AC mains (3), to which an electric power drawn from the DC source (2) is supplied by the inverter (1) following a conversion of direct current to alternating current or from DC voltage to AC voltage. To convert the power provided as DC voltage, the inverter (1) has a switching network (6) that contains multiple semiconductor switches (6.1-6.n, 9.1, 9.2). The switching network (6) has an input capacitance (15) upstream of it that provides a buffer for the DC voltage or the direct current at the DC input (4) and results in the inverter behaving like a voltage-fed inverter. Digitally operated semiconductor switches (6.1-6.n) of the switching network (6) are actuated by means of a digital control unit (7) and switched either to a conductive (low-impedance) or a nonconductive (high-impedance) state by means of the latter. In this case, an actuating signal or a switching pattern of the digital control unit (7) can have a pulse width modulation (PWM). Appropriate actuation of the digitally operated semiconductor switches (6.1-6.n) converts an input voltage (U.sub.in) provided at the input capacitance (15) into a first output voltage (U.sub.out,dig) at the output of the digitally operated switches (6.1-6.n). In addition, the switching network (6) has at least one linearly operated semiconductor switch (9.1, 9.2) that is actuated by means of a linear control unit (8). In the event of linear actuation of the at least one linearly operated semiconductor switch (9.1, 9.2), the ohmic resistance is changed between load connections of the semiconductor switch (9.1, 9.2) smoothly in general, so that a voltage drop (U.sub.out,lin) is generated across the semiconductor switch (9.1, 9.2) by a current flowing via its load connections. The voltage drop (U.sub.out,lin) across the linearly operated switch(es) (9.1, 9.2) is (are) then adjusted—particularly set and/or regulated—by means of the linear control unit (8) such that, in combination with the first output voltage (U.sub.out,dig), a driving voltage for the current (I.sub.out) to be supplied results that, on account of a basically smooth variation capability for the voltage drop (U.sub.out,lin), has no further abrupt changes. Instead, the combined voltage has a significantly smooth profile and comes very close to a desired sinusoidal shape. The combination of the first output voltage (U.sub.out,dig) and the voltage drop (U.sub.out,lin), particularly the difference therein, corresponds to the output voltage U.sub.out of the inverter (1), i.e. it holds that U.sub.out=U.sub.out,dig U.sub.out,lin. The output voltage is connected to the AC output (5) via an AC relay (16) of the inverter (1). When the AC relay (16) is closed, the output voltage U.sub.out of the inverter is hard-coupled to an AC voltage U.sub.AC for the AC mains (3), particularly to an AC voltage U.sub.AC that is applied to a line arm end of the AC mains (3) that is connected to the AC output (5) of the inverter (1). When there is hard coupling or a closed AC relay (16), therefore, the two voltages are equal at any time, i.e. it holds that U.sub.out=U.sub.AC. Hence, the inverter (1) is capable of altering the voltage at the line arm end of the AC mains (3) at least slightly, and thus producing a voltage gradient within the line arm that allows a current I.sub.out to be supplied in the direction of the AC mains (3). Taking into consideration the sinusoidal output voltage (U.sub.out) or the sinusoidal AC voltage (U.sub.AC) of the AC mains (3), the current (I.sub.out) to be supplied generated by means of the driving voltage is also smooth and free of abrupt changes. Instead, the current (I.sub.out) has, likewise to a great extent, a desired sinusoidal profile that is to the greatest extent free of harmonics. To supply the current (I.sub.out), the combination of the first output voltage (U.sub.out,dig) and the voltage drop (U.sub.out,lin) is provided at the AC output (5) of the inverter (1).
[0057] The digital control unit (7) and the linear control unit (8) may be separate control units within the inverter, but they may also be part of a superordinate control system of the inverter (1), which is symbolized in FIG. 1a by means of a dashed border for the two control units (7, 8). The inverter (1) can optionally have a passive filter (14) for filtering interference current components that are still present out of the current (I.sub.out) to be supplied. In this case, the passive filter (14) has an interconnection of inductances and capacitances. The passive filter (14) is an optional component that may be present, but does not have to be present. Therefore, it is depicted in dashed form in FIG. 1a. If present, the passive filter (14) may be of significantly simpler and cheaper design in comparison with conventional passive filters, however, since the current (I.sub.out) to be supplied now contains only small components of interference current on account of signal shaping of dissipative design that has already taken place.
[0058] FIG. 1b shows a PV installation (26) with a first embodiment of the inverter (1) according to the disclosure as a PV inverter in a more detailed depiction in comparison with FIG. 1a. Similar components of the inverter (1) that also appear in FIG. 1a are provided with like reference symbols in FIG. 1b—as in the subsequent figures. To describe these components, reference is made to the corresponding explanations and the description of figures relating to FIG. 1a.
[0059] Relative to FIG. 1a, FIG. 1b depicts the switching network (6) of the inverter (1) in more detail. In this embodiment, the switching network (6) has a DC/DC converter (12) whose input is connected to the DC input (4) of the inverter (1) via the input capacitance (15). An output of the DC/DC converter (12) is connected to an input of a DC/AC converter (10) via a link circuit (13). The output of the DC/AC converter (10) is connected to the AC output (5) of the inverter via an optional passive filter (14).
[0060] The DC/DC converter (12) is designed as a combined step-up/step-down converter and, for this purpose, has some of the digitally operated semiconductor switches (6.1-6.j, where j<n). It is essentially actuated by means of the digital control unit (7) with the aim of converting the input voltage (U.sub.in) provided at the DC input (4) or of the input capacitance (15) by the DC source (2), as a DC voltage, into a pulsed, particularly into a half-cycle-sinusoidal pulsed voltage (U.sub.LNK) across the link circuit (13). On account of the digitally operated semiconductor switches (6.1-6.j) of the DC/DC converter (12), the pulsed DC voltage (U.sub.LNK) dropped across the link circuit (13) has a ripple-like profile. Individual half-cycles of the pulsed DC voltage (U.sub.LNK) present across the link circuit (13) have subsequently been switched over by means of the DC/AC converter (10) operating as a polarity reverser and, as such, converted into an AC voltage. The voltage ripple still present is removed by dissipation, but at least reduced, by means of at least one linearly operated semiconductor switch (9.1, 9.2) of the DC/AC converter (10). For this purpose, the DC/AC converter (10) is connected for control purposes both to the digital control unit (7) and to the linear control unit (8), since it firstly contains individual instances of the digitally operated semiconductor switches (6.j+1-6.n) as well as the at least one linearly operated semiconductor switch (9.1, 9.2). The digitally and linearly operated switches are not depicted explicitly in FIG. 1b for reasons of clarity. The connection for control purposes is symbolized in FIG. 1b—and in FIG. 1a—by means of dashed arrows to the switching network (6).
[0061] At particular points in the inverter (1), voltage profiles observable therein are outlined schematically as a function of time. As such, above the input capacitance (15) the time profile of the input voltage (U.sub.in) is outlined, which corresponds to that of a pure DC voltage. This does not mean that the input voltage (U.sub.in) does not actually change over time. As such, it changes on the basis of a Maximum Power Point (MPP) tracking method alone—at least on a macroscopic timescale, e.g. on a timescale of a few seconds, or minutes. By contrast, a change in the input voltage (U.sub.in) does not take place, but at least to a much smaller extent, on a microscopic timescale, e.g. on a timescale of a few oscillation periods of the frequency in the AC mains (3). Above the link circuit (13), the time profile of the voltage dropped across that (U.sub.LNK) is depicted. This time profile corresponds to a half-cycle-sinusoidally pulsed DC voltage that has a voltage ripple overlaid on it. At the AC output (5), the time profile of the output voltage (U.sub.out) applied thereto is outlined schematically. This time profile corresponds to an AC voltage that has a smooth sinusoidal shape. The voltage ripple is removed, but at least significantly reduced, by the at least one linearly operated semiconductor switch (9.1, 9.2). In the time profile of the output voltage (U.sub.out), the half-cycle-sinusoidally pulsed DC voltage, including the voltage ripple that is still present, as the DC voltage dropped across the link circuit (13) previously, is also outlined in dashes again for the sake of clarity. To detect voltages, voltage drops and/or currents, there may be suitable voltage and/or current sensors present. These may be connected to a separate evaluation and a regulatory device that may in turn be operatively connected to the digital control unit (7) or the linear control unit (8) and performs or supports regulation or setting of the voltage drop in conjunction with the control. Alternatively, the evaluation and regulatory device may also be an integral part of the digital control unit (7) or linear control unit (8) or of a superordinate control system of the inverter (1). For reasons of clarity, the sensors and the evaluation and regulatory device are not depicted in FIG. 1b—or in the subsequent figures. Similarly, the AC relay (16) is not depicted explicitly in FIG. 1b, or in the subsequent figures, for reasons of clarity. It may nevertheless be present, however.
[0062] FIG. 2a and FIG. 2b illustrate current paths for the current (I.sub.out) to be supplied using the example of an inverter (1) in a second embodiment for two different times. In the second embodiment of the inverter (1), the DC/DC converter (12) of the switching network (6) is embodied as a step-down converter with digitally operated semiconductor switches (6.1, 6.2) and an inductance (20). The DC/AC converter (10) comprises two half-bridges (11a, 11b), each having two semiconductor switches. In this embodiment of the inverter (1), no passive filter (14) is outlined upstream of the AC output (5) of the inverter (1). However, it may likewise be present as an additional optional assembly.
[0063] At the time outlined in FIG. 2a, an upper semiconductor switch of a first half-bridge (11a) and a lower semiconductor switch of a second half-bridge (11b) are operated as first linearly operated semiconductor switch (9.1) and second linearly operated semiconductor switch (9.2) in a linear mode with a variable ohmic resistance between the load connections of the switches. For this purpose, the relevant semiconductor switches are denoted using the symbol for a variable resistor. A lower semiconductor switch of the first half-bridge (11a) and an upper semiconductor switch of the second half-bridge (11b) act as a third digitally operated semiconductor switch (6.3) and as a fourth digitally operated semiconductor switch (6.4), respectively, and are actuated by means of the digital control unit (7) using a digital switching pattern. They are open at the time depicted in FIG. 2a. For the current (I.sub.out) to be supplied, a current path (19.1) from the link circuit (13) via the first linearly operated semiconductor switch (9.1), the AC output (5), the AC mains (3), the second linearly operated semiconductor switch (9.2) back to the link circuit (13) is obtained. The corresponding current path (19.1) for the current (I.sub.out) to be supplied is illustrated schematically in FIG. 2a.
[0064] FIG. 2b depicts a current profile for the current (I.sub.out) to be supplied at a later time. At this time, the upper semiconductor switch of the first half-bridge (11a) and the lower semiconductor switch of the second half-bridge (11b) are operated as third digitally operated semiconductor switch (6.3) and as fourth digitally operated semiconductor switch (6.4), respectively. The digitally operated semiconductor switches (6.3, 6.4) are open at the time depicted in FIG. 2b. At this time, the lower semiconductor switch of the first half-bridge (11a) and the upper semiconductor switch of the second half-bridge (11b) operate as first linearly operated semiconductor switch (9.1) and as second linearly operated semiconductor switch (9.2), respectively.
[0065] In the example depicted, the roles of the digitally operated (6.3, 6.4) and linearly operated semiconductor switches (9.1, 9.2) have therefore been reversed. The semiconductor switches (6.3, 6.4) operated digitally at a previous time as shown in FIG. 2a act as linearly operated semiconductor switches (9.1, 9.2) at the later time depicted in FIG. 2b, and vice versa. The digitally operated semiconductor switches (6.3, 6.4) thus do not have to be operated digitally at all times, but rather can be operated digitally during a first period of time and linearly during a second period of time. The same thus also applies to the linearly operated semiconductor switches (9.1, 9.2).
[0066] For the current (I.sub.out) to be supplied, a current path (19.2) from the link circuit (13) via the second linearly operated semiconductor switch (9.2), the AC output (5), the AC mains (3), the first linearly operated semiconductor switch (9.1) back to the link circuit (13) is obtained at the second time. The corresponding current path (19.2) for the current (I.sub.out) to be supplied is illustrated schematically in FIG. 2b.
[0067] In FIGS. 2a and 2b the semiconductor switches operated in a linear mode are arranged within the current paths 19.1, 19.2, through which current paths 19.1, 19.2 the current (I.sub.out) to be supplied to the AC-mains 3 is flowing. Therefore the current I.sub.out to be supplied also flows through the respective linearly operated semiconductor switches 9.1, 9.2. Within the current paths 19.1, 19.2 the semiconductor switches are conducted in series relative to each other. Therefore the voltage drop (U.sub.out,lin) is generated collectively by the first 9.1 and the second semiconductor switch 9.2 operated in linear mode. Via a concurrent or rather synchronous variation of the ohmic resistances of the first 9.1 and the second linearly operated semiconductor switch 9.2 a differential-mode interference signal that is superposed in the current (I.sub.out) to be supplied can be selectively manipulated, or even selectively be reduced. Accordingly, a common-mode interference signal overlaid on the current (I.sub.out) to be supplied can be selectively manipulated, or even selectively reduced, by a concurrent but inverse variation of the ohmic resistances of the first 9.1 and the second linearly operated semiconductor switch 9.2.
[0068] FIGS. 3a, 3b, 3c, 3d each show part of the switching network (6) using the example of different embodiments of the inverter (1) according to the disclosure. They each depict the DC/AC converter (10) as part of the switching network (6) of semiconductor switches (6.1-6.n, 9.1, 9.2). The input side of the DC/AC converter (10) is connected either to the input capacitance (15) or to the DC input (4) directly. Equally, it is possible for the DC/AC converter (10) to be connected to the input capacitance (15) or the DC input (4) via the link circuit (13) and an upstream DC/DC converter (12) (not depicted in FIG. 3a-3d). The input capacitance (15) and/or the capacitance of the link circuit (13) ensures that the DC/AC converter (10) behaves and accordingly operates as a voltage-fed DC/AC converter (10) and the inverter (1) behaves and accordingly operates as a voltage-fed inverter. The DC/AC converter (10) is connected for control purposes both to the digital control unit (7) and to the linear control unit (8). Additionally, a boundary of the inverter (1) running through the AC output (5) is depicted in the form of a dashed line. The different embodiments of FIG. 3a-3d differ primarily in respect of a respective implementation of the DC/AC converter (10) and an arrangement of the linearly operated semiconductor switches (9.1, 9.2). For the sake of clarity, all of the semiconductor switches in FIGS. 3a-3d, and in FIGS. 2a and 2b, are depicted only in the form of switch symbols without parallel freewheeling diodes associated with each of the switches. However, even if the freewheeling diodes are not shown explicitly, the freewheeling diodes may nevertheless be present.
[0069] In FIG. 3a, the DC/AC converter (10) comprises a first and a second half-bridge, each having two digitally operated semiconductor switches (6.1-6.4). The linearly operated semiconductor switches (9.1, 9.2) are arranged in a connecting line between the half-bridges (11a, 11b) and the link circuit (13), or between the half-bridges (11a, 11b) and the input capacitance (15).
[0070] In contrast to FIG. 3a, in FIG. 3b, the linearly operated semiconductor switches (9.1, 9.2) are each arranged in a connecting line for a centre tap of each half-bridge (11a, 11 b) and a corresponding output connection of the AC output (5). The DC/AC converter (10) of the embodiment shown in FIG. 3c comprises merely one half-bridge (11a). The half-bridge (11a) is embodied in the form of a switchover bridge having two digitally operated semiconductor switches (6.1, 6.2). The DC/AC converter (10) additionally comprises merely one linearly operated semiconductor switch (9.1) that is arranged in a connecting line between the centre tap of the half-bridge (11a) and an output connection of the AC output (5). The link circuit (13) and/or the input capacitance (15) is embodied as a divided link circuit (13) or as a divided input capacitance (15) with a plurality—in this case: two—of series-connected capacitors. In this way, the divided link circuit (13) and/or the divided input capacitance (15) is capable of providing multiple voltage levels. The voltage levels can be explicitly accessed using a multilevel half-bridge as the half-bridge (11a) of the DC/AC converter (10), in which case the centre tap of the respective half-bridge (11a) can be connected to the individual voltage levels. A centre tap of the divided link circuit (13) or of the divided input capacitance (15) is connected to another output connection of the AC output (5) in FIG. 3c.
[0071] The DC/AC converter (10) of the embodiment shown in FIG. 3d has, similarly to the embodiment shown in FIG. 3c, a half-bridge (11a) that is embodied as a multilevel half-bridge. The half-bridge (11a) has a total of eight digitally operated semiconductor switches (6.1-6.8). In conjunction with the divided link circuit (13) or the input capacitance (15) embodied in divided fashion, the half-bridge is capable of connecting a total of five voltage levels to a centre tap associated with it. The centre tap of the half-bridge (11a) is connected to an output connection of the AC output (5) via a linearly operated semiconductor switch (9.1). The further output connection of the AC output (5) is connected to a centre of the divided link circuit (13) or the divided input capacitance (15).
[0072] As an alternative to the merely one depicted half-bridge (11a), the DC/AC converter (10) in the embodiments shown in FIG. 3c and FIG. 3d can also have multiple half-bridges, particularly two half-bridges (11a, 11b). In the latter case, both output connections are each connected to a centre tap of one of the half-bridges (11a, 11 b). The divided link circuit (13) and/or the divided input capacitance (15) can have a different number from the depicted number of series-connected capacitors. Accordingly, the multilevel half-bridge or the multilevel half-bridges may also be designed to connect a different number from the depicted number of voltage levels to the respective centre tap. Equally, as an alternative to the one linearly operated semiconductor switch (9.1), there may also be multiple linearly operated semiconductor switches. As such, e.g. additionally, a second linearly operated semiconductor switch (9.2) may be arranged in a connection between the centre of the divided link circuit (13) and/or the divided input capacitance (15). Equally, it may be arranged in a connection between a centre tap of the second half-bridge (11b) and the output connection of the AC output (5). In FIGS. 3a-3d, passive filters 14 between the DC/AC converter 10 and the AC output of the inverter 1 are not depicted explicitly, for reasons of clarity. Nevertheless, they may still be present as additional assemblies, however.
[0073] FIG. 4a shows voltage/time profiles for different voltages using the example of the embodiment of the inverter according to the disclosure shown in FIG. 3d. For the description that follows, it is assumed that the DC/AC converter (10) of the switching network (6) is connected directly to the DC input (4) or the divided input capacitance (15).
[0074] What is depicted specifically is a profile of the input voltage (U.sub.in), which is measured at the DC input (4) or at the input capacitance (15), in the form of a dash-dot line. The input voltage (U.sub.in) is connected to the input of the DC/AC converter (10) or the relevant half-bridge (11a). On account of a multilevel topology, the half-bridge (11a) is capable of connecting discrete voltage levels to the centre tap of the bridge. Appropriate actuation of the digitally operated semiconductor switches (6.1-6.8) by means of the digital control unit (7) generates the first output voltage (U.sub.out,dig) on the centre tap of the half-bridge (11a). In this case, the first output voltage (U.sub.out,dig) is obtained solely on the basis of the switching behaviour of the digitally operated switches (6.1-6.8) of the half-bridge (11a) and has the staircase-shaped profile depicted in FIG. 4a. The first output voltage (U.sub.out,dig) can be observed in concrete terms at the centre tap of the half-bridge (11a). Equally, it can, in principle, also be observed at the AC output (5) of the inverter (1), namely if all of the linearly operated semiconductor switches (9.1, 9.2) were operated not in the envisaged linear mode but instead in completely closed fashion. In addition, the sinusoidal profile of the AC voltage (U.sub.AC) in the AC mains (3) is depicted in dashed form. In this case, the AC voltage in the AC mains (3) means particularly a voltage profile (U.sub.AC) measured directly at the source of the AC mains (3)—for example a local mains transformer associated with the section of the AC mains (3). In a zero-current state of a connecting line between the inverter (1) and the local mains transformer, this profile is observable to the greatest extent also at the AC output (5) of the inverter (1). The current (I.sub.out) to be supplied to the AC mains (3) flows through the at least one linearly operated semiconductor switch (9.1, 9.2) that is actuated by means of the linear control unit (8) and operated in a linear mode. The at least one linearly operated semiconductor switch (9.1, 9.2) is actuated by the linear control unit (8) such that the linearly operated semiconductor switch has a voltage drop (U.sub.out,lin) produced across it that, in combination with the first output voltage (U.sub.out,dig), likewise has a sinusoidal profile. The voltage drop (U.sub.out,lin) is depicted as a double-headed arrow in FIG. 4a by way of example for two particular times in the time profile. The combination of the voltage drop (U.sub.out,lin) and the first output voltage (U.sub.out,dig) is connected as an output voltage (U.sub.out) to the AC output (5) of the inverter (1). The sinusoidal profile of the output voltage (U.sub.out) corresponds, in the event of hard coupling to a line arm end connected to the AC output, to the AC voltage (U.sub.AC) of the AC mains (3) that prevails at the line arm end. The hard coupling means that the inverter is capable of changing the AC voltage (U.sub.AC) slightly at the line arm end of the AC mains. Additionally, a sinusoidal AC voltage (U.sub.AC,zero current) of the AC mains (3) that characterizes a supply-free or zero-current state (I.sub.out=0) is also depicted schematically. In this case, the AC voltage (U.sub.AC,zero current) characterizing the zero-current state can be detected e.g. when no current (I.sub.out) is supplied to the AC mains (3) or an AC relay (16) of the inverter (1) is open. A difference between the output voltage (U.sub.out), or the AC voltage (U.sub.AC) of the AC mains (3) modified by means of the output voltage (U.sub.out), and the AC voltage (U.sub.AC,zero current) characterizing the zero-current state is a driving force for the current (I.sub.out) to be supplied. The sinusoidal shape of the output voltage (U.sub.out) and the AC voltage (U.sub.AC,zero current) characterizing the zero-current state in the AC mains (3) means that the difference therein ΔU=U.sub.out−U.sub.AC,zero current is also highly sinusoidal. The difference ΔU=U.sub.out−U.sub.AC,zero current is depicted as a double-headed arrow in FIG. 4a for a particular time in the time profile. Since this is the driving force for the current (I.sub.out) to be supplied, the current (I.sub.out) to be supplied is itself also highly sinusoidal and to the greatest extent free of undesirable interference current components or harmonics.
[0075] FIG. 4b shows voltage/time profiles for different voltages using the example of the embodiment of the inverter (1) according to the disclosure shown in FIG. 1b. In this case, the DC/AC converter (10) of the switching network (6) is connected to the DC input (4) or the input capacitance (15) via the link circuit (13) and an upstream DC/DC converter (12). The DC/DC converter (12) is embodied as a combined step-up/step-down converter in this case. The DC/AC converter has two half-bridges (11a, 11b) and is designed to operate as a polarity reverser. By way of example, it should be assumed that the DC/AC converter (10) has two linearly operated semiconductor switches (9.1, 9.2), with in each case, one linearly operated semiconductor switch being arranged in each connecting line between the half-bridges and the link circuit (13).
[0076] The DC input (4) of the inverter (1) or of the input capacitance (15) has the input voltage (U.sub.in) applied to it as a DC voltage. The input voltage (U.sub.in) is depicted as a dot-dash line in FIG. 4b. The DC/DC converter (12) converts the input voltage (U.sub.in) into a half-cycle-sinusoidally pulsed DC voltage that is transferred to the link circuit (13). The voltage (U.sub.LNK) applied to the link circuit (13) is depicted in FIG. 4b by way of example in the form of two sinusoidal half cycles containing a voltage ripple for a period duration of the frequency in the AC mains (3). In time periods in which the input voltage (U.sub.in) is lower than the voltage (U.sub.LNK) applied to the link circuit (13), the DC/DC converter (12) operates as a step-up converter, and it operates as a step-down converter in the other time periods. The DC/AC converter (10) operates as a polarity reverser and switches over every second instance of the sinusoidal half cycles appearing in the link circuit (13) by means of appropriate digitally operated switches (6.j+1-6.n). This is symbolized in FIG. 4b by the curved arrow in conjunction with mirroring of the relevant sinusoidal half cycle on the time axis. The voltage ripple that is still overlaid on the first output voltage (U.sub.out,dig) is removed by means of appropriate actuation of the linearly operated semiconductor switches (9.1, 9.2) by using the latter, by virtue of actuation by means of the linear control unit (8), to produce a voltage drop (U.sub.out,lin) in total, so that the combination of the voltage drop (U.sub.out,lin) with the first output voltage (U.sub.out,dig) has a highly sinusoidal profile. FIG. 4b illustrates the level of the voltage drop (U.sub.out,lin) as a double-headed arrow by way of example for two particular times.
[0077] The sinusoidal profile of the combination of voltage drop (U.sub.out,lin) and first output voltage (U.sub.out,dig) is depicted in the form of a solid line in FIG. 4b as an output voltage (U.sub.out). The sinusoidal output voltage (U.sub.out) is transferred to the AC output (5) of the inverter (1) and is hard-coupled to the AC voltage (U.sub.AC) in the AC mains (3), at least with respect to an AC voltage (U.sub.AC) prevailing at a line arm end of the AC mains (3). In addition, a sinusoidal AC voltage (U.sub.AC,zero current) of the AC mains (3) that characterizes a supply-free or zero-current state (I.sub.out=0) is depicted in the form of a dashed curve in this case too. The difference ΔU=U.sub.out−U.sub.AC,zero current in the output voltage (U.sub.out) or the AC voltage (U.sub.AC) of the AC mains (3) and the AC voltage (U.sub.AC,zero current) characterizing the zero-current state of the line arm at this time in the AC mains (3) is the driving force for the current (I.sub.out) to be supplied. FIG. 4b illustrates the difference ΔU=U.sub.out−U.sub.AC,zero current as a double-headed arrow by way of example for a particular time. Similarly to FIG. 4a, the difference U.sub.out−U.sub.AC,zero current is also highly sinusoidal, which is why the current (I.sub.out) to be supplied is also highly sinusoidal and to the greatest extent free of undesirable interference current components.
[0078] FIGS. 5a and 5b illustrate current paths for the current to be supplied to the AC-mains using the example of an inverter (1) in a seventh embodiment for two different points in time. The seventh embodiment of the inverter (1) is similar to the second embodiment shown in FIGS. 2a and 2b. Therefore in the following only the differences to the second embodiment shown in FIGS. 2a and 2b are explained. At the point in time depicted in FIG. 5a an upper semiconductor switch of the left half-bridge 11a is acting as third digitally operated semiconductor switch 6.3, whereas a lower semiconductor switch of the right half-bridge 11b is acting as fourth digitally operated semiconductor switch 6.4. Both digitally operated semiconductor switches 6.3, 6.4 are closed. Additionally a lower semiconductor switch of the left half-bridge 11a and an upper semiconductor switch of the right half bridge 11b are acting as first linearly and second linearly operated semiconductor switches 9.1 and 9.2, respectively. The semiconductor switches operated in linear mode are arranged aside a current path 19.1 depicted as a dotted line, through which current path 19.1 the current (I.sub.out) to be supplied to the AC mains is flowing. Starting from a substantially open state of the linearly operated semiconductor switches 9.1, 9.2 are somewhat closed and via this moved to a state comprising a somewhat lower ohmic resistance between their load connections. Due to this a fraction of the current (I.sub.out) to be supplied is bypassed along current paths 19.3, 19.4 illustrated as chain dotted line. That respective current fraction accordingly does not flow through the AC-output 5 of the inverter 1 and is therefore not supplied to the AC-mains 3.
[0079] At the point in time depicted in FIG. 5b the semiconductor switches operated in linear mode and the semiconductor switches operated in digital mode are interchanged. Now a lower semiconductor switch of the left half-bridge 11a acts as third 6.3, and an upper semiconductor switch of the right half-bridge 11b acts as fourth semiconductor switch 6.4 operated in a digital mode. Both digitally operated semiconductor switches 6.3, 6.4 are closed at the point in time depicted in FIG. 5b. Furthermore, an upper semiconductor switch of the left half-bridge 11a acts as first linearly operated semiconductor switch 9.1, and a lower semiconductor switch of the right half-bridge 11b acts as second linearly operated semiconductor switch 9.2. Also here, the linearly operated semiconductor switches 9.1, 9.2 are arranged aside a current path 19.2, in which current path 19.2 the current I.sub.out to be supplied to the AC-mains 3 is flowing and which current path 19.2 is depicted in FIG. 5b as a dotted line. Starting from an open state of the linearly operated semiconductor switches 9.1, 9.2 the semiconductor switches 9.1, 9.2 operated in linear mode are somewhat closed and therefore their ohmic resistance between their load connections is somewhat lowered. Due to this a fraction of the current (Iout) to be supplied is directed along current paths 19.3, 19.4 depicted as chain dotted lines through the linearly operated semiconductor switches 9.1, 9.2. Again, that current fraction does not flow through the AC-output 5 of the inverter 1 and therefore is not supplied to the AC-mains.
[0080] Dependent on how the ohmic resistances of the linearly operated semiconductor switches 9.1, 9.2 are varied relative to each other, either a differential-mode interference signal or common-mode interference signal superposed on the current I.sub.out to be supplied to the AC-mains 3 can be selectively manipulated, or even reduced. In particular, a concordant or rather synchronous variation of the ohmic resistances of the first 9.1 and the second linearly operated semiconductor switch 9.2 relative to each other leads to a selective manipulation of a differential-mode interference signal. Furthermore, an inverse variation of the ohmic resistances of first 9.1 and second 9.2 linearly operated semiconductor switch 9.2 leads to a selective manipulation, or even a reduction, of a common mode interference signal.
