Calibrating circuit and calibrating method for display panel

Abstract

A circuit and a calibrating method are provided. A pixel sensor senses a terminal voltage of a driving transistor during a sensing period. A calibration sensor senses a first predetermined voltage and a second predetermined voltage during a calibration period. An amplifying circuit amplifies the terminal voltage according to a gain, and amplifies the first predetermined voltage and the second predetermined voltage according to the gain. An analog to digital converter converts the amplified terminal voltage into a digital code, and converts the amplified first predetermined voltage into a first digital code and converts the amplified second predetermined voltage into a second digital code. A gain adjusting circuit adjusts the gain according to the first digital code and the second digital code. Accordingly, the gain of the amplifying circuit is calibrated.

Claims

1. A calibrating circuit for a display panel, wherein the display panel comprises a source driver, a gate driver, and a pixel circuit comprising a driving transistor, the calibrating circuit in the source driver comprising: a pixel sensor having an input terminal coupled to the pixel circuit through a data line of the display panel, for sensing a terminal voltage of the driving transistor during a sensing period, wherein the terminal voltage of the driving transistor is a threshold voltage; at least one calibration sensor having input terminals coupled to a first predetermined voltage and a second predetermined voltage; an amplifying circuit having an input terminal coupled to the pixel sensor and the at least one calibration sensor, for amplifying the terminal voltage of the driving transistor according to a gain of the amplifying circuit during the sensing period to obtain an amplified terminal voltage, and amplifying the first predetermined voltage and the second predetermined voltage according to the gain of the amplifying circuit during a calibration period to obtain an amplified first predetermined voltage and an amplified second predetermined voltage respectively; an analog to digital converter having an input terminal coupled to an output terminal of the amplifying circuit, for converting the amplified terminal voltage into a digital code during the sensing period, and converting the amplified first predetermined voltage into a first digital code and converting the amplified second predetermined voltage into a second digital code during the calibration period; and a gain adjusting circuit coupled to an output terminal of the analog to digital converter and the amplifying circuit, for adjusting the gain of the amplifying circuit according to the first digital code and the second digital code.

2. The calibrating circuit of claim 1, wherein the gain adjusting circuit comprises: a first register for storing the first digital code; a second register for storing the second digital code; a comparing circuit having input terminals coupled to the first register and the second register, for calculating a first difference between the first digital code and the second digital code; and a controlling circuit adjusting the gain of the amplifying circuit according to the first difference.

3. The calibrating circuit of claim 2, wherein if the first difference is less than a predetermined threshold, the controlling circuit increases the gain of the amplifying circuit, if the first difference is greater than the predetermined threshold, the controlling circuit decreases the gain of the amplifying circuit.

4. The calibrating circuit of claim 3, wherein after the controlling circuit adjusts the gain of the amplifying circuit, the amplifying circuit amplifies the first predetermined voltage and the second predetermined voltage according to the adjusted gain, and the analog to digital converter re-generates the first digital code and the second digital code to obtain a re-generated first digital code and a re-generated second digital code respectively, the comparing circuit calculates a second difference between the re-generated first digital code and the re-generated second digital code, if the first difference is less than the predetermined threshold and the second difference is greater than the predetermined threshold, or the first difference is greater than the predetermined threshold and the second difference is less than the predetermined threshold, the controlling circuit stops adjusting the gain of the amplifying circuit, and if the first difference and the second difference are both less than the predetermined threshold or both greater than the predetermined threshold, the controlling circuit continues adjusting the gain of the amplifying circuit.

5. The calibrating circuit of claim 1, wherein the first predetermined voltage is essentially at 25% of an input converting range of the amplifying circuit, and the second predetermined voltage is essentially at 75% of the input converting range.

6. The calibrating circuit of claim 1, wherein the amplifying circuit comprises: a switch, coupled to the pixel sensor and the at least one calibration sensor; and an amplifier, coupled to the switch, wherein the switch couples the pixel sensor to the amplifier during the sensing period, and couples the at least one calibration sensor to the amplifier during the calibration period, wherein the amplifier comprises: a differential amplifier having a first input terminal and a second input terminal coupled to a second output terminal of the at least one calibration sensor; a first capacitor having a first terminal and a second terminal respectively coupled to the first output terminal of the at least one calibration sensor and the first input terminal of the differential amplifier; a second capacitor having a first terminal and a second terminal respectively coupled to the second output terminal of the at least one calibration sensor and the second input terminal of the differential amplifier; a plurality of third capacitance adjusting circuits, wherein each of the third capacitance adjusting circuits comprises a third capacitor and a first switch, a first terminal of each of the third capacitor is coupled to the first input terminal of the differential amplifier, a second terminal of each of the third capacitor is coupled to a first terminal of one of the first switch, a second terminal of each of the first switches is coupled to a first output terminal of the differential amplifier; a second switch having a first terminal and a second terminal respectively coupled to the first input terminal of the differential amplifier and a first output terminal of the differential amplifier; a third switch having a first terminal coupled to second terminals of the first switches and a second terminal coupled to a common mode voltage; a fourth switch having a first terminal coupled to the second terminals of the first switches and a second terminal coupled to the first output terminal of the differential amplifier; a fourth capacitor having a first terminal coupled to the second input terminal of the differential amplifier; a fifth switch having a first terminal and a second terminal respectively coupled to the second input terminal of the differential amplifier and a second output terminal of the differential amplifier; a sixth switch having a first terminal and a second terminal respectively coupled to a second terminal of the fourth capacitor and the common mode voltage; and a seventh switch having a first terminal and a second terminal respectively coupled to the second terminal of the fourth capacitor and the second output terminal of the differential amplifier, wherein the gain adjusting circuit controls a conducting status of each of the first switches to adjust the gain of the amplifying circuit.

7. A calibrating method for a display panel comprising a source driver, a gate driver, and a pixel circuit comprising a driving transistor, wherein a terminal voltage of the driving transistor is sensed by a pixel sensor, wherein the terminal voltage of the driving transistor is a threshold voltage, the terminal voltage of the driving transistor is amplified according to a gain of the amplifying circuit by an amplifying circuit to obtain an amplified terminal voltage, and the amplified terminal voltage is converted into a digital code by an analog to digital converter during a sensing period, and wherein the calibrating method is performed by a calibrating circuit in the source driver, the calibrating method comprising: sensing a first predetermined voltage and a second predetermined voltage, and amplifying, by the amplifying circuit, the first predetermined voltage and the second predetermined voltage according to the gain of the amplifying circuit during a calibration period to obtain an amplified first predetermined voltage and an amplified second predetermined voltage respectively; converting, by the analog to digital converter, the amplified first predetermined voltage into a first digital code, and converting the amplified second predetermined voltage into a second digital code during the calibration period; and adjusting the gain of the amplifying circuit according to the first digital code and the second digital code.

8. The calibrating method of claim 7, wherein the step of adjusting the gain of the amplifying circuit according to the first digital code and the second digital code comprises: calculating a first difference between the first digital code and the second digital code; if the first difference is less than a predetermined threshold, increasing the gain of the amplifying circuit; and if the first difference is greater than the predetermined threshold, decreasing the gain of the amplifying circuit.

9. The calibrating method of claim 8, further comprising: after adjusting the gain of the amplifying circuit, amplifying, by the amplifying circuit, the first predetermined voltage and the second predetermined voltage according to the adjusted gain, and re-generating, by the analog to digital converter, the first digital code and the second digital code to obtain a re-generated first digital code and a re-generated second digital code respectively; calculating a second difference between the re-generated first digital code and the re-generated second digital code; if the first difference is less than the predetermined threshold and the second difference is greater than the predetermined threshold, or the first difference is greater than the predetermined threshold and the second difference is less than the predetermined threshold, stopping adjusting the gain of the amplifying circuit; and if the first difference and the second difference are both less than the predetermined threshold or both greater than the predetermined threshold, continuing adjusting the gain of the amplifying circuit.

10. The calibrating method of claim 9, wherein the first predetermined voltage is essentially at 25% of an input converting range of the amplifying circuit, and the second predetermined voltage is essentially at 75% of the input converting range.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The invention can be more fully understood by reading the following detailed description of the embodiment, with reference made to the accompanying drawings as follows:

(2) FIG. 1 is a circuit diagram illustrating an active matrix organic light emitting diode (AMOLED) display in the prior art;

(3) FIG. 2 is a schematic circuit diagram illustrating a display device 200 according to an embodiment;

(4) FIG. 3A is a schematic block diagram illustrating a calibrating circuit 300 during the sensing period according to an embodiment;

(5) FIG. 3B is a schematic block diagram illustrating a calibrating circuit 300 during the calibration period according to an embodiment;

(6) FIGS. 4A and 4B are schematic diagrams illustrating the adjustment of the gain according to the first difference in an embodiment;

(7) FIG. 5 is a circuit diagram illustrating the calibration sensor according to an embodiment;

(8) FIG. 6 is a circuit diagram illustrating the amplifier 332 according to an embodiment; and

(9) FIG. 7 is a flowchart illustrating a controlling method for a display panel according to an embodiment.

DETAILED DESCRIPTION

(10) Specific embodiments of the present invention are further described in detail below with reference to the accompanying drawings. In the specification and the claims, “couple” is referred as a direct or indirect connection. For example, when “a first device is coupled to a second device” is described, then it should be referred as the first device being directly connected to the second device, or the first device being indirectly connected to the second device through other devices or connection means. Moreover, the units/structure/steps having the same label represents, if possible, the identical or similar part.

(11) FIG. 2 is a schematic circuit diagram illustrating a display device 200 according to an embodiment. The display device 200 includes a gate driver 210, a source driver 220 and a display panel 230. The display panel 230 includes scan lines (also referred to gate lines), data lines (also referred to source lines) and pixel circuits. Take a scan line 212, a data line 221 and a pixel circuit 231 as examples, the pixel circuit 231 includes a switch 232, a driving transistor 233, a LED 234, a storing capacitor 235, a switch 236 and a switch 237. The LED 234 may be an OLED or other types of LED.

(12) During a scanning period, the gate driver 210 turns off the switch 236 and turns on the switch 237 through a mode line 211. During the scanning period, the gate driver 210 turns on the switch 232 through the scan line 212, so that the source driver 220 transmits a data voltage to the gate of the driving transistor 233 through the data line 221. The data voltage is stored in the storing capacitor 235. A gate voltage of the driving transistor 233 determines a current I2. The current I2 flowing through the OLED 234 determines brightness of the OLED 234.

(13) During a sensing period, the gate driver 210 turns on the switch 236 and turns off the switch 237 through the mode line 211. During the sensing period, the gate driver 210 turns on the switch 232 through the scan line 212, so that a calibrating circuit (will be described below) in the source driver 220 senses a terminal voltage (i.e. threshold voltage in the embodiment of FIG. 2) of the driving transistor 233 through the data line 221. After the terminal voltage of the driving transistor 233 is sensed, the source driver 220 adjusts the data voltage to be written into the pixel circuit 231 to compensate the drift of the threshold voltage.

(14) It should be noted that, the terminal voltage sensed by the source driver 220 in the embodiment of FIG. 2 is the voltage on the gate (drain) of the driving transistor 233, but the pixel circuit 231 may have another different structure in other embodiments. Therefore, the terminal voltage may also be a voltage on the source of the driving transistor 233. The structure of the pixel circuit 231 is not limited in the invention, and which terminal the terminal voltage is on is not limited, either.

(15) FIG. 3A is a schematic block diagram illustrating a calibrating circuit 300 during the sensing period according to an embodiment. Referring to FIG. 2 and FIG. 3A, the calibrating circuit 300 includes a pixel sensor 310, at least one calibration sensor 320, an amplifying circuit 330, an analog to digital converter 340 and a gain adjusting circuit 350. In the embodiment, the amplifying circuit 330 includes a switch 331 and an amplifier 332, in which the switch 331 is coupled to the pixel sensor 310 and the calibration sensor 320, and the amplifier 332 is coupled to the switch 331. The gain adjusting circuit 350 includes a first register 351, a second register 352, a comparing circuit 353 and a controlling circuit 354.

(16) An input terminal of the pixel sensor 310 is coupled to the pixel circuit 231 through the data line 221, and input terminals of the amplifying circuit 330 are coupled to the pixel sensor 310 and the calibration sensor 320. During the sensing period (referring to FIG. 3A), the pixel sensor 310 obtains the terminal voltage of the driving transistor 232, and the switch 331 couples the pixel sensor 310 to the amplifier 332. The pixel sensor 310 transmits the terminal voltage and a common mode voltage to the amplifier 332. The amplifier 332 amplifies the terminal voltage according to a gain. Note that the gain may be greater or less than 1. In the embodiment, the gain is about 0.5, but the invention is not limited thereto. An input terminal of the analog to digital converter 340 is coupled to the amplifying circuit 330 for converting the terminal voltage into a digital code during the sensing period. The digital code is used to adjust the data voltage transmitted to the pixel circuit 231. However, the display device 300 may have multiple amplifiers 332 which may have different gains due to a process drift or other factors. The calibration sensor 320 and the gain adjusting circuit 350 can calibrate the gain of the amplifier 332.

(17) Input terminals of the calibration sensor 320 are coupled to a first predetermined voltage V1, a common mode voltage VCM and a second predetermined voltage V2. During the calibration period (as shown in FIG. 3B), the switch 331 couples the calibration sensor 320 to the amplifier 332, and the calibration sensor 320 sequentially transmits the first predetermined voltage V1 and second predetermined voltage V2 to the amplifier 332. In detail, the calibration sensor 320 first transmits the first predetermined voltage V1 and the common mode voltage VCM to the amplifier 332. The amplifier 332 amplifies the first predetermined voltage V1 according to its gain. Then, the analog to digital converter 340 converts the amplified first predetermined voltage V1 into a first digital code, which is stored in the first register 351. Next, the calibration sensor 320 transmits the second predetermined voltage V2 and the common mode voltage VCM to the amplifier 332, and the amplifier 332 amplifies the second predetermined voltage V2 according to its gain. The analog to digital converter 340 converts the amplified second predetermined voltage V2 into a second digital code which is stored in the second register 352.

(18) Because the first predetermined voltage V1 and the second predetermined voltage V2 are known, and the gain of the amplifier 332 is required to be fixed at a certain value, the first digital code and the second digital code should be two particular values. Therefore, the gain adjusting circuit 350 can adjust the gain of the amplifier 332 according to the first digital code and the second digital code. In the embodiment, the comparing circuit 353 calculates a difference (referred to a first difference) between the first digital code and the second digital code, and the controlling circuit 354 adjusts the gain of the amplifier 332 according to the first difference.

(19) FIGS. 4A and 4B are schematic diagrams illustrating the adjustment of the gain according to the first difference in an embodiment. Referring to FIG. 4A, the horizontal axis illustrates the first predetermined voltage V1 and the second predetermined voltage V2, and the vertical axis represent the output of the analog to digital converter 340. A curve 410 represent an ideal converting curve of the amplifier 332, and a curve 420 is an actual curve. In the embodiment, the amplifier 332 has an input converting range which is, for example, 4 volts to 8 volts. The first predetermined voltage V1 is essentially at 75% of the input converting range (i.e. 7 volts), and the second predetermined voltage V2 is essentially at 25% of the input converting range (i.e. 5 volts). In addition, a digital code outputted from the analog to digital converter 340 has a resolution of 10 bits. Therefore, after the first predetermined voltage V1 and the second predetermined voltage V2 are passed through the ideal amplifier 332, the first digital code should be “767”, and the second digital code should be “256”. However, there is a difference between the actual curve 420 and the ideal curve 410. In the embodiment, the obtained first digital code is “750”, and the second digital code is “273”. The comparing circuit 353 calculates the first difference (i.e. 750−273=477) between the first digital code and the second digital code. The controlling circuit 354 determines whether the first difference is less than a predetermined threshold which is determined according to the digital codes corresponding to the ideal curve 410. In the embodiment, the predetermined threshold is 1024/2=512. If the first difference is less than the predetermined threshold, it means the gain of the amplifier 332 is too small, therefore the controlling circuit 354 increased the gain of the amplifier 332. If the first difference is greater than the predetermined threshold, it means the gain of the amplifier 332 is too large, and therefore controlling circuit 354 decreased the gain of the amplifier 332. In the embodiment of FIG. 4A, the first difference “477” is less than the predetermined threshold “512”, therefore the controlling circuit 354 increases the gain of the amplifier 332. After the gain is adjusted, referring to FIG. 4B, the amplifier 332 has a curve 430 closer to the ideal curve 410 relative to the curve 420.

(20) In the embodiment, the first predetermined voltage V1 is at 75% of the input converting range, the second predetermined voltage V2 is at 25% of the input converting range, and the predetermined threshold is “512”. However, in other embodiments, the first predetermined voltage V1 and the second predetermined voltage V2 may have other values, and thus the predetermined threshold is correspondingly changed. For example, if the first predetermined voltage V1 is at 80% of the input converting range and the second predetermined voltage V2 is at 20%, then the predetermined threshold is about 614 or 615. It is worth mentioning that the first predetermined voltage V1 should not be set too large, and the second predetermined voltage V2 should not be set too small because it may not be linear at two ends of the actual curve 420. In an embodiment, the first predetermined voltage V1 is at 60%-90% of the input converting range, and the second predetermined voltage is at 10%-40% of the input converting range. In addition, if the resolution of the digital code outputted by the analog to digital converter 340 has more or less bits, the predetermined threshold is also correspondingly changed. Moreover, in the embodiment, the gain calibrating circuit 350 adjusts the gain of the amplifier 332 according to the difference between the first digital code and the second digital code, but the gain calibrating circuit 350 may adjust the gain of the amplifier 332 according to the ratio of the first digital code to second digital code in other embodiments.

(21) Referring to FIG. 3B, in an embodiment, the controlling circuit 354 slightly adjusts the gain of the amplifier 332 each time so that the controlling circuit 354 needs to determine whether to stop or continue the adjustment. To be specific, after the gain of the amplifier 332 is adjusted according to the first difference, the first predetermined voltage V1 and the second predetermined voltage V2 are again inputted into the amplifier 332. The amplifier 332 amplifies the first predetermined voltage V1 and the second predetermined voltage V2 according to the adjusted gain, and the analog to digital converter 340 re-generates the first digital code and the second digital code. The re-generated first digital code and the re-generated second digital code are then stored in the first register 351 and the second register 352, respectively. The comparing circuit 353 calculates a difference (also referred to a second difference) between the re-generated first digital code and the re-generated second digital code. If the first difference is less than the predetermined threshold and the second difference is greater than the predetermined threshold (as shown in the embodiment of FIG. 4A and FIG. 4B), or the first difference is greater than the predetermined threshold and the second difference is less than the predetermined threshold, then the controlling circuit 354 stops the adjustment of the gain. If the first difference and the second difference are both less than the predetermined threshold or both greater than the predetermined threshold, it means there is still a gap between the gain of the amplifier 332 and the ideal gain, and thus the controlling circuit 354 continues the adjustment.

(22) FIG. 5 is a circuit diagram illustrating the calibration sensor according to an embodiment. In the embodiment, there are two calibration sensors having identical circuit structures. One of the two calibration sensors receives the first predetermined voltage V1 and the common mode voltage VCM (as illustrated in FIG. 5), and the other one receives the second predetermined voltage V2 and the common mode voltage VCM. For simplification, only the calibration sensor receiving the first predetermined voltage V1 and the common mode voltage VCM is illustrated, and the first predetermined voltage V1 can be replaced with the second predetermined voltage V2 in the other calibration sensor. Referring to FIG. 5, the calibration sensor 320 includes 502, 504 and 505, capacitors 503 and 506, and gain amplifiers 510 and 520. A first terminal of the switch 502 is coupled to the first predetermined voltage V1. A first terminal of the switch 505 is coupled to the common mode voltage VCM. A first terminal and a second terminal of the switch 504 are respectively coupled to a second terminal of the switch 502 and a second terminal of the switch 505.

(23) A first terminal and a second terminal of the capacitor 503 are respectively coupled a first reference voltage VR1 and the second terminal of the switch 502. The first reference voltage VR1 may be any fixed voltage (e.g. system voltage, ground voltage, or another fixed voltage) with any level. A first terminal and a second terminal of the capacitor 506 are respectively coupled to a second reference voltage VR2 and the second terminal of the switch 505. The second reference voltage VR2 may be any fixed voltage (e.g. system voltage, ground voltage, or another fixed voltage) with any level. The first reference voltage VR1 may be identical to or different from the second reference voltage VR2.

(24) An input terminal of the gain amplifier 510 is coupled to the second terminal of the switch 502, and an output terminal of the gain amplifier 510 is taken as a first output terminal VOP of the calibration sensor 320. An input terminal of the gain amplifier 520 is coupled to the second terminal of the switch 505, and an output terminal of the gain amplifier 520 is taken as a second output terminal VON of the calibration sensor 320. The gain amplifier 510 and the gain amplifier 520 may be any type of amplifying circuit. For example, in the embodiment, the gain amplifier 510 and the gain amplifier 520 are unit gain amplifiers.

(25) When the display panel 230 is in a first period (first phase) T1 of the sensing period, the switch 502 and the switch 505 are turned on, and the switch 504 is turned off. Therefore, in the first period T1, the gain amplifier 510 outputs VOP(T1)=V1+Voffset1, and the gain amplifier 520 output VON(T1)=VCM+Voffset2, in which Voffset1 denotes a voltage offset of the gain amplifier 510, and Voffset2 denotes a voltage offset of the gain amplifier 520. The amplifier 332 calculates VOP(T1)−VON(T1)=(V1+Voffset1)−(VCM+Voffset2) during the first period T1. During a second period (second phase) T2 of the sensing period, the switch 502 and the switch 505 are turned off, and the switch 504 is turned on. During the second period T2, the gain amplifier 510 outputs VOP(T2)=Vreset+Voffset1, and the gain amplifier 520 output VON(T2)=Vreset+Voffset2, in which Vreset denotes an input terminal voltage of the gain amplifier 510 and the gain amplifier 520 when the switch 504 is turned on. The amplifier 332 calculates VOP(T2)−VON(T2)=Voffset1−Voffset2 during the second period T2. The amplifier 332 calculates [VOP(T1)−VON(T1)]−[VOP(T2)−VON(T2)]=V1−VCM. Therefore, the voltage offsets of the gain amplifier 510 and the gain amplifier 520 are eliminated.

(26) FIG. 6 is a circuit diagram illustrating the amplifier 332 according to an embodiment. Referring to FIG. 5 and FIG. 6, a first input terminal VIP_GA of the amplifier 332 is coupled to the first output terminal VOP of the calibration sensor 320, and a second input terminal VIN_GA of the amplifier 332 is coupled to the second output terminal VON of the calibration sensor 320. The amplifier 332 includes a first capacitor C1, a second capacitor C2, multiple third capacitance adjusting circuits 610, a fourth capacitor C4, a second switch SW2, a third switch SW3, a fourth switch SW4, a fifth switch SW5, a sixth switch SW6, a seventh switch SW7 and a differential amplifier 620. A first input terminal (e.g. inverting input terminal) and a second input terminal (e.g. non-inverting input terminal) of the differential amplifier 620 are respectively coupled to the first input terminal VIP_GA and the second input terminal VIN_GA of the amplifier 332.

(27) A first terminal and a second terminal of the first capacitor C1 are respectively coupled to the first input terminal VIP_GA of the amplifier 332 and the first input terminal of the differential amplifier 620. Each third capacitance adjusting circuit 610 includes a third capacitor C3 and a first switch SW1. A first terminal of each third capacitor C3 is coupled to the first input terminal of the differential amplifier 620, and a second terminal of each third capacitor C3 is coupled to a first terminal of the first switch SW1. A second terminal of each first switch SW1 is coupled to a first output terminal (e.g. non-inverting output terminal) of the differential amplifier 620. A first terminal and a second terminal of the second switch SW2 are respectively coupled to the first input terminal and the first output terminal of the differential amplifier 620. A first terminal and a second terminal of the third switch SW3 are respectively coupled to a second terminal of each first switch SW1 and the common mode voltage VCM. A first terminal and a second terminal of the fourth switch SW4 are respectively coupled to the second terminal of each first switch SW1 and the first output terminal of the differential amplifier 620.

(28) A first terminal and a second terminal of the second capacitor C2 are respectively coupled to the second input terminal VIN_GA of the amplifier 332 and a second input terminal (e.g. non-inverting input terminal) of the differential amplifier 620. A first terminal and a second terminal of the fifth switch SW5 are respectively coupled to the second input terminal and a second output terminal (e.g. inverting output terminal) of the differential amplifier 620. A first terminal of the fourth capacitor C4 is coupled to the second input terminal of the differential amplifier 620. A first terminal and a second terminal of the sixth switch SW6 are respectively coupled to a second terminal of the fourth capacitor C4 and the common mode voltage VCM. A first terminal and a second terminal of the seventh switch SW7 are respectively coupled to the second terminal of the fourth capacitor C4 and the second output terminal of the differential amplifier 620.

(29) During the first period T1 of the sensing period, the second switch SW2, the third switch SW3, the fifth switch SW5 and the sixth switch SW6 are turned on, and the fourth switch SW4 and the seventh switch SW7 are turned off. During the second period T2 of the sensing period, the second switch SW2, the third switch SW3, the fifth switch SW5 and the sixth switch SW6 are turned off, and the fourth switch SW4 and the seventh switch SW7 are turned on. An output voltage of the differential amplifier 620 is written as the following equation (1), in which Voffset denotes a voltage offset of the differential amplifier 620, and A denotes the gain of the differential amplifier 620.

(30) $\begin{array}{cc}{V}_o=-\left(\frac{A}{1+A}\right)\left(\frac{C1}{C3}\right)\left(\mathrm{VIP\_GA}-\mathrm{VIN\_GA}\right)+\left(\frac{A}{1+A}\right).Math.\mathrm{VCM}+\left[\frac{A}{{\left(1+A\right)}^2}\right]\left(\frac{C1}{C3}\right).Math.\mathrm{VCM}+\left[\frac{A}{{\left(1+A\right)}^2}\right].Math.\mathrm{VCM}+\left[\frac{A}{{\left(1+A\right)}^2}\right]\left(\frac{C1}{C3}\right).Math.V_{\mathrm{offset}}+\left[\frac{A}{{\left(1+A\right)}^2}\right].Math.V_{\mathrm{offset}}& \left(1\right)\end{array}$

(31) It should be noted that the capacitance C3 in the equation (1) is provided by the third capacitors C3. If more first switches SW1 are turn on, more third capacitors C3 are connected in parallel, and thus the capacitance C3 in the equation (1) is greater. In contrast, if at least one of the first switches SW1 is turned off, the capacitance C3 in the equation (1) is decreased. Referring to FIG. 3B and FIG. 6, in the embodiment, when the controlling circuit 354 needs to increase the gain of the amplifier 332, the controlling circuit 354 turns off at least one of the first switches SW1. In contrast, when the controlling circuit 354 needs to decrease the gain of the amplifier 332, the controlling circuit 354 turns on at least one of the first switches SW1. In other words, the controlling circuit 354 controls the conducting status of the first switches SW1 to adjust the gain of the amplifier 332.

(32) FIG. 7 is a flowchart illustrating a controlling method for a display panel according to an embodiment. Referring to FIG. 7, in a step S701, the first predetermined voltage and the second predetermined voltage are sensed during the calibration period, and the first predetermined voltage and the second predetermined voltage are amplified according to the gain by the amplifying circuit. In a step S702, the first predetermined voltage is converted into the first digital code, and the second predetermined voltage is converted into the second digital code by the analog to digital converter during the calibration period. In a step S703, the gain of the amplifying circuit is adjusted according to the first digital code and the second digital code. Each step in FIG. 7 has been described above, and therefore the description of the steps will not be repeated. It is worth mentioning that each step in FIG. 7 can be implemented as program codes or circuits, which is not limited in the invention. In addition, the method in FIG. 7 can be performed with the said embodiments or performed independently.

(33) Although the present invention has been described in considerable detail with reference to certain embodiments thereof, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein. It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims.