Method and system for linearizing a radio frequency power amplifier

Abstract

A method and system for linearizing a Radio Frequency Power Amplifier (RFPA) is disclosed. The method comprises calibrating signals in the RFPA to linearize the RFPA, using at least one of a first signal, a second signal, a third signal, and a fourth signal. The first signal is generated corresponding to ambient temperature. The second signal is generated corresponding to process corner of transistors in the RFPA. The third signal is generated corresponding to power supply voltage. The fourth signal is generated by feeding back output of the RFPA.

Claims

1. A method of linearizing a Radio Frequency Power Amplifier (RFPA), the method comprising: calibrating signals in the RFPA to linearize the RFPA, using at least one of a first signal, a second signal, a third signal, and a fourth signal, wherein the first signal is generated corresponding to ambient temperature, wherein the second signal is generated corresponding to process corner of transistors in the RFPA, wherein the third signal is generated corresponding to power supply voltage, and wherein the fourth signal is generated by feeding back output of the RFPA.

2. The method as claimed in claim 1, wherein the fourth signal is used to calibrate at least one of the first signal, the second signal, and the third signal.

3. The method as claimed in claim 1, wherein the first signal, the second signal, the third signal, and the fourth signal are used to calibrate the bias signal of one or more transistors of the RFPA.

4. The method as claimed in claim 3, wherein the bias signals are generated using a bias generator, wherein the bias generator comprises one of an analogue bias generator, and a digital bias generator.

5. The method as claimed in claim 4, wherein the digital bias generator comprises one of a processor based digital bias generator or a look-up table based digital bias generator.

6. The method as claimed in claim 4, wherein the analogue bias generator generates the bias signals by: generating a cascode bias signal by adding multiples or polynomials of the first signal, the second signal, the third signal, and the fourth signal; generating a bias current using the multiples or polynomials of one of the first signal, the second signal, the third signal, and the fourth signal; and generating an input bias signal based on the cascode bias signal and the bias current.

7. The method as claimed in claim 5, wherein the processor based digital bias generator or the look-up table based digital bias generator generates the bias signals by: converting the first signal, the second signal, the third signal and the fourth signal into a first digital code, a second digital code, a third digital code, and a fourth digital code, respectively; calculating values for the bias signal using one of the processor based digital bias generator and the look-up table based digital bias generator, based on the first digital code, the second digital code, the third digital code, and the fourth digital code; generating one or more digital bias signals based on the values calculated; and generating the bias signals using the one or more digital bias signals.

8. A system for linearizing a Radio Frequency Power Amplifier (RFPA), the system comprising: a circuit to calibrate signals in the RFPA in order to linearize the RFPA, wherein the signals in the RFPA are calibrated using at least one of a first signal, a second signal, a third signal, and a fourth signal, wherein the first signal is generated, by a temperature sensor, corresponding to ambient temperature of the RFPA; wherein the second signal is generated, by a process monitor, corresponding to process corner of transistors in the RFPA, wherein the third signal is generated, by a power supply sensing circuit, corresponding to power supply voltage, and wherein the fourth signal is generated by feeding back output of the RFPA.

9. The system as claimed in claim 8, wherein the fourth signal is used to calibrate at least one of the first signal, the second signal, and the third signal.

10. The system as claimed in claim 8, wherein the first signal, the second signal, the third signal, and the fourth signal are used to calibrate bias signal of the one or more transistors of the RFPA.

11. The system as claimed in claim 10, wherein the bias signals are generated using a bias generator.

12. The system as claimed in claim 11, wherein the bias generator is one of an analogue bias generator, and a digital bias generator.

13. The system as claimed in claim 12, wherein the digital bias generator is one of a processor based digital bias generator and a look-up table based digital bias generator.

14. The system as claimed in claim 12, wherein the analogue bias generator comprises: a cascode bias signal generator to generate a cascode bias signal by adding multiples or polynomials of the first signal, the second signal, the third signal, and the fourth signal; a signal adder to generate a first bias signal by adding the multiples or polynomials of the first signal, the second signal, the third signal, and the fourth signal; a voltage controlled current source to generate a first bias current; and an auxiliary RFPA to generate a second bias signal based on the first bias current and the cascade bias signal.

15. The system as claimed in claim 13, wherein the processor based digital bias generator or the look-up table based digital bias generator comprises: an Analogue to Digital Converter (ADC) to convert the first signal, the second signal the third signal and the fourth signal into a first digital code, a second digital code, a third digital code, and a fourth digital code, respectively; and a processor operable to: calculate values for the bias signals based on the first digital code, the second digital code, the third digital code, and the fourth digital code; and generate one or more digital bias signals based on the calculation; and a Digital to Analogue Converter (DAC) to generate the bias signals from the one or more digital bias signals.

16. The system as claimed in claim 15, wherein the one or more digital bias signals are selected from a lookup table in the look-up table based digital bias generator based on the first digital code, the second digital code, the third digital code, and a fourth digital code.

17. The system as claimed in claim 8, wherein the temperature sensor is at least one of a bandgap temperature sensor, a thermistor based circuit, and an application based integrated chip.

18. The system as claimed in claim 8, wherein the RFPA is at least one of a cascode power amplifier, a low noise amplifier, a pre-power amplifier, a Class A power amplifier, a Class B power amplifier, a Class AB power amplifier, a Class C power amplifier, and a Class D power amplifier.

Description

BRIEF DESCRIPTION OF FIGURES

(1) In the following drawings like reference numbers are used to refer to like elements. Although the following figures depict various examples of the invention, the invention is not limited to the examples depicted in the figures.

(2) FIG. 1 is a block diagram of a system for linearizing a Radio Frequency Power Amplifier, in accordance with one embodiment of the present invention;

(3) FIG. 2 is an exemplary illustration of an analogue bias generator in accordance with another embodiment of the present invention;

(4) FIG. 3 is an exemplary illustration of a cascode bias signal generator in accordance with yet another embodiment of the present invention;

(5) FIG. 4 is an exemplary illustration of an input bias signal generator in accordance with one embodiment of the present invention;

(6) FIG. 5 is an exemplary illustration of a digital bias generator in accordance with one embodiment of the present invention; and

(7) FIG. 6 is a flowchart of a method of linearizing a Radio Frequency power amplifier (RFPA) with a bias generator in accordance with one embodiment of the present invention.

DESCRIPTION

(8) In the present disclosure, relational terms such as first and second, and the like, may be used to distinguish one entity from the other, without necessarily implying any actual relationship or order between such entities. The following detailed description is intended to provide example implementations to one of ordinary skill in the art, and is not intended to limit the invention to the explicit disclosure, as one or ordinary skill in the art will understand that variations can be substituted that are within the scope of the invention as described.

(9) Embodiments of the present disclosure described herein disclose a system and method for linearizing a Radio Frequency Power Amplifier (RFPA). The system discloses a bias generator to generate bias signals and to linearize the RFPAs in spite of variations in ambient temperature and a process corner. Further, the present disclosure discloses a method of reducing dependency of linearity of the RFPA on temperature variations and process corner.

(10) FIG. 1 is a block diagram of a system 100 for linearizing a Radio Frequency Power Amplifier (RFPA) in accordance with one embodiment of the present invention. The system 100 includes a bias generator 105, a matched load 110, a radio frequency power amplifier (RFPA) 115, a resistor 120, a process monitor 125, a temperature sensor 130, and a supply voltage sense 135. The matched load 110 helps in impedance matching. The matched load 110 is at least one of a capacitive load, an inductive load, and a resistive load. Examples of the RFPA 115 include, but are not limited to a cascode power amplifier, a low noise amplifier, a pre-power amplifier, a Class A power amplifier, a Class B power amplifier, a Class AB power amplifier, a Class C power amplifier, and a Class D power amplifier. The RFPA 115 comprises one or more transistors (not shown) interconnected with each other. Examples of transistors include, but are not limited to Metal Oxide Field Effect Transistors (MOSFET), Complementary Metal Oxide Field Effect Transistors (CMOS), JFETS, finfets, mesfets, and Bipolar Junction Transistors (BJT). As RFPA 115 comprises one or more transistors, operating points of the one or more transistors determine linearity and operational aspects of the RFPA 115. Further, the operating points of the one or more transistors are determined by one or more bias signals received at the one or more transistors.

(11) The operating points of the one or more transistors wherein the RFPA 115 exhibits linearity in operation is hereafter referred to as optimum operating points. In other words, when the operating points of the one or more transistors match the optimum operating points, the RFPA 115 functions with linearity. Moreover, when the one or more transistors are at the optimum operating points, the RFPA 115 causes reduced third order Intermodulation Distortion (IM3). In order to operate at the optimum operating points, the system 100 generates the one or more bias signals to bias the one or more transistors. However, the optimum operating points vary with variations in multiple factors. For example, the optimum operating points vary with variations in ambient temperature and supply voltage of the RFPA 115. Further, rate of the variations in the optimum operating points depend on a process corner of the one or more transistors. Hence, while adjusting the one or more bias signals, the process corner and the variations in the ambient temperature and supply voltage have to be accounted for.

(12) In one example, the system 100 generates the one or more bias signals in the bias generator 105. At the time of generating, the system 100 takes into account the variation in the optimum operating point caused due to variation in the ambient temperature. In order to generate the one or more bias signals, at first, the bias generator 105 receives a first signal from the temperature sensor 130. Examples of the temperature sensor 130 include, but are not limited to a bandgap temperature sensor, a thermistor based circuit, and an application based integrated chip. The first signal comprises information regarding the ambient temperature. In one example, the first signal is a V.sub.temp signal. Further, in order to account the variation in the process corner, the bias generator 105 receives a second signal from the process monitor 125. In one example, the second signal is a V.sub.proc signal. In order to account for the variation in the supply voltage, the bias generator 105 receives a third signal from the supply voltage sense block 125. In one example, the third signal is a V.sub.sup signal. The process monitor 125 is an electronic circuit capable of detecting a process corner of the one or more transistors. The second signal comprises information regarding the process corner of the one or more transistors in the RFPA 115. The process corner can be anywhere between the two extreme process corners for which the Foundry supplies device models. The extreme process corners are usually named slow corner and fast corner, weak corner and strong corner etc.

(13) After receiving the first signal, the second signal (i.e, the V.sub.temp signal and the V.sub.proc signal) and the third signal i.e., the supply voltage, the bias generator 105 generates the one or more bias signals. In other words, the bias generator 105 generates the one or more bias signals in accordance with the ambient temperature, the supply voltage and the process corner. Further, the bias generator 105 considers the variations occurring in the first signal, the second signal and the third signal. As a result, the bias generator 105 adjusts the one or more bias signals to circumvent variations and get to the optimum operating points. It is to be understood that the RFPA 115 may suffer from non-linearity as a result of multiple factors other than the variation in the ambient temperature. For example, the RFPA 115 may suffer non-linearity as a result of at least one of a current spike, harmonics, and intermodulation distortion. To compensate for the non-linearity resulting from the multiple factors, the system 100 has to consider a fourth signal, an output of the RFPA 115. In other words, the fourth signal is indicative of a feedback signal from the RFPA 115. In one example, the bias generator 105 senses the fourth signal from the RFPA 115. Specifically, the bias generator 105 senses the fourth signal using the resistor 120. It is to be understood that the fourth signal may have variations. After receiving the fourth signal, the fourth signal is used to calibrate at least one of the first signal, the second signal, and the third signal.

(14) The bias signals are generated by the bias generator 105. The bias generator 105 is one of an analogue bias generator and a digital bias generator. The analogue bias generator comprises multiple analogue components. Examples of the analogue components include, but are not limited to signal adders, signal subtractors, signal multipliers, signal squarer, power amplifiers, and current mirrors. The digital bias generator uses digital components to generate the one or more bias signals. Examples of the digital components include, but are not limited to analogue to digital convertors, digital to analogue converters, logical gates, processors, and field programmable gate arrays. The digital bias generator is at least one of a processor based digital bias generator and a look-up table based digital generator.

(15) In one exemplary illustration of the present invention, the RFPA 115 is a cascode Radio Frequency Power Amplifier (cascade RFPA). The cascode RFPA 115 comprises a cascode transistor and an input transistor. As discussed earlier, when the one or more transistors (the cascode transistor and the input transistor) function at the optimum operating points, the RFPA 115 (the cascode RFPA) functions with linearity. In order to linearize the cascode RFPA 115, the system 100 biases the cascode transistor and the input transistor to the optimum operating points. The system 100 biases the cascode transistor with a cascode bias signal (V.sub.cascode). Further, the system 100 biases the input transistor with an input bias signal (V.sub.input).

(16) In one example, the bias generator 105 is the analogue bias generator. Referring to FIG. 2, an analogue bias generator 200 is explained in detail. The analogue bias generator 200 includes a temperature sensor 205, a process monitor 210, a RFPA 215, a cascode bias signal generator 220, an input bias signal generator 225, and a supply voltage sense 235. The analogue bias generator 200 generates a cascode bias signal, V.sub.cascode in the cascode bias signal generator 220 and an input bias signal, V.sub.input (described with reference to FIG. 1) in the input bias signal generator 225. To generate the V.sub.cascode signal and the V.sub.input signal, the analogue bias generator 200 receives the V.sub.temp signal (described with reference to FIG. 1) signal as input from the temperature sensor 205 and the V.sub.proc signal (described with reference to FIG. 1) as input from the process monitor 210. Input from the process monitor 210 comprises information regarding a process corner of one or more transistors. The one or more transistors comprises a cascode transistor and an input transistor (described with reference to FIG. 1) in the RFPA 215. In other words, the V.sub.proc signal is dependent on the process corner of the transistors. The supply voltage sense 235 senses variations in supply voltage.

(17) The cascode bias signal generator 220 receives the V.sub.temp signal, the V.sub.sup signal and the V.sub.proc signal to generate the V.sub.cascode signal. Further, the input bias signal generator 225 receives the V.sub.temp signal, the V.sub.sup signal and the V.sub.proc signal to generate the V.sub.input signal. Further, the analogue bias generator 200 receives a fourth signal or a feedback signal from the RFPA 215. The analogue bias generator 200 calibrates the V.sub.cascode signal and the V.sub.input signal in accordance with the feedback signal. In one embodiment, the analogue bias generator 200 calibrates at least one of the V.sub.cascode signal, V.sub.temp signal, the V.sub.sup signal, the V.sub.proc signal and the V.sub.input signal in accordance with the feedback signal.

(18) As discussed earlier, the cascode bias signal generator 220 generates the V.sub.cascode signal. With reference to FIG. 3, a cascode bias signal generator 300 is explained in detail. The cascode bias signal generator 300 generates the V.sub.cascode signal (described in FIG. 1) using analogue components. The cascode bias signal generator 300 comprises multiple analogue components such as a first amplifier 305, a second amplifier 310, a third amplifier 320, a first signal squarer 315, and a signal adder 325, a fourth amplifier 330, a second signal squarer 335, and a fifth amplifier 340. The first amplifier 305 is a linear amplifier with gain α.sub.1. The second amplifier 310 is a linear amplifier with gain β.sub.1. The third amplifier 320 is a linear amplifier with gain β.sub.2, The fourth amplifier 330 is a linear amplifier with gain β.sub.3. The fifth amplifier 340 is a linear amplifier with gain β.sub.4.

(19) To generate the V.sub.cascode signal, the cascode bias signal generator 300 receives a first signal, i.e., the V.sub.temp signal as input from the temperature sensor 205. Further, the cascode bias signal generator receives a second signal, i.e., V.sub.proc signal as input from the process monitor 210 (shown in FIG. 2). The V.sub.proc signal is indicative of a process corner of a cascode transistor (described with reference to FIG. 1). Further, the V.sub.proc signal is dependent on a threshold voltage Vt, of the cascode transistor. The threshold voltage Vt is a gate to source voltage differential required to create a conducting path between a source terminal and a drain terminal in the cascode transistor. The V.sub.proc is obtained by the following equation:
Vproc(t)=f(μ*Cox,Vtemp)  (1)

(20) μ*Cox indicates a parameter dependent on the process corner. In one example, the temperature sensor 205 generates the V.sub.temp signal from a band gap voltage reference and additional circuitry in the temperature sensor 205. The V.sub.temp signal varies proportionally with the ambient temperature. The V.sub.temp signal is given by an equation:
Vtemp(t)=f(t)  (2)

(21) In one embodiment, the cascode bias signal generator 300 receives a third signal, i.e., the V.sub.supply signal as input from the supply voltage sense 235, the V.sub.cascode signal is given by an equation:
V.sub.c.sub.ascode(t)=α.sub.1*Vproc(t)+β.sub.1*Vtemp(t)+β.sub.2*Vtemp.sup.2(t)+β.sub.3*Vsup(t)+β.sub.4*Vsup.sup.2(t)  (3)

(22) α.sub.1, β.sub.1 β.sub.2, β3, and β4 are constants obtained from running the first set of simulation tests. To generate the bias signals, the cascode bias signal generator 300 combines the V.sub.temp signal, the V.sub.proc signal and the V.sub.sup signal in accordance with equation (3). Based on the equations one to three, values of the V.sub.temp, V.sub.proc, V.sub.cascode, V.sub.sup and V.sub.input are obtained by running simulation tests by varying the ambient temperature, supply voltage and the process corner.

(23) The cascode bias signal generator 300 generates the α.sub.1*Vproc(t) by passing the V.sub.proc signal through the first amplifier 305. Further, the bias generator 105 generates the β.sub.1*Vtemp(t) by passing the V.sub.proc signal through the second amplifier 310. Further, the bias generator 105 generates the β.sub.2*Vtemp.sup.2(t) by sending the V.sub.temp signal through the first signal squarer 315 and the third amplifier 320, Further, the bias generator 105 generates the β.sub.3*V.sub.sup(t) by passing the V.sub.sup signal through the fourth amplifier 330. Further, the bias generator 105 generates the β.sub.4*Vsup.sup.2(t) by passing the V.sub.sup signal through the second signal squarer 335 and the fifth amplifier 340. Furthermore, the cascode bias signal generator 300 combines output of the first amplifier 305, the second amplifier 310, the third amplifier 320, the fourth amplifier 330, the fifth amplifier 340 in the signal adder 325 to generate the V.sub.cascode signal. In other words, the cascode bias signal generator 300 generates the V.sub.cascode signal by adding multiples of the V.sub.temp signal, the V.sub.proc signal, the V.sub.sup signal, the V.sub.sup.sup.2 signal and the Vtemp.sup.2 signal.

(24) The analogue bias generator 200 (as shown in FIG. 2) generates the V.sub.input signal in the input bias signal generator 225. Referring to FIG. 4, functioning of an input bias signal generator 400 is explained in detail, in accordance with one exemplary embodiment of the present disclosure. The input bias signal generator 400 comprises an auxiliary RFPA 435 to generate the V.sub.input signal. The auxiliary RFPA 435 includes a pair of transistors connected to each other to replicate connections of the one or more transistors in the RFPA 115 (shown in FIG. 1). When the auxiliary RFPA 435 is biased with a bias current I.sub.bias and the V.sub.cascode signal (described with reference to FIG. 3), the auxiliary RFPA 435 generates the V.sub.input signal as an output. Further, the input bias signal generator 400 comprises a first signal squarer 405, a first amplifier 410, a second amplifier 415, a third amplifier 420, a signal adder 425, a Voltage Controlled Current Source (VCCS) 430, a fourth amplifier 440, a second signal squarer 445, and a fifth amplifier 450. The first amplifier 410 is a linear amplifier with gain α.sub.2. The second amplifier 315 is a linear amplifier with gain β5. The third amplifier 420 is a linear amplifier with gain β6. The fourth amplifier 440 is a linear amplifier with gain β.sub.7. The fifth amplifier 450 is a linear amplifier with gain β.sub.8. The voltage controlled current source 430 controlled by a control signal V.sub.CTRL. As discussed earlier, the input bias signal generator 400 generates the V.sub.input signal by biasing the auxiliary RFPA 435 with the bias current signal I.sub.bias and the V.sub.cascode signal. In other words, the auxiliary RFPA 435 generates the V.sub.input based on the bias current signal I.sub.bias and the V.sub.cascode signal. The bias generator 105 generates the bias current I.sub.bias from the voltage controlled current source 430 controlled by the control signal V.sub.CTRL. For example, the control signal V.sub.CTRL is given by an equation:
V.sub.CTRL(t)=α.sub.2*Vproc(t)+β.sub.5*Vtemp(t)+β.sub.6*Vtemp.sup.2(t)+β.sub.7*Vsup(t)+β.sub.8*Vsup.sup.2(t)  (4)

(25) α.sub.2, β.sub.5, β.sub.6, β.sub.7 and β.sub.8 are constants obtained from simulation tests. To generate the control signal V.sub.CTRL, the input bias signal generator 400 combines the V.sub.temp signal and the V.sub.proc signal in accordance with equation (4). Further, the input bias signal generator 400 generates the α.sub.2*V.sub.proc(t) by passing the V.sub.proc signal through the first amplifier 410. Further, the input bias signal generator 400 generates the β.sub.5*V.sub.temp (t) by sending the V.sub.tempj signal through the second amplifier 415. Further, the input bias signal generator 400 generates the β.sub.6*V.sub.temp.sup.2(t) by sending the V.sub.temp signal through the signal squarer 405 and the third amplifier 420. Further, the input bias signal generator 400 generates the β.sub.7*V sup(t) by passing the V.sub.sup signal through the fourth amplifier 440. Further, the input bias signal generator 400 generates the β.sub.8*V sup.sup.2(t) by passing the V.sub.sup signal through the second signal squarer 445 and the fifth amplifier 450. The first signal squarer 405 squares the V.sub.temp signal. Furthermore, the input bias signal generator 400 combines outputs of the first amplifier 410, the second amplifier 415, the third amplifier 420, the fourth amplifier 440, and the fifth amplifier 450 in the signal adder 425 to generate the control signal V.sub.CTRL. In other words, the input bias signal generator 400 generates the V.sub.cascode signal by adding multiples of the V.sub.temp signal, the V.sub.proc, signal, the signal, the V.sub.sup signal, the V.sub.sup.sup.2 signal. The input bias signal generator 400 uses the control signal V.sub.CTRL as input to the voltage controlled current source 430. The voltage controlled current source 430 generates the bias current signal I.sub.bias in accordance with the control signal V.sub.CTRL. The bias current signal I.sub.bias is given by the following equation:
I.sub.bias(t)=G(V.sub.CTRL)=G(α.sub.2*Vproc(t)+β.sub.5*Vtemp(t)+β.sub.6*Vtemp.sup.2(t)+β.sub.7*Vsup(t)+β.sub.8*Vsup.sup.2(t)   (5)

(26) G is the transconductance of the Voltage Controlled Current Source 430. The Voltage Controlled Current Source 430 supplies the bias current signal I.sub.bias to the auxiliary RFPA 435. The auxiliary RFPA 435 generates the V.sub.input signal based on the bias current signal I.sub.bias and the V.sub.cascode signal.

(27) As discussed in FIG. 1, the bias generator 105 may be a digital bias generator. Referring to FIG. 5, a digital bias generator 500 is described in detail. The digital bias generator 500 is one of a processor based digital bias generator and/or a look-up table based digital bias generator. The digital bias generator 500 comprises a plurality of analogue to digital convertors (ADC) such as a first ADC 505, a second ADC 510, a third ADC 515, a digital device 520, and two digital to analogue convertors, a first DAC 525, and a second DAC 530. Further, the digital bias generator 500 comprises a fourth ADC 535. The digital device 520 is at least one of a processor, a look up table, a field programmable gate array, and a flash memory. The digital bias generator 500 generates one or more bias signals required to bias the one or more transistors to the optimum operating points (described with reference to FIG. 1) to linearize the RFPA 115. To generate the one or more bias signals, the digital bias generator 500 receives a V.sub.temp signal from a temperature sensor 130, a V.sub.proc signal from a process monitor, and a feedback signal from the RFPA 115 (shown in FIG. 1). The first ADC 505 in the digital bias generator 500 converts the V.sub.temp signal into a first digital signal and supplies the first digital code to the digital device 520. The second ADC 510 converts the V.sub.proc signal into a second digital signal and supplies the second digital code to the digital device 520. The third ADC 515 converts the feedback signal into a third digital signal and supplies the third digital code to the digital device 520. The fourth ADC 535 converts the supply voltage signal into a fourth digital signal and supplies the fourth digital code to the digital device 520.

(28) In one embodiment of the present invention, the digital device 520 is a processor. The digital device 520 calculates values of the one or more bias signals required to bias the one or more transistors to the optimum operating points. Further, the digital device 520 generates one or more digital bias signals based on the values calculated. In another embodiment of the present invention, the digital device 520 comprises a look-up table. The look-up table comprises values of the one or more bias signals required for multiple combinations of the V.sub.temp signal, the V.sub.proc signal, the feedback signal, and the supply voltage signal. The digital device 520 identifies the values of the one or more bias signals required and generates the one or more digital bias signals. The first DAC 525 and the second DAC 530 generate the one or more bias signals from the one or more digital bias signals.

(29) In one embodiment of the present invention, the one or more bias signals comprises a V.sub.cascode signal and a V.sub.input signal. The digital device 520 generates a fifth digital code in accordance to the value of the V.sub.input signal and a sixth digital code in accordance to the value of the V.sub.cascode signal. The first DAC 525 generates the V.sub.input from the fifth digital signal. The second DAC 530 generates the V.sub.cascode from the sixth digital signal.

(30) FIG. 6 is a flowchart of a method 600 for linearizing a Radio Frequency power amplifier (RFPA) with a bias generator in accordance with one embodiment of the present invention. The RFPA comprises one or more transistors.

(31) At step 610, a first signal corresponding to ambient temperature of the RFPA is generated. In one embodiment of the present invention, the first signal is generated by a temperature sensor (as described in FIG. 1). In one embodiment of the present invention, the first signal is a V.sub.temp signal.

(32) At step 615, a second signal based on the process corner of transistors in the RFPA is generated. In one embodiment of the present invention, the second signal is generated by the process monitor. The second signal is a V.sub.proc signal.

(33) At step 620, a third signal corresponding to power supply voltage is generated.

(34) At step 625, a fourth signal is generated by feeding back output of the RFPA. In one embodiment of the present invention, the fourth signal is generated by the bias generator.

(35) At step 630, signals in the RFPA are calibrated using at least one of the first signal, the second signal, the third signal, and the fourth signal.

(36) Techniques mentioned in the present disclosure invention are further applicable to systems requiring power amplifiers with high degree of linearity in a wide gamut of temperatures and process corners.

(37) Advantageously, the embodiments specified in the present disclosure provide a system and method of linearizing Radio Frequency Power Amplifiers (RFPA). The proposed invention increases allowed temperature range of operation of RFPAs. Further, the proposed invention makes the RFPA independent of variations in temperature and power supply voltage. Moreover, the proposed invention decreases dependency of the RFPAs on process corners.

(38) In the preceding specification, the present disclosure and its advantages have been described with reference to the specific embodiments. However, it will be apparent to a person with ordinary skill in the art that various modifications and changes can be made, without departing from the scope of the present disclosure, as set forth in the claims below. Accordingly, the specification and figures are to be regarded as illustrative examples of the present disclosure, rather than in restrictive sense. All such possible modifications are intended to be included within the scope of present disclosure.