Digital perceptron

Abstract

In view of the neural network information parallel processing, a digital perceptron device analogous to the build-in neural network hardware systems for parallel processing digital signals directly by the processor's memory content and memory perception in one feed-forward step is disclosed. The digital perceptron device of the invention applies the configurable content and perceptive non-volatile memory arrays as the memory processor hardware. The input digital signals are then broadcasted into the non-volatile content memory array for a match to output the digital signals from the perceptive non-volatile memory array as the content-perceptive digital perceptron device.

Claims

1. A digital perceptron device, comprising: a non-volatile content memory array having m rows by n columns of first memory cells for parallel comparing a n-bit input symbol with a number m of n-bit non-volatile content symbols pre-configured in the m rows of first memory cells respectively having m first output nodes, wherein each of the m first output nodes generates an indication signal indicative of whether the n-bit input symbol matches its pre-configured n-bit non-volatile content symbol; a match detector circuit having m detector cells that are respectively connected to the m first output nodes and that have m second output nodes, wherein each of the m detector cells generates a digital switching signal at its second output node after receiving a corresponding indication signal; a non-volatile perceptive memory array having m rows by q columns of second memory cells, wherein the m rows of second memory cells are respectively connected to the m second output nodes and pre-configured with a number m of q-bit non-volatile perceptive symbols, wherein a received digital switching signal with a first voltage level switches on a corresponding row of second memory cells to output a corresponding q-bit non-volatile perceptive symbol as a q-bit output symbol, wherein a received digital switching signal with a second voltage level switches off a corresponding row of second memory cells, and wherein m, n and q are greater than one; wherein each of the m rows by n columns of first memory cells and the m rows by q columns of second memory cells comprises a non-volatile memory (NVM) device pair, and each NVM device pair outputs one of a high operating voltage VDD and a ground voltage VSS of the digital perceptron device in response to two input voltages VDD and VSS, wherein the digital perceptron device further comprises an output bus; and an output buffer and driver unit located between bit lines of the non-volatile perceptive memory array and the output bus for temporarily storing the q-bit output symbol and amplifying the q-bit output symbol signal to drive the output bus, wherein whether the output buffer and driver unit is electrically connected to the bit lines of the non-volatile perceptive memory array depends on a first control signal, and whether the output buffer and driver unit is electrically connected to the output bus depends on a second control signal; and wherein the second control signal is activated when the n-bit input symbol matches one of the number m of pre-configured n-bit non-volatile content symbols.

2. The digital perceptron device according to claim 1, wherein the n-bit input symbol matches zero or one of the number m of pre-configured n-bit non-volatile content symbols so that zero or one of the number m of pre-configured q-bit non-volatile perceptive symbols is outputted as the q-bit output symbol.

3. The digital perceptron device according to claim 1, wherein each of the m detector cells generates the digital switching signal in response to the first control signal, and wherein the first control signal is activated when the digital perceptron device is turned on.

4. The digital perceptron device according to claim 3, further comprising: an input bus for receiving a n-bit input signal; and an input buffer and driver unit connected between bit lines of the non-volatile content memory array and the input bus for temporarily storing and amplifying the n-bit input signal to output the n-bit input symbol according to the first control signal.

5. The digital perceptron device according to claim 1, wherein the m rows by n columns of first memory cells are organized in a plurality of NAND strings and the non-volatile content memory array comprises: a number m of match lines respectively connected to the m first output node, each match line being formed by series-connected switching transistors of the first memory cells in a corresponding NAND string; a number n of first complementary bit line pairs for receiving the n-bit input symbol, each first complementary bit line pair being connected to the first memory cells in a column; and a common source line for connecting the same-side terminals of the match lines altogether to a predetermined voltage terminal.

6. The digital perceptron device according to claim 5, wherein each first memory cell consists of: a first non-volatile memory (NVM) device and a second NVM device, the first NVM device and the second NVM device respectively in a conducting state and a non-conducting state indicating a first non-volatile binary datum, the first NVM device and the second NVM device respectively in the non-conducting state and the conducting state indicating a second non-volatile binary datum; and the switching transistor, wherein two first terminals of the first NVM device and the second NVM device are connected together to a gate electrode of the switching transistor, a second terminal of the first NVM device being connected to a first bit line of one first complementary bit line pair, a second terminal of the second NVM device being connected to a second bit line of the first complementary bit line pair.

7. The digital perceptron device according to claim 1, wherein the non-volatile perceptive memory array comprises: a number m of word lines respectively connected to the m second output node, each word line being formed by gates of access transistors of the second memory cells in a row; a number q of second complementary bit line pairs, each second complementary bit line pair being connected to the second memory cells in a column; and a number q of output bit lines, each of which extends vertically and is connected to the outputs of the second memory cells in a column.

8. The digital perceptron device according to claim 7, wherein each second memory cells consists of: a third NVM device and a fourth NVM device, the third NVM device and the fourth NVM device respectively in a conducting state and a non-conducting state indicating a third non-volatile binary datum, and the third NVM device and the fourth NVM device respectively in the non-conducting state and the conducting state indicating a fourth non-volatile binary datum; and the access transistor, wherein two first terminals of the third NVM device and the fourth NVM device are connected together to a source electrode of the access transistor, a second terminal of the third NVM device being connected to a first bit line of one second complementary bit line pair, a second terminal of the second NVM device being connected to a second bit line of the second complementary bit line pair; wherein drain electrodes of the access transistors in one column are connected together to form one of the output bit lines.

9. The digital perceptron device according to claim 1, wherein the number m of pre-configured n-bit non-volatile content symbols in the non-volatile content memory array and the number m of pre-configured q-bit non-volatile perceptive symbols in the non-volatile perceptive memory array are capable of being re-configured in real time according to at least one of coding efficiency and a learning algorithm.

10. The digital perceptron device according to claim 1, wherein the q-bit output symbol is autonomously processed with the n-bit input symbol according to the number m of pre-configured n-bit non-volatile content symbols and the number m of pre-configured q-bit non-volatile perceptive symbols.

11. A method for operating a digital perceptron device comprising a non-volatile content memory array and a non-volatile perceptive memory array, the method comprising: parallel comparing an n-bit input symbol with a number m of n-bit non-volatile content symbols pre-configured in the non-volatile content memory array having m rows by n columns of first memory cells so that each of the m rows of first memory cells generates an indication signal indicative of whether the n-bit input symbol matches its pre-configured n-bit non-volatile content symbol; respectively obtaining m digital switching signals according to m indication signals; respectively receiving the m digital switching signals by m rows of second memory cells in the non-volatile perceptive memory array having m rows by q columns of second memory cells, wherein the m rows of second memory cells are respectively pre-configured with a number m of q-bit non-volatile perceptive symbols; switching on a corresponding row of second memory cells to output a corresponding q-bit non-volatile perceptive symbol as a q-bit output symbol in response to one digital switching signal having a first voltage level; and switching off a corresponding row of second memory cells in response to one digital switching signal having a second voltage level, wherein m, n and q are greater than one; wherein each of the m rows by n columns of first memory cells and the m rows by q columns of second memory cells comprises a non-volatile memory (NVM) device pair, and each NVM device pair outputs one of a high operating voltage VDD and a ground voltage VSS of the digital perceptron device in response to two input voltages VDD and VSS, wherein the method further comprises: temporarily storing the q-bit output symbol according to a first control signal; amplifying the q-bit output symbol to obtain a q-bit output signal; and outputting the q-bit output signal in response to a second control signal, wherein the second control signal is activated when the n-bit input symbol matches one of the number m of pre-configured n-bit non-volatile content symbols.

12. The method according to claim 11, wherein the n-bit input symbol matches zero or one of the number m of pre-configured n-bit non-volatile content symbols so that zero or one of the number m of pre-configured q-bit non-volatile perceptive symbols is outputted as the q-bit output symbol.

13. The method according to claim 11, wherein the step of respectively obtaining the m digital switching signals further comprises: respectively obtaining the m digital switching signals based on the m indication signals in response to the first control signal, wherein the first control signal is activated when the digital perceptron device is turned on.

14. The method according to claim 13, further comprising: prior to the step of parallel comparing, temporarily storing an n-bit input signal; and amplifying the n-bit input signal to obtain the n-bit input symbol according to the first control signal.

15. The method according to claim 11, wherein the q-bit output symbol is autonomously processed with the n-bit input symbol according to the number m of pre-configured n-bit non-volatile content symbols and the number m of pre-configured q-bit non-volatile perceptive symbols.

16. The method according to claim 11, further comprising: prior to the step of parallel comparing, configuring the non-volatile content memory array with the number m of n-bit non-volatile content symbols and the non-volatile perceptive memory array with the number m of q-bit non-volatile perceptive symbols according to at least one of coding efficiency and a learning algorithm.

17. The method according to claim 11, further comprising: after the steps of switching on and switching off, re-configuring the non-volatile content memory array with a number m of updated n-bit non-volatile content symbols and the non-volatile perceptive memory array with a number m of updated q-bit non-volatile perceptive symbols according to at least one of coding efficiency and a learning algorithm.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) For a better understanding of the present invention and to show how it may be carried into effect, reference will now be made to the following drawings, which show the preferred embodiment of the present invention, in which:

(2) FIG. 1 shows the conventional Von-Neumann computing architecture for a typical Central Processing Unit (CPU).

(3) FIG. 2 shows the schematics of the digital perceptron according to the invention.

(4) FIG. 3 shows the schematic of a pair of complementary non-volatile memory devices according to the invention.

(5) FIG. 4 illustrates the configuration definition of the non-volatile memory data for the pair of complementary non-volatile memory devices in FIG. 3.

(6) FIG. 5 summarizes the applied voltage biases for the input digital data signals to match the configured non-volatile memory data defined in FIG. 4.

(7) FIG. 6 shows the n-bit×m-rom NAND-type non-volatile content memory array in the digital perceptron according to one embodiment of the invention.

(8) FIG. 7 shows the schematic of n-bit input buffer and driver unit in the digital perceptron according to an embodiment of the invention.

(9) FIG. 8 shows the schematic of a match detector in the digital perceptron according to an embodiment of the invention.

(10) FIG. 9 shows the schematic of the Match Logic circuitry in the digital perceptron according to an embodiment of the invention.

(11) FIG. 10 shows a q-bit×m-row CEEPROM memory array in the digital perceptron according to an embodiment of the invention.

(12) FIG. 11 shows the schematic of q-bit output buffer and driver unit in the digital perceptron according to an embodiment of the invention.

DETAILED DESCRIPTION OF THE INVENTION

(13) The following detailed description is meant to be illustrative only and not limiting. It is to be understood that other embodiment may be utilized and element changes may be made without departing from the scope of the present invention. Also, it is to be understood that the phraseology and terminology used herein are for the purpose of description and should not be regarded as limiting. Those of ordinary skill in the art will immediately realize that the embodiments of the present invention described herein in the context of methods and schematics are illustrative only and are not intended to be in any way limiting. Other embodiments of the present invention will readily suggest themselves to such skilled persons having the benefits of this disclosure. In the figures of the accompanying drawings, elements having the same reference numeral designations represent like elements throughout.

(14) In one embodiment, the complementary Non-Volatile Memory (NVM) devices 310 and 320 have applied to store a non-volatile binary digit (bit) as shown in FIG. 3. The terminals of the two NVM devices 310 and 320 are connected together to form the output node “O” 315 of the complementary non-volatile memory device pair 300. The other two terminals 311 and 321 of the complementary non-volatile memory pair form the input nodes, a “B” node 311 and a “B” node 321, respectively. The complementary pair of the NVM devices 310 and 320 can be configured as one is in “conducting state” and the other is in “non-conducting state”. As illustrated in FIG. 4, we can define the non-volatile datum “1” for the NVM device 310 configured in “conducting state” and the NVM device 320 configured in “non-conducting state”, and the non-volatile datum “0” for the NVM device 310 configured in “non-conducting state” and the NVM device 320 configured in “conducting state”. With the digital signals, V.sub.DD and V.sub.SS, biased to the input nodes, the “B” node 311 and the “B” node 321, the signals at the output node “O” 315 are V.sub.DD and V.sub.SS for the non-volatile data “1” and “0”, respectively.

(15) For matching the input digital data with the non-volatile data in the complementary non-volatile memory device pairs 300, we apply (V.sub.DD and V.sub.SS) signals to “B” node 311 and “B” node 321 for input datum “1”, and (V.sub.SS and V.sub.DD) signals to “B” node 311 and “B” node 321 for input datum “0”, respectively. Accordingly the signals at the output node “O” 315 for “matching” and “not-matching” the input data with the non-volatile data are always V.sub.DD and V.sub.SS, respectively. The digital signals for matching the input data and non-volatile data are summarized in FIG. 5.

(16) We then apply the complementary non-volatile memory pair device 300 and a switching N-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) device 630 to form the non-volatile content memory cell 650 shown in FIG. 6. The output node 315 of the complementary non-volatile memory pair device 300 is connected with the gate of N-type MOSFET device 630 in each non-volatile content memory cell 650. For the “n”-bitדm”-row NAND-type content memory array 600 shown in FIG. 6, the input nodes 311 and 321 of the complementary non-volatile memory pair devices 300 in each column are connected to form BL(i) line 613 and BL(i) line 614 for i=1, 2 . . . , n columns. The N-type MOSFET devices 630 in each row are connected in series to form the matching lines ML(j) 615, for j=1, 2 . . . , m rows, of the NAND-type content memory array 600. End nodes 612 of the matching lines 615 are connected altogether to form the common source line (CSL) 610 tied to the ground voltage. When the input digital signals, (V.sub.DD and V.sub.SS) for datum “1”, and (V.sub.SS and V.sub.DD) for datum “0”, are applied to BL(i) line and BL(i) line respectively for searching non-volatile digital data in the n-bit columns, the “matching” signal V.sub.DD at node 315 turns on the N-type MOSFET devices 630 to electrically connect their source electrodes 631 and drain electrodes 633 in the non-volatile content memory cells 650. While the “not-matching” signal V.sub.SS turns off the N-type MOSFET devices 630 to electrically disconnect their source electrodes 631 from drain electrodes 633 in the non-volatile content memory cells 650. Therefore if and only if the n-bit input digital signals match the entire row of n-bit non-volatile data for turning on all the N-type MOSFET devices 630 in the row, the output node 611 of the matching line ML(jm) 615 is electrically connected to the ground CSL line 610.

(17) In the embodiment, the n-bit input buffer and driver unit 700 is formed by a row of “n” input buffer and driver cells 750. Each input buffer and driver cell i 750, for each i=1, 2 . . . , n, consists of two transmission gates 712 and 713, cross-inverter buffer 710, and a pair of bit-datum drivers 720. When the “V.sub.DD” signal is at the “enable high” node 210, the transmission gate 712 is “on” to pass the digital signals from the input node D (i) 711 to the cross-inverter buffer 710. Meanwhile the bit-datum signal and its complementary signal from the cross-inverter buffer 710 are amplified by the bit-datum driver 720 at the nodes 730 and 731 to drive up the bitlines BL(i) and BL(i) in the non-volatile content memory array 600. When the “V.sub.SS” signal is at the “enable high” node 210, the transmission gates 712 are “off” to disconnect from the input node D(i) 711 and the transmission gate 713 are “on” to retain the data in the cross-inverter buffers 710. The row of “n” input buffer and driver cells 750 are synchronously controlled by the “enable high” signals at node 210 for receiving the n-bit data signals from the n-bit input bus lines 250 and retaining the n-bit data in the data buffers 710.

(18) In the embodiment, the match detector 800 is formed by a column of “m” match detector cells 850. Each match detector cell 850 consists of the match-line pre-charging PMOSFET 810, the “hit” PMOSFET 820, the conversion buffer 830, the transmission gates 840 and 841, the match-value buffer 860, and the wordline driver 870. When the “enable high” signal V.sub.DD is at the node 210, for each j=1, 2 . . . , m, the match-line pre-charging PMOSFET devices 810 are “off” to disconnect the match-line nodes ML(j) 811 from V.sub.DD, and the transmission gates 840 are “on” to receive the voltage signals from the output lines 831 of the conversion buffers 830. If and only if the n-bit input digital data match the row of n-bit non-volatile data to connect the row match-line to the ground potential in the non-volatile content memory array 600, the voltage potential for the matched node ML(jm) 811 is rapidly discharged from the initial voltage V.sub.DD to the ground voltage V.sub.SS. The data match signal V.sub.DD at 831 for the matched row is then captured in the match-value buffer 860. The match signal V.sub.DD in the match-value buffer 860 is amplified by the wordline driver 870 at the connecting node 871 to switch on the correspondent wordline W(jm) in the non-volatile CEEPROM array 100. Otherwise, the voltage potentials at the ML(j) nodes 811, j≠jm, for the “not-match” rows remain near V.sub.DD for the period of “enable high” time. The data unmatched signal V.sub.SS in the match-value buffers 860 for the “not-match” rows remains off for the correspondent wordlines in the non-volatile CEEPROM array 100. Meanwhile for the matched row, the voltage signal V.sub.SS at node 811 by discharging one of the match-lines can turn on the “hit” PMOSFET 820 in the match detector cell 850 to charge the “H” node 211 to V.sub.DD. Otherwise, if none of the rows in the n-bit×m-row non-volatile content memory array 600 can match to discharge their match-lines, the output signal at the “H” 211 cannot be charged to V.sub.DD due to all the “hit” PMOSFET devices 820 in the match detector cells 850 being off. The V.sub.DD signal at the “H” node 211 is applied to activate the “Match Logic” circuitry 900 to connect the q-bit output buffer and driver unit 110 with the output bus-lines 251 for sending the output digital signals.

(19) In the embodiment, the “Match Logic” circuitry 900 is shown in FIG. 9. When the “enable high” node 210 is applied with V.sub.SS, the PMOSFET 910 and the NMOSFET 920 are both “on” to have the voltage potential V.sub.DD at node 911 such that the voltage potential at the node “send high” 208 of the half latch 940 is V.sub.SS. When the “enable high” node 210 is activated with V.sub.DD to turn off both PMOSFET 910 and NMOSFET 920, the NMOSFET 930 is “on” only with V.sub.DD at the “H” node 211 to pull down the voltage potential at node 911 to the ground voltage such that the voltage potential at the node “send high” 208 of the half latch 940 is V.sub.DD. Therefore the V.sub.DD signal at the node “send high” 208 of the half latch 940 is applied to connect the q-bit output buffer and driver unit 110 to the q-bit output bus-lines 251 only for the V.sub.DD signal at the “H” node 211. Accordingly, if the n-bit input data match one row of n-bit non-volatile content data in content memory array 600, the V.sub.DD signal at the “H” node 211 from one of the match detector cells 850 activates the “Match Logic” circuitry 900 to connect the q-bit output buffer and driver unit 110 with the q-bit output bus-lines 251. Otherwise, the q-bit output buffer and driver unit 110 are not connected with the output q-bit bus-lines 251 for the “no-match” content memory situation.

(20) In the embodiment the “q”-bitדm”-row CEEPROM array 100 is shown in FIG. 10. We then apply the complementary non-volatile memory pair device 300 and an access NMOSFET device 130 to form a CEEPROM cell 120. The input nodes 311 and 321 of the complementary non-volatile memory pair devices 300 in each column are connected to form BL(k) line 101 and BL(k) line 102 for k=1, 2 . . . , q columns. The output node 315 of the complementary non-volatile memory pair device 300 is connected to the source electrode of the access NMOSFET 130 with the drain electrode attached to the output bitline BC(k) 106. The gates of the access NMOSFET devices 130 in the row j for j=1, 2 . . . , m, are connected to form the wordline W(j) 105 of the CEEPROM array 100. When the bitlines BL(k) and BL(k) for k=1, 2 . . . , q are biased with the V.sub.DD and V.sub.SS respectively, the signals at the output nodes 315 of the complementary non-volatile memory device pairs 300 are V.sub.DD for the non-volatile datum “1” and V.sub.SS for the non-volatile datum “0”. If the match detector 800 sends a match signal V.sub.DD to turn on the correspondent wordline W(j) in response to the matched row in the non-volatile content memory array 600, the signals of the q-bit data stored in the row of the CEEPROM cells 120 are passed to the output bitlines BC(k) 106 for k=1, 2 . . . , q. Otherwise, the correspondent wordlines with the unmatched signal V.sub.SS from the match detectors 800 in response to the unmatched rows in the non-volatile content memory array 600 remain off to output no data to the output bitlines BC(k) 106 for k=1, 2 . . . , q.

(21) In the embodiment, the q-bit output buffer and driver unit 110 are formed by a row of “q” output buffer and driver cells 150. The input node 155 of the output buffer and driver cell 150 is connected to the output bitline BC(k), for each k=1, 2 . . . , q, of the q-bit×m-row CEEPROM array 100. The output buffer and driver cell 150 consists of two transmission gates 151 and 152, cross-inverter buffer 153, and tri-state output driver 154. When the “enable high” node 210 is activated with V.sub.DD, the row of the transmission gates 151 are turned on for sending the signals from the output bitline BC(k), for k=1, 2 . . . , q, to the cross-inverter buffers 153. If the row of tri-state drivers 154 is activated by the “send high” signal V.sub.DD at the node 208, the q-bit data are then amplified by the tri-state driver 154 to drive the q-bit output bus lines 251 for sending the perceptive digital data out of the digital perceptron 200.

(22) The aforementioned description of the preferred embodiments of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form or to exemplary embodiments disclosed. Accordingly, the description should be regarded as illustrative rather than restrictive. Obviously, many modifications and variations of non-volatile memory elements including the types of non-volatile memory devices such as the conventional MOSFET devices with floating gate, charge trap dielectrics, or nano-crystals for charge storage material, and the non-volatile memory devices having the “conducting” and “non-conducting” states to form a complementary memory device pair such as Read Only Memory (ROM), Phase Change Memory (PCM), Programmable Metallization Cell (PMC), Magneto-Resistive Random Memories (MRAM), Resistive Random Access Memory (RRAM), Carbon Nano-Tube Memory (CNTM), and Nano-Random Access Memory (NRAM) will be apparent to practitioners skilled in this art. The embodiments are chosen and described in order to best explain the principles of the invention and its best mode practical application, thereby to enable persons skilled in the art to understand the invention for various embodiments and with various modifications as are suited to the particular use or implementation contemplated. It is intended that the scope of the invention be defined by the claims appended hereto and their equivalents in which all terms are meant in their broadest reasonable sense unless otherwise indicated. The abstract of the disclosure is provided to comply with the rules requiring an abstract, which will allow a searcher to quickly ascertain the subject matter of the technical disclosure of any patent issued from this disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Any advantages and benefits described may not apply to all embodiments of the invention. It should be appreciated that variations may be made in the embodiments described by persons skilled in the art without departing from the scope of the present invention as defined by the following claims. Moreover, no element and component in the present disclosure is intended to be dedicated to the public regardless of whether the element or component is explicitly recited in the following claims.