Method of Producing Transition Metal Dichalcogenide Layer
20170250075 · 2017-08-31
Assignee
Inventors
Cpc classification
H01L21/0262
ELECTRICITY
H01L21/02068
ELECTRICITY
C23C16/45553
CHEMISTRY; METALLURGY
H01L21/02568
ELECTRICITY
International classification
H01L21/02
ELECTRICITY
C23C16/30
CHEMISTRY; METALLURGY
C23C16/455
CHEMISTRY; METALLURGY
Abstract
Method of producing one or more transition metal dichalcogenide (MX.sub.2) layers on a substrate, comprising the steps of: obtaining a substrate having a surface and depositing MX.sub.2 on the surface using ALD deposition, starting from a metal halide precursor and a chalcogen source (H.sub.2X), at a deposition temperature of about 300° C. Suitable metals are Mo and W, suitable chalcogenides are S, Se and Te. The substrate may be (111) oriented. Also mixtures of two or more MX.sub.2 layers of different compositions can be deposited on the substrate, by repeating at least some of the steps of the method.
Claims
1. A method of producing at least one transition metal dichalcogenide layer (MX.sub.2) on a substrate, the method comprising: obtaining a substrate having a surface; and depositing a transition metal dichalcogenide layer (MX.sub.2) on the surface using ALD deposition, starting from a metal halide precursor and a chalcogen source (H.sub.2X).
2. The method according to claim 1 wherein the surface comprises at least one layer of dielectric.
3. The method according to claim 1 wherein the surface comprises a sacrificial layer.
4. The method according to claim 1, further comprising functionalizing the surface before depositing the transition metal dichalcogenide layer (MX.sub.2).
5. The method according to claim 4, wherein functionalizing the surface comprises functionalizing the surface with at least one of: SiH.sub.4, Si.sub.2H.sub.2, Si.sub.2H.sub.6, Si.sub.3H.sub.8, B.sub.2H.sub.6, or a combination thereof.
6. The method according to claim 4, wherein functionalizing the surface comprises an O.sub.3 oxidation at 40° C. to 80° C. for 200 to 1000 msec.
7. The method according to claim 4, wherein functionalizing the surface comprises annealing the substrate with H.sub.2S at a temperature in the range of 300° C. to 550° C. during a period ranging from 1 to 40 minutes.
8. The method according to claim 1, wherein depositing the transition metal dichalcogenide layer (MX.sub.2) on the surface using ALD deposition comprises depositing the transition metal dichalcogenide layer (MX.sub.2) on the surface using Plasma Enhanced ALD deposition.
9. The method according to claim 1, wherein depositing the transition metal dichalcogenide layer (MX.sub.2) is performed at a deposition temperature in the range of 250° C. to 450° C.
10. The method according to claim 1, further comprising removing a native oxide from the surface.
11. The method according to claim 10, wherein removing the native oxide comprises HF/H.sub.2O dipping the substrate.
12. The method according to claim 11, wherein removing the native oxide further comprises H.sub.2 baking of the substrate during at least 5 minutes at a temperature in the range of 700° C. to 800° C.
13. The method according to claim 1, wherein a metal of the metal halide precursor is selected from the group consisting of Mo and W, and wherein a chalcogen of the chalcogen source (H.sub.2X) is selected from the group consisting of S, Se, and Te.
14. The method according to claim 1, wherein the substrate comprises a (111) oriented semiconductor substrate or a substrate having a surface which is suitable for epitaxial seeding of a transition metal dichalcogenide layer.
15. A method of producing at least two transition metal dichalcogenide materials on a substrate, the method comprising: providing a first metal dichalcogenide material on the substrate using the method of claim 1, thereby using a first metal halide precursor and a first chalcogen source; providing a second metal dichalcogenide material on the substrate by using ALD deposition, starting from a second metal halide precursor and a second chalcogen source, wherein the first metal halide precursor is different from the second metal halide precursor and/or the first chalcogen source is different from the second chalcogen source.
16. The method according to claim 1, further comprising providing a sulphur layer on the surface.
17. The method according to claim 16, further comprising exposing the substrate to a plurality of gas pulses, wherein the gas pulses comprise at least one of: WF.sub.6, Si.sub.2H.sub.6, H.sub.2S, or an inert gas.
18. The method according to claim 16, wherein providing the sulphur layer comprises exposing the substrate to H.sub.2S.
19. The method according to claim 2, wherein the at least one layer of dielectric comprises at least one of: Si.sub.3N.sub.4, SiO.sub.2, Al.sub.2O.sub.3, HfO.sub.2, or ZrO.sub.2.
20. The method according to claim 2, wherein the at least one layer of dielectric formed via epitaxial growth.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
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[0058] The drawings are only schematic and are non-limiting. In the drawings, the size of some of the elements may be exaggerated and not drawn on scale for illustrative purposes. Any reference signs in the claims shall not be construed as limiting the scope.
[0059] In the different drawings, the same reference signs refer to the same or analogous elements.
DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS
[0060] The present invention will be described with respect to particular embodiments and with reference to certain drawings but the invention is not limited thereto but only by the claims. The drawings described are only schematic and are non-limiting. In the drawings, the size of some of the elements may be exaggerated and not drawn on scale for illustrative purposes. The dimensions and the relative dimensions do not correspond to actual reductions to practice of the invention.
[0061] The terms first, second and the like in the description and in the claims are used for distinguishing between similar elements and not necessarily for describing a sequence, either temporally, spatially, in ranking or in any other manner. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments of the invention described herein are capable of operation in other sequences than described or illustrated herein.
[0062] Moreover, the terms top, under and the like in the description and the claims are used for descriptive purposes and not necessarily for describing relative positions. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments of the invention described herein are capable of operation in other orientations than described or illustrated herein.
[0063] It is to be noticed that the term “comprising”, used in the claims, should not be interpreted as being restricted to the means listed thereafter; it does not exclude other elements or steps. It is thus to be interpreted as specifying the presence of the stated features, integers, steps or components as referred to, but does not preclude the presence or addition of one or more other features, integers, steps or components, or groups thereof. Thus, the scope of the expression “a device comprising means A and B” should not be limited to devices consisting only of components A and B. It means that with respect to the present invention, the only relevant components of the device are A and B.
[0064] Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment, but may. Furthermore, the particular features, structures or characteristics may be combined in any suitable manner, as would be apparent to one of ordinary skill in the art from this disclosure, in one or more embodiments.
[0065] Similarly it should be appreciated that in the description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various inventive aspects. This method of disclosure, however, is not to be interpreted as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this invention.
[0066] Furthermore, while some embodiments described herein include some but not other features included in other embodiments, combinations of features of different embodiments are meant to be within the scope of the invention, and form different embodiments, as would be understood by those in the art. For example, in the following claims, any of the claimed embodiments can be used in any combination.
[0067] In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the invention may be practiced without these specific details. In other instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.
[0068] In this document, when reference is made to a “monolayer of MX.sub.2 material” or a “layer of a 2D transition metal dichalcogenide”, reference is made to a tri-atomic layer structure consisting of a single metal layer sandwiched between two chalcogen atomic layers.
[0069] In this document, when reference is made to a “monolayer stack”, reference is made to a structure comprising one or more monolayers. As an example, the right hand part of
[0070] In this document, the unit of Angstrom is used, 1 Å=0.1 nm.
[0071] As described in the background section, atomic layer deposition (ALD) is a known technique for depositing two-dimensional (2D) transition metal dichalcogenides (MX.sub.2) on a semiconductor, for instance silicon, substrate. This technique requires suitable precursors, which are volatile with sufficient vapor pressure at reasonable temperatures in order to inject them into the reactor. Suitable metal halide precursors are e.g. the metal hexafluorides, such as WF.sub.6, MoF.sub.6. WF.sub.6 is a well-known gas in semiconductor manufacturing, used in dry etch processes. MoF.sub.6 is a solid with melting point of about 17.5° C., and hence is liquid at room temperature (25° C.). They are commercially available. The present invention is not limited thereto, and other materials (e. g. comprising other halogens such as Cl) may be used.
[0072] An ALD process in embodiments of the present invention may be a thermal ALD process or a plasma enhanced ALD process. In a general ALD process, different precursors are injected into the reactor in consecutive pulses, and separated by purge steps with an inert purge gas. The assembly of pulses and purges is called a unit deposition cycle. In every precursor pulse, the precursor adsorbs on the surface until saturation. In a thermal ALD process, the precursors will react with the surface and form a chemical bond, activated by the temperature. In this case, heat is applied to initiate a chemical reaction between the surface and the adsorbent, so as to facilitate surface reactions which allow for the formation of thin films in a stepwise fashion. Chemical gases are carefully selected for ALD so that after a single pulse of the precursor, the surface is saturated and no further reactions take place. A plasma enhanced ALD process is an ALD process including a plasma enhancement step rather than a thermal activation. In a plasma enhanced ALD process, reactions are initiated by using energy from a plasma. The plasma enhancement can take place during one of the precursor pulses, or after any of the precursor pulses (metal halide precursor and chalcogen source).
[0073] Suitable chalcogen sources are H.sub.2X, e.g. H.sub.2S, H.sub.2Se, H.sub.2Te, all gaseous at room temperature and also well known in semiconductor manufacturing. They are also commercially available.
[0074] Typical overall half-reaction schemes for ALD deposition of WX.sub.2, where X=S or Se or Te, are as follows:
a. 2*+H.sub.2X->XH+H
b. XH+WF.sub.6->XWF.sub.x+HF
with * denoting an active surface site and XH an XH group connected to a surface site.
HF is an extremely effective leaving group. As such, these precursors allow growth of very pure MX.sub.2 films without substantial contamination such as e.g. by carbon, which can be found when using metalorganic precursors. It is known that this ALD sequence has difficulties in nucleating on semiconductor material such as silicon or on a dielectric such as SiO.sub.2, and in the prior art the catalytic effect of DEZn (di-ethyl zinc) is used to solve that problem. This, however causes contamination of the MX.sub.2 layer by undesired co-deposition of Zn.
[0075] The inventors of the present invention have discovered that the undesired deposition of Zn when using Zn or Zn compounds as a catalyst can be avoided by further preparation of the surface, for example by deposition of a dielectric layer of material on the substrate, and/or by functionalizing the semiconductor or dielectric surface, e.g. pre-treating the semiconductor or dielectric surface with H.sub.2S, in other words by for instance sulfidizing the surface before applying ALD. At a temperature of about 500° C., this leads to a self-limiting reaction resulting in a mono-layer coverage of the Si surface with sulphur. Any suitable ALD technique may be applied. For instance thermal ALD, or plasma enhanced ALD (PEALD), in which the deposition is enforced by plasma (by applying plasma during a unit deposition cycle, for example, applying H.sub.2X plasma pulse or a mixture of H.sub.2X and H.sub.2 in a plasma pulse during the second pulse, or applying a H.sub.2 plasma pulse after or during the first pulse, the present invention not being limited thereto).
[0076] A method according to embodiments of the present invention may comprise removing the native oxide layer from the substrate before functionalization. Additionally or alternatively, the surface may include a dielectric layer, for example obtained by deposition via ALD, for example deposition of Si.sub.3N.sub.4, SiO.sub.2, of Al.sub.2O.sub.3, or otherwise providing a controlled oxidation of the surface (hence obtaining SiO.sub.2). The surface may be obtained according any suitable technique, the present invention not being limited thereto. The method may include functionalization of the dielectric surface, or directly PEALD.
[0077] Avoiding using Zn may be done by performing thermal ALD directly on a substrate comprising a sacrificial layer. For example, the sacrificial monolayer or monolayer stack may be obtained by deposition, for example semiconductor deposition, or deposition of a very thin sacrificial layer or monolayer stack of dielectrics such TiN. The thickness of the sacrificial layer, for example 2 monolayers or less, may be used to control the deposition (for example, control of the thickness of the ALD layer). Examples of semiconductor materials suitable for the thin sacrificial layer are Si, GaAs, Ge, or any other semiconductor, the present invention not being limited to these examples. The step of functionalization may be omitted in case of deposition of a thin sacrificial layer.
[0078]
[0079] In a second step 320, an MX.sub.2 layer is deposited on the surface using ALD deposition, for example using thermal ALD, or for example using plasma enhanced ALD in those embodiments not comprising deposition of a sacrificial layer. The number of ALD cycles to be carried out, or the number of sacrificial layers, depends on the number of ALD layers to be deposited, typically less than ten in the context of the present invention, where it is desired to obtain thin MX.sub.2 layers.
[0080] Optionally, a method according to embodiments of the present invention may comprise a further step 330, where the substrate surface is functionalized. Hereto, the substrate may for instance be sulphidized, i.e. the substrate surface is provided with an S-containing layer. Any suitable method to obtain this may be used. Typically a S-containing precursor such as H.sub.2S is used hereto. Alternatively, the substrate may be treated with ozone. Any suitable method to do this may be used.
[0081] In a first example, the substrate is a semiconductor substrate, such as for instance, but not limited thereto, a silicon substrate.
[0082]
[0083] In order to induce reduction of the hexavalent metal ion (M6+), three pathways can be followed:
(i) Electrons can be captured from an n-type doped semiconductor substrate, e.g. Si substrate, especially in the case where epitaxial seeding from a (111) substrate is used, hence after removal of native oxide. Especially since only very thin MX.sub.2 layers are needed (e.g. typically below 10 monolayers, e.g. up to 7 monolayers, preferably less than 5 monolayers), this is a viable approach.
(ii) By applying a H.sub.2 plasma, reactive H radicals can interact with a metal halide (e.g. MF.sub.6) in the chemistry as follows: MF.sub.6+H->MH.sub.5+HF; MF.sub.5+H->MH.sub.4+HF. In this way, H goes into a redox reaction with MF.sub.6 resulting in the formation of HF and the reduction of the M.sup.6+. In view of the low deposition temperature (e.g. less than 500° C.), it is unlikely that H.sub.2 can initiate similar reactions (due to the thermal stability of H.sub.2).
(iii) By adding a third reagent, i.e. Si.sub.2H.sub.6, which is a strong reducing agent, according to the overall reaction: WF.sub.6+Si.sub.2H.sub.6->W+2SiHF.sub.3+2H.sub.2. This reaction is the basis of W ALD such as used for deposition of W contacts and vias in mainstream Si CMOS technology. A detailed description of W ALd using WF.sub.6 and Si.sub.2H.sub.6 can be found in J. W. Elam, C. E Nelson, R. K. Grubbs and S. M. George, Kinetics of the WF.sub.6 and Si.sub.2H.sub.6 surface reactions during tungsten atomic layer deposition, Surface Science 479 (2001) 121-135. In this reaction, Si from the Si.sub.2H.sub.6 molecule reacts with WF.sub.6 to remove sequentially the F ions. Simultaneously, the H.sup.1− (hydride) ions from Si.sub.2H.sub.6 are converted to H.sup.0 in H.sub.2, which is the oxidation part of the redox system. In the case of embodiments of the present invention, however, different from the W ALD case, the reduction of WF.sub.6 to W is stopped at the intermediate state of W.sup.4+ due to the bonding with S at the stage of WS.sub.4, since WS.sub.4 is a more stable compound than W in these conditions. Due to the strong atomic Si—F bond, contamination by Si is not likely as SiHF.sub.3 is a volatile reaction by-product and will be exhausted readily. Similar reaction schemes can be thought of for the other transitions metals as well as for the Se case.
[0084] The reaction sequence then could look as follows:
1. Providing a substrate and a surface
2. Providing a sulphur surface layer from H.sub.2S treatment at appropriate temperature
3. Injecting consequentially WF.sub.6, Si.sub.2H.sub.6, and H.sub.2S in well-separated pulses including inert gas purges in between the pulses
[0085] An alternative initiation procedure for ALD nucleation is to functionalize the semiconductor surface, e.g. Si surface, after native oxide stripping and H.sub.2-bake for oxygen removal, by using O.sub.3. With this process, it is possible to activate a semiconductor, e.g. Si, surface after substantially complete native oxide removal and reconstruction in a H.sub.2 bake by depositing a monolayer of oxygen using O.sub.3 oxidation at low temperature, e.g. about 40-80° C. After this functionalization, it is possible to grow an epitaxial semiconductor, e.g. Si, layer on top of this oxygen monolayer, which indicates that the O layer does not hamper epitaxial seeding from the underlying substrate. Using this approach, the Si surface can be functionalized with —OH groups which is an ideal active site for further ALD growth of MX.sub.2 material. It is very likely that these OH groups allow further epitaxial line-up for MX.sub.2 to be grown on top of this, starting with the sulfur layer, with S replacing O.
[0086] This first half cycle then ends up in a Si—O—SH or Si—SH sequence, which then is the starting of the MX.sub.2 layer.
[0087] In order to control the desired planar orientation of the 2H basal plane of MX.sub.2, it is advantageous to induce epitaxial seeding. The trigonal unit cell parameter ‘a’ of MX.sub.2 (distance between two sulfur atoms, as shown in
[0088] An even more interesting surface for epitaxial seeding is an epitaxial layer of wurtzite AlN grown on (111) Si substrates in AlN[0 0 01]//Si[1 1 1] relationship. The unit cell parameter a for (0001) AlN is 3.1, which is even closer to the unit cell parameter a of MX2. Another good surface can be offered by 4H or 6H SiC, also epitaxially grown on (111) Si. The a constant of 4H or 6H SiC is 3.07. Moreover, AlN and SiC are very wide bandgap materials, offering substantial electrical isolation between the MX.sub.2 layer and the (111) Si substrate.
[0089] The resulting product of this process is a stack comprising a predefined number of layers of MX.sub.2, for example but not limited thereto WS.sub.2 or MoS.sub.2, whereas a covalent silicon sulfide type of bond is not desired. The enthalpy of formation ΔH.sub.f.sup.o of SiS.sub.2, WS.sub.2 and MoS.sub.2 is resp. −34.7, −46.3 and −61.2 kcal/mole, meaning that SiS.sub.2 is the least stable of these three materials. In view of this, it is not unlikely that the formed MX.sub.2 film can be detached from the Si surface, such as upon thermal annealing, and remains on the surface only by means of van der Waals forces.
[0090] In a second example, the substrate comprises a dielectric layer at the top. The substrate may for instance comprise a semiconductor layer with a dielectric such as Si.sub.3N.sub.4, or an oxide layer, e.g. SiO.sub.2, Al.sub.2O.sub.3, HfO.sub.3, ZrO.sub.2, or an epitaxially grown oxide on top thereof. In such case, the optional step of stripping the native oxide from the surface (described in the previous example, with reference to
[0091] A method 600 according to embodiments of the present invention is illustrated in
[0092] In a first step 610, a substrate having a dielectric top surface, e.g. by means of a dielectric layer at its top, is obtained. Such dielectric layer can be provided by deposition, or a dielectric layer can be grown atop a semiconductor layer. For instance a Si substrate can be oxidized such that a SiO.sub.2 layer atop the Si substrate is formed. Alternatively, the obtained substrate can simply be a completely dielectric surface.
[0093] In an optional second step 620, this dielectric substrate or top layer can be functionalized, for example sulphidized, for instance by replacing OH bonds by SH bonds. The sulphidizing step may for instance be carried out at a temperature between 300° C. and 500° C., during a time period between about 1 minute and about 1 hour. Alternatively, the optional functionalization may be performed with ozone. In some cases, a third reagent from the group of SiH.sub.4, Si.sub.3H.sub.8, Si.sub.2H.sub.6, B.sub.2H.sub.6, may be included, for example as part of a plasma mixture.
[0094] In a further step 630, a layer of MX.sub.2 is deposited on the optionally functionalized surface, using ALD deposition. The number of ALD cycles applied determines the thickness of the deposited MX.sub.2 layer, which may be limited in the context of the present invention, e.g. less than ten layers, for instance not more than seven layers, not more than five layers, e.g. only one or two layers.
[0095] The choice of the type of ALD is determined by the type of treatment performed on the substrate. For example, thermal ALD may be used after sulphidization or functionalization with ozone (for example, after sulphidization or functionalization with ozone of a semiconductor substrate, or after functionalization of a dielectric substrate layer with e.g. SiH.sub.4, Si.sub.2H.sub.6, Si.sub.3H.sub.8, B.sub.2H.sub.6 compounds).
[0096] Thermal ALD may comprise the unit cycle:
a) Metal halide precursor pulse
b) Purging with inert gas
c) H.sub.2X pulse (e.g. H.sub.2S pulse)
d) Purging with inert gas
[0097] This sequence is suitable after functionalization or after providing a sacrificial layer. The thickness of the sacrificial layer would determine the thickness of the deposited layer. In case no sacrificial layer is used, the cycle may be repeated a number of times, which would determine the size of the deposition layer. The deposition may be performed between e.g. 250 and 450° C.
[0098] The optional functionalization may also comprise SiH.sub.4, Si.sub.2H.sub.6, Si.sub.3H.sub.8, B.sub.2H.sub.6 compounds, in which case plasma can be advantageously used. In case the substrate is oxidized or otherwise covered by an oxide layer (e.g. by ALD), such as SiO.sub.2 or Al.sub.2O.sub.3, PEALD may advantageously be performed on the dielectric layer, due to the fact that PEALD promotes nucleation on dielectric layers. The H.sub.2(S) plasma may generate H atoms for the chemical reduction of M.sup.6+. If in the present example a dielectric layer of SiO.sub.2 is used, it can react with MF.sub.6, binding the F atoms into the volatile SiF.sub.4 or SiHF.sub.3, thusly initiating the nucleation on the inert dielectric. PEALD may be advantageously performed after functionalization comprising silicon-hydrogen compounds, but it may be performed after any other type of functionalization. PEALD may also be performed directly on the substrate, omitting the functionalization. PEALD can be applied following the unit cycle
a) Metal halide precursor pulse
b) Purging with inert gas
c) Plasma pulse comprising H.sub.2S, or mixture of H.sub.2 and H.sub.2X, or mixture of noble gasses with H.sub.2X
d) Purging with inert gas
[0099] The PEALD may also be performed according to complex unit cycles (or reaction cycles). Parameters like temperature, pulse time and purge times, number of cycles, and power of pulses may be optimized. Some examples of PEALD reaction cycles are: [0100] Metal halide and H.sub.2 plasma cyclically, followed by pulse of H.sub.2S. [0101] Metal halide precursor pulse, followed by cycles of H.sub.2 plasma and H.sub.2S [0102] Metal halide precursor pulse, followed by cycles of H.sub.2S and H.sub.2 plasma [0103] Cycles of metal halide and H.sub.2S, followed by a pulse of H.sub.2 plasma [0104] Cycles of metal halide and H.sub.2 plasma, followed by cycles of H.sub.2S and H.sub.2 plasma
Purging can be done after or during a reaction cycle.
[0105] In a third example, the obtained substrate may include a sacrificial layer on the surface, for instance a semiconductive layer such as a Si layer, or a TiN layer. ALD deposition of an MX.sub.2 layer may be performed on such substrate. In this example, the functionalization may be omitted and the ALD may be directly performed after obtaining the substrate, obtaining a wide deposition area and saving time.
[0106] The initial substrate may comprise a multi-layer structure, for example a semiconductor layer coated with a protective dielectric layer. The dielectric layer may be obtained, e.g. deposited, after removing native oxide, for example via H.sub.2 plasma. The dielectric layer may comprise for example Si.sub.3N.sub.4, or crystalline Al.sub.2O.sub.3, or SiO.sub.2 obtained by deposition or by oxidation of the substrate (in case of oxidation, the removal of native oxide may be omitted). The dielectric layer is in turn covered by a thin sacrificial monolayer or monolayer stack. In this example, a layer of semiconductor such as Si, Ge, GaAs, or others is applied. In the present case, the sacrificial layer can be obtained by deposition, for example by Molecular Beam Epitaxial (MBE) deposition. The thin layer shall ideally comprise one or two monolayers, which could be further protected by addition of a H-passivation layer. The thin layer, for instance thin Si layer, acts as a solid state reagent during thermal ALD, hence the thickness of the thin layer may be used to control the thickness of the dichalchogenide layer, as the amount of material in the thin layer, e.g. Si, controls the progress of the MF.sub.6 reaction. Simultaneously, H.sub.2X will interact so as to bind with the released M.sup.4+ and stabilize it as MX.sub.2: MF.sub.6+Si+H.sub.2X->MX.sub.2+SiF.sub.4+2 HF. The compound SiHF.sub.3 may also form in the reaction. In this scheme, the thin layer, in the embodiment explained Si layer, can be seen as a sacrificial layer or as a solid state redox reagent. The ALD sequence in case of the sacrificial Si layer may be a thermal ALD as previously explained, optionally further comprising starting with one or more H.sub.2X pulses such that H.sub.2S is present abundantly when MF.sub.6 will attack Si. Nonetheless, the present invention is not limited to a sacrificial layer comprising semiconductor, and the method can be broadened to other materials such as e.g. TiN.
[0107] In a second aspect, the present invention provides a method of producing at least two transition metal dichalcogenide materials on a substrate. The method comprises the steps of:
1) providing a first metal dichalcogenide material on the substrate using a method of any embodiments of the first aspect of the present invention, thereby using a first metal halide precursor and a first chalcogenide precursor; and
2) providing a second metal dichalcogenide material on the substrate by using ALD deposition, starting from a second metal halide precursor and a second chalcogen source,
wherein the first metal halide precursor is different from the second metal halide precursor and/or the first chalcogen source is different from the second chalcogen source.
[0108] In embodiments of the present invention, the first and second metals and chalcogenides may be mixed inside the monolayer itself, such as for instance by forming a layer of Mo.sub.(1-x)W.sub.xS.sub.2(1-y)Se.sub.2y.
[0109] In alternative embodiments of the present invention, heterogeneous combinations of homogeneous monolayers, e.g. MoS.sub.2 on top of WSe.sub.2 may be made. Using multiple metal and/or chalcogenide precursors for the first resp. second layer, e.g. MoF.sub.6 and H.sub.2S for the first layer, and WF.sub.6 and H.sub.2Se for the second layer, or vice versa, allows to make a stack comprising mixtures of metal dichalcogenides, e.g. MoS.sub.2/WS.sub.2, in a predefined ratio. For example: [0110] a single MoS.sub.2 monolayer in combination with a single WS.sub.2 monolayer, or [0111] a single MoS.sub.2 monolayer in combination with a double WS.sub.2 monolayer, or [0112] a double MoS.sub.2 monolayer in combination with a single WS.sub.2 monolayer, or [0113] a double MoS.sub.2 monolayer in combination with a double WS.sub.2 monolayer.
[0114] In general, it is possible to deposit a first layer consisting of a first predefined number N1 of first monolayers (where N1 is an integer value in the range of 1 to 5, and to deposit a second layer consisting of a second predefined number N2 of second monolayers (where N2 is an integer in the range of 1 to 5. Moreover, the stack of all monolayers may be arranged as a lower part of the N1 first monolayers and an upper part of the N2 second monolayers, or as interleaved, e.g. alternating, first and second layers.
[0115] As another example, when using MoF.sub.6 and H.sub.2S for depositing the first layer, and MoF.sub.6 and H.sub.2Se for the second layer, or vice versa, one can make a mixed channel layer MoS.sub.2/MoSe.sub.2, in well-controlled ratios, e.g. predefined ratios. Such a method allows to make semiconductor structures with channels made of different materials in predefined ratios. This allows bandgap engineering of the deposited materials.
[0116] It is possible to use any suitable method according to the present invention, for example depositing a protective dielectric layer, a thin sacrificial layer and, via ALD, depositing a first dichalcogenide layer or monolayer stack, then depositing a second thin sacrificial layer and, via ALD, depositing a second dichalcogenide layer or monolayer stack. It is also possible to use functionalization, or deposition of dielectrics and functionalization, followed by ALD, for example PEALD or thermal ALD, or a combination of deposition techniques.
Summary:
[0117] MX.sub.2 films of monolayer thickness (less than 1.0 nm) can be deposited by means of ALD starting from MF.sub.6 and H.sub.2X precursors. ALD allows to deposit layers of monolayer thickness with extremely good uniformity, for instance with a standard deviation less than 1% within 1 sigma, at deposition temperatures of 250-450° C., even on large area substrates (e.g. up to 300-450 mm silicon wafers). The layer thickness can be controlled to be a predefined number of monolayers (e.g. only one, or only two). The procedure may be performed by preparing the surface layer of the substrate and performing ALD. The preparation may comprise covering the surface with dielectric, for example comprising SiO.sub.2, Al.sub.2O.sub.3, Si.sub.3N.sub.4, a sacrificial layer of TiN, a sacrificial layer of a semiconductor such Si, Ge, GaAs, or others, for instance one or two layers of Si. The preparation may also comprise removing the native oxide from the substrate. After removing the native oxide, (111) oriented substrates, or an epitaxial layer of wurtzite AlN grown on (111) oriented substrates in AlN[0 0 01]//Si[1 1 1] relationship, or 4H or 6H SiC, also epitaxially grown on a (111) substrate allow to control the orientation of the MX.sub.2 by epitaxial seeding with the basal plane being substantially parallel to the surface. The semiconductor surface can be pre-functionalized, e.g. pre-sulphidized by annealing the substrate, either after deposition of the protective layer, or after native oxide removal, in H.sub.2S at T of about 400° C. The reduction of the W.sup.6+ precursor can follow a few different pathways: i) by uptake of electrons from an n-type doped Si substrate; ii) by applying a H.sub.2 plasma such that active H radicals can interact in the chemistry and reduce the W.sup.6+, or iii) by addition of Si.sub.2H.sub.6 as a strong reducing agent. This avoids the need for a catalyst during the ALD initiation and hence helps preserving a high purity film, e.g. having Zn and C impurities below 1e18/cm.sup.3. ALD may also be directly performed on the sacrificial layer, whose thickness may control the reaction and formation of the TMD layers. In case a semiconductor is used as sacrificial layer, the functionalization step may be omitted before thermal ALD. Using multiple metal and/or chalcogenide precursors, e.g. Mo and W, S and Se, allows to make mixtures of metal dichalcogenides (e.g. MoS.sub.2/WS.sub.2, or MoS.sub.2/MoSe.sub.2) in well-controlled ratios, for example 50% MoS.sub.2 and 50% WS.sub.2, or 1/3 MoS.sub.2 and 2/3 WS.sub.2 or any other ratio N/M. This allows bandgap engineering of the deposited materials.
Applications:
[0118] A method according to embodiments of the present invention allows to produce semiconductor devices with extremely small dimensions. Such devices are particularly suited for continued scaling beyond Si CMOS technology nodes (e.g. beyond the 12 nm technology node). The stack of monolayers of MX.sub.2 materials may e.g. be used as alternative transistor channel material for regular MOSFET devices in low-power CMOS, or as material for heterostructures such as used in tunneling devices (TFET), or as material for spintronics. Such devices may have in particular the following advantages: [0119] high I.sub.ON/I.sub.OFF ratio, providing low power consumption in the OFF-state, [0120] low subtreshold voltage swing, hence suitable for low voltage operation, [0121] lower dielectric constant than Silicon resulting in a smaller characteristic length, and therefore no short channel effects expected at small gate lengths, [0122] low dimensional material (thickness of 1 monolayer of about 0.68 nm), hence ultra-thin body, [0123] MoS.sub.2 layers (basal planes) are believed to be chemically inert due to the sulfur termination. In contrast, the edges of patterned MX.sub.2 are highly active due to the dangling bonds at these edges;
[0124] The method described above may also be particularly suited for producing optoelectronic devices requiring transparent semiconductors. Transparent material allows use as driving circuits for OLEDs, or as tunable band gap (e.g. by alloys) enables LED.
[0125] The method described above may also be particularly suited for producing electronics on flexible substrates, e.g. wearable electronics, e-newspaper, etc.
[0126] The method described above may also be particularly suited for producing gas sensing devices because they exhibit a highly selective response to electron donors (higher selectivity than CNT sensors), and have quick response times.