Abstract
The present invention describes essentially three different embodiments for the implementation of low impedance (over frequency) power delivery to a die. Such low impedance to a high frequency allows the die to operate at package-level speed, thus reducing yield loss at the packaging level. Each embodiment addresses a slightly different aspect of the overall wafer probe application. In each embodiment, however, the critical improvement of this disclosure is the location of the passive components used for supply filtering/decoupling relative to prior art. All three embodiments require a method to embed the passive components in close proximity to the pitch translation substrate or physically in the pitch translation substrate.
Claims
1. An Improved Power Supply Transient Performance (power integrity) structure for a Probe Card Assembly in an Integrated Circuit Test Environment, comprising: a thin pitch translator substrate; passive components are located within an interposer that also acts as an attach mechanism between the pitch translation substrate and the probe card so that the passive components are in close proximity to said pitch translation substrate so that low impedance to a high frequency permits a die to operate at package-level speed, thereby reducing yield loss at a packaging level.
2. The structure according to claim 1 where said passive components are capacitors.
3. The structure according to claim 1 wherein said pitch translation substrate is a glass or silicon based pitch translator substrate, based on a “TSV”, “TGV” or like technology.
4. The structure according to claim 1 wherein said thin substrate 1 is 50 to 100 micrometer thick.
5. The structure according to claim 1 wherein said passive elements on the interposer are close to the probe card and are approximately 200-300 micro meters distance from the probe card.
6. The structure according to claim 1 wherein said pitch translation substrate is replaceable.
7. The structure according to claim 1 wherein said pitch translation substrate is soldered to said passive component interposer.
8. The structure according to claim 1 wherein said entire structure is soldered to the probe card thereby enhancing reliability of said structure.
9. The structure according to claim 1 wherein said passive electrical components, such as discrete capacitors, may be placed significantly closer to a die under test through a method of embedding and thus shortening the physical distance between the passive components and a die under test.
10. The structure according to claim 1, wherein said structure improves power supply filtering and decoupling, such that the die under test may operate at faster speeds, including package-level speeds.
11. The structure according to claim 1 wherein said substrate is an extremely thin pitch translation substrate connected to said passive decoupling components and reduces electrical length/delay in the supply path.
12. The structure according to claim 1 wherein a fan-out routing of the signals extends to a periphery of the pitch translation substrate for the purposes of prioritizing on power and ground routing directly above the die.
13. The structure according to claim 12 wherein a supply loop impedance is reduced, such that the die may operate at faster speeds, including package-level speeds.
14. The structure according to claim 1 wherein said structure allows a die to be tested with performance criteria consistent with “Known Good Die” testing and thus allowing performance level testing close to die to die interconnects in multi-die packages.
15. The structure according to claim 1 wherein wear items in a probe test environment can be interchanged rapidly, with minimal cost, and with no impact on embedded components
16. (canceled)
17. The structure according to claim 1 wherein said passive components are attached to the top of the pitch translation substrate by soldering with solder and copper pillars said passive components to the top of the substrate.
18. The structure according to claim 1 wherein said passive components are attached to the top of the pitch translation substrate by thermal sonic bonding.
19. The structure according to claim 1 wherein said entire structure is soldered to the probe card thereby enhancing reliability of said structure.
20. An Improved Power Supply Transient Performance (power integrity) structure for a Probe Card Assembly in an Integrated Circuit Test Environment, comprising a thin pitch translator substrate formed of thin build-up layers; passive components embedded directly into the pitch translation substrate pitch translation substrate, said substrate being compatible with said components embedding and further comprising thin redistribution layers built-up between said passive components and a lower or bottom surface of said pitch translation substrate, said thin layers providing a closest possible location of said passive embedded components to a wafer/die so that the passive components are in close proximity to said pitch translation substrate so that low impedance to a high frequency permits a die to operate at package-level speed, thereby reducing yield loss at a packaging level.
21. The structure according to claim 20 wherein the pitch translation substrate is compatible with component embedding and that thin redistribution layers be built-up between the components and a lower or bottom surface of the pitch translation substrate.
22. The structure according to claim 21 wherein routing method shown in a center portion, directly above a die, of the pitch translation substrate prioritizes on power and ground routing.
23. A method for improving a Power Supply Transient Performance (power integrity) structure for a Probe Card Assembly in an Integrated Circuit Test Environment, the steps comprising: Providing a thin pitch translator substrate; and Locating passive components within an interposer that also acts as an attach mechanism between the pitch translation substrate and the probe card so that the passive components are in close proximity to said pitch translation substrate so that low impedance to a high frequency permits a die to operate at package-level speed, thereby reducing yield loss at a packaging level.
24. A method for improving a Power Supply Transient Performance (power integrity) structure for a Probe Card Assembly in an Integrated Circuit Test Environment, the steps comprising Fully embedding a structure including passive components directly to a pitch translation substrate formed of thin build-up layers, so that the passive components are in close proximity to said pitch translation substrate so that low impedance to a high frequency permits a die to operate at package-level speed, thereby reducing yield loss at a packaging level.
Description
BRIEF DESCRIPTION OF DRAWINGS
[0028] FIG. 1-4 basically describe a first embodiment of the present invention showing a structure which embeds the decoupling components and planes in a interposer structure that also acts as an attach mechanism between the pitch translation substrate and the probe card wherein:
[0029] FIG. 1 is partially exploded sectional view of a first embodiment of the present invention in which the present invention is shown as a structure which embeds the decoupling components and planes in a interposer structure that also acts as an attach mechanism between the pitch translation substrate and the probe card;
[0030] FIG. 2 is a fully assembled sectional view of the first embodiment of the present invention as shown in FIG. 1;
[0031] FIG. 3 is a similar embodiment of the present invention as shown in FIGS. 1 and 2 in which the pitch translation substrate is soldered to the interposer structure for the decoupling components and planes;
[0032] FIG. 4 is a similar embodiment of the present invention as shown in FIG. 3 except that the pitch translation substrate is soldered to the probe card;
[0033] FIGS. 5-7 illustrate basically a second embodiment of the present invention in which a structure is provided for decoupling components to directly attach to the upper surface pitch translation substrate in which:
[0034] FIG. 5 is partially exploded sectional view of a second embodiment of the present invention in which the present invention is shown as a structure for decoupling components to directly attach top the upper surface pitch translation substrate;
[0035] FIG. 6 is a fully assembled view of the second embodiment shown in FIG. 5;
[0036] FIG. 7 is a similar embodiment of the present invention as shown in FIGS. 5 and 6 except that the pitch translation substrate is soldered to the probe card;
[0037] FIGS. 8-10 illustrate basically a third embodiment of the present invention in which the decoupling components are fully embedded directly to the pitch translation substrate directly beneath thin electrical signal redistribution layers, in which:
[0038] FIG. 8 is partially exploded sectional view of a third embodiment of the present invention in which the present invention is shown as a structure in which the decoupling components are fully embedded directly to the pitch translation substrate directly beneath thin electrical signal redistribution layers,
[0039] FIG. 9 is a fully assembled sectional view of the third embodiment shown in FIG. 8,
[0040] FIG. 10 is a similar embodiment of the present invention as shown in FIGS. 8 and 9 except that the pitch translation substrate is soldered to the probe card;
[0041] FIG. 11 is a sectional view of a prior art structure;
[0042] FIG. 12 is a graph showing a supply loop impedance in frequency domain for the first embodiment (FIGS. 1-4) and the third embodiment (FIGS. 8-10) compared with the prior art structure of FIG. 11:
[0043] FIG. 13 is an illustration of a simple pattern data eye @ 667 Mb/s for the third embodiment (FIGS. 8-10; A) compared to the prior Art (FIG. 1; B)
[0044] FIG. 14: is an illustration of a simple pattern data eye @ 1 Gb/s of the third Embodiment (A) (FIGS. 8-10) Compared to Prior Art (B) (FIG. 11)
[0045] FIG. 15 is an illustration of a simple pattern data eye @ 2 GB/s Third embodiment (A) (FIGS. 8 10) compared to Prior Art (B) (FIG. 11)
[0046] FIG. 16: illustrates Voltage vs. time domain clock pattern for Third embodiment (A) (FIGS. 8-10) compared to Prior Art (B) (FIG. 11)
[0047] FIG. 17: is a top View showing Routing for Signals Relative to Capacitor Location on the Pitch Translation Substrate and/or the embedded component Interposer for all the embodiments of the present invention;
[0048] FIG. 18 is an expanded view of the pitch translation substrate of FIG. 1:
[0049] FIG. 19 is an expanded view of the pitch translation substrate of FIG. 5; and
[0050] FIG. 20 is an expanded view of the pitch translation substrate of FIG. 8;
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0051] The element numbers of the various embodiments in the FIGS. of the drawings, FIGS. 1-20, are as follows:
FIG. 1: Break-Out Cross-Sectional Diagram of First Embodiment with Compliant Interconnect [0052] 1. Probe Card Printed Circuit Board (PCB) [0053] 2. Wafer to be probed with individual die [0054] 3. Supporting probe Chuck [0055] 4. Probe housing [0056] 5. Probe mechanism [0057] 6. PCB to ECI Compliant Interconnect [0058] 7. Compression stop housing for #6 [0059] 8. Embedded component, passive [0060] 9. Embedded Component Interposer (ECI) Substrate [0061] 10. ECI to PTS Compliant Interconnect [0062] 11. Compression stop housing for #10 [0063] 12. Pitch Translation Substrate (PTS) with through “glass” or “silicon” vias [0064] 13. Embedded Component Interposer Assembly, consisting of #6-#11 [0065] 14. EC/PTS Assembly, replacing prior art (e.g. MLO, MLC) [0066] 15. Probe Head Assembly
FIG. 2: First embodiment (FIG. 1) Shown Assembled and Probing a Die [0067] 16. Probe Card Printed Circuit Board (PCB) (Same as FIG. 1.1) [0068] 17. Wafer to be probed with individual die (Same as FIG. 1.2) [0069] 18. Supporting probe Chuck (Same as FIG. 1.3) [0070] 19. ECI/PTS Assembly, replacing prior art (e.g. MLO, MLC) (Same as FIG. 1.14) [0071] 20. Probe Head Assembly (Same as FIG. 1.15)
FIG. 3: Minor Deviation 1 to First Embodiment: Use of Permanent Electrical Interconnect Between PTS to the ECI
[0072] 21. Probe Card Printed Circuit Board (PCB) (Same as FIG. 1.1) [0073] 22. Wafer to be probed with individual die (Same as FIG. 1.2) [0074] 23. Supporting probe Chuck (Same as FIG. 1.3) [0075] 24. ECI/PTS Assembly, replacing prior art (e.g. MLO, MLC) (Similar to FIG. 1.14, but items 10, 11 have been replaced with a permanent interconnect) [0076] 25. Probe Head Assembly (Same as FIG. 1.15) [0077] 26. Permanent Conductive Interconnect Mechanism (Solder, Copper pillar) between the ECI and the PTS
FIG. 4: Minor Deviation 2 to First Embodiment: Use of Permanent Electrical Interconnect Between the PTS ECI Assembly and the Probe Card
[0078] 27. Probe Card Printed Circuit Board (PCB) (Same as FIG. 1.1) [0079] 28. Wafer to be probed with individual die (Same as FIG. 1.2) [0080] 29. Supporting probe Chuck (Same as FIG. 1.3) [0081] 30. ECI/PTS Assembly, replacing prior art (e.g. MLO, MLC) (Similar to FIG. 1.14, but items 6, 7 and 10, 11 have been replaced with a permanent interconnect) [0082] 31. Probe Head Assembly (Same as FIG. 1.15) [0083] 32. Permanent Conductive Interconnect Mechanism (Solder. Copper pillar) between the ECI and the PTS [0084] 33. Permanent Conductive Interconnect Mechanism (Solder, Copper pillar) between the ECI/PTS assembly and the probe card
FIG. For Second Embodiment:
[0085] FIGS. 5-7 describe two minor deviations using cross-sectional views of the improved method for signal loading and power supply delivery using the second major embodiment: a glass or silicon based pitch translator substrate (PTS), based on a “TSV”, “TGV”, or like technology with passive components mounted directly onto the pitch translator. The components may be in either a die or packaged form. A stiffening element with electrical conductivity paths permanently attached to the pitch translator substrate for mechanical strengthening, better durability, and coarse pitch translation, as required. FIG. 5 describes the individual component pieces. FIG. 6 shows FIG. 5 assembled in “mission mode”. FIG. 7 describe a minor deviation, where by the compliant interconnect has been replaced by a more permanent connection of any form but commonly solder and copper pillar.
[0086] In FIG. 5, labels 34-38, 46 describe necessary functional items associated with the disclosure but specifically included in the disclosure. These items are shown because they are necessary to describe both function and improvements over prior art.
FIG. 5: Cross-Sectional Breakout Diagram for Embodiment #2: Embedded Decoupling Components Attached to the PTS with a Supporting Stiffener and Using Compliant Electrical Interconnect [0087] 34. Probe Card Printed Circuit Board (PCB) [0088] 35. Wafer to be probed with individual die [0089] 36. Supporting probe Chuck [0090] 37. Probe housing [0091] 38. Probe mechanism [0092] 39. PCB to PTS Compliant Interconnect [0093] 40. Compression stop housing for #39 [0094] 41. Embedded component, passive, and cavity [0095] 42. Permanent conductive attach mechanism between the PTS and the stiffening element [0096] 43. Stiffening Element with conductive paths for coarse pitch translation [0097] 44. Pitch Translation Substrate (PTS) with through “glass” or “silicon” vias or like technology [0098] 45. Embedded Component Pitch Translator Assembly, consisting of #39-#44 [0099] 46. Probe Head Assembly
FIG. 6: Second Embodiment (FIG. 5) Shown Assembled and Probing a Die
[0100] 47. Probe Card Printed Circuit Board (PCB) (Same as FIG. 5.34) [0101] 48. Wafer to be probed with individual die (Same as FIG. 5.35) [0102] 49. Supporting probe Chuck (Same as FIG. 5.36) [0103] 50. ECI/PTS Assembly, replacing prior art (e.g. MLO, MLC) (Same as FIG. 5.45) [0104] 51. Probe Head Assembly (Same as FIG. 5.46)
FIG. 7: Minor Deviation for Second Embodiment: Use of Permanent Electrical Interconnects Between the Adjoining Stiffener to the Probe Card
[0105] 52. Probe Card Printed Circuit Board (PCB) (Same as FIG. 5.34) [0106] 53. Wafer to be probed with individual die (Same as FIG. 5.35) [0107] 54. Supporting probe Chuck (Same as FIG. 5.36) [0108] 55. ECI/PTS Assembly, replacing prior art (e.g. MLO, MLC) (Similar to FIG. 5.45, except that compliant elements #39 and #40 have been replaced with a permanent attach mechanism) [0109] 56. Probe Head Assembly (Same as FIG. 5.46) [0110] 57. Permanent attach mechanism between the embedded component/pitch translator substrate assembly and the probe card.
FIG. For Third Embodiment:
[0111] FIGS. #8-#10 describe two minor deviations using cross-sectional views of the improved method for signal loading and power supply delivery using the third major embodiment: a pitch translation substrate with passive electrical component embedded directly above the test die of interest. FIG. #8 describes the individual component pieces. FIG. #9 shows FIG. #8 assembled in “mission mode”. FIG. #10 describes a minor deviation, where by the compliant interconnect has been replaced by a more permanent connection of any form but commonly solder and copper pillar.
[0112] In FIG. #8, labels 58-62, 68 describe necessary functional items associated with the disclosure but specifically included in the disclosure. These items are shown because they are necessary to describe both function and improvements over prior art.
FIG. 8: Sectional Breakout Drawing for Third Embodiment: Passive Components Embedded Directly into the Pitch Translation Substrate Using Compliant Electrical Interconnects [0113] 58. Probe Card Printed Circuit Board (PCB) [0114] 59. Wafer to be probed with individual die [0115] 60. Supporting probe Chuck [0116] 61. Probe housing [0117] 62. Probe mechanism [0118] 63. PCB to ECI Compliant Interconnect [0119] 64. Compression stop housing for #63 [0120] 65. Embedded component, passive [0121] 66. Pitch Translation Substrate (PTS) with integrated Embedded Components [0122] 67. PITS Assembly [0123] 68. Probe head Assembly
FIG. 9: Third Embodiment Shown Assembled (FIG. 8) and Probing a Die
[0124] 69. Probe Card Printed Circuit Board (PCB) (Same as FIG. 8.58) [0125] 70. Wafer to be probed with individual die (Same as FIG. 8.59) [0126] 71. Supporting probe Chuck (Same as FIG. 8.60) [0127] 72. Pitch Translation Substrate (Same as FIG. 8.67) [0128] 73. Probe Housing (Same as FIG. 8.68)
FIG. 10: Minor Deviation to Third Embodiment: Use of Permanent Electrical Interconnects Between the PTS and the Probe Card
[0129] 74. Probe Card Printed Circuit Board (PCB) (Same as FIG. 8.58) [0130] 75. Wafer to be probed with individual die (Same as FIG. 8.59) [0131] 76. Supporting probe Chuck (Same as FIG. 8.60) [0132] 77. Pitch Translation Substrate (Similar to FIG. 8.67 but modified for a permanent attach) [0133] 78. Probe Housing (Same as FIG. 8.68) [0134] 79. Permanent Attach Mechanism
FIG. 11: Prior Art Description
[0135] 80. Probe Card Printed Circuit Board (PCB) [0136] 81. Pitch Translation Substrate [0137] 82. Permanent Attach mechanism [0138] 83. Probe Housing and probes [0139] 84. Wafer to be probed with individual die [0140] 85. Supporting probe Chuck [0141] 86. Solder Mount Passive Components
[0142] FIGS. 12-16 shows performance comparisons between prior art and the disclosed embodiments. In FIGS. 12-16, the “A” side shows the improved performance of the disclosure; the “B” side show the performance of prior art.
FIG. 12: The Supply Loop Impedance in Frequency Domain for First Embodiment (A) and Third Embodiment (A) Compared to Prior Art (B).
FIG. 13: A Simple Pattern Data Eye @ 667 Mb/s; Third Embodiment (A) Compared to Prior Art (B)
FIG. 14: A Simple Pattern Data Eye @ 1 Gb/s; Third Embodiment (A) Compared to Prior Art (B)
FIG. 15: A Simple Pattern Data Eye @ 2 GB/s; Third Embodiment (A) Compared to Prior Art (B)
[0143] FIG. 16: Voltage Vs. Time Domain Clock Pattern for Third Embodiment (A) Compared to Prior Art (B).
FIG. 17: Top-Down View Showing Routing for Signals Relative to Capacitor Location on the Pitch Translation Substrate and/or the Embedded Component Interposer [0144] 87. Location of the Die beneath the Pitch Translation Substrate (PTS) [0145] 88. Location of the Passive Components (e.g. decoupling capacitors) directly above the die in the ECI (Embodiment #1) or PTS [0146] 89. Fine pitch via ring: 50 um to 10 um pitch vias, commonly known “through silicon vias” (TSV) or “through glass vias” (TGV) [0147] 90. Signal Routing from the Die to the fine pitch via ring [89] on redistribution layers closest to die [87] [0148] 91. Signal Routing from the fine pitch via ring [89] to the interface pads [92] on redistribution layers opposite the die [0149] 92. Interface pads to the probed card through a permanent or complaint interconnect [0150] 93. Pitch translation Substrate
FIG. 18: Cut Away View of the Modified Pitch Translation Substrate for Embodiment #1
[0151] 94. Upper redistribution layers (opposite of die) for fan-out from the TSV/TGV to the interface pad to the ECI and probe card [0152] 95. Though via section of the pitch translation substrate [0153] 96. Lower redistribution layers (closest to the die) for fan-out from the die pads to the TSV/TGV [0154] 97. Die pads for interface the probes [0155] 98. “Keep-out” region for signal routing. This area in both redistribution regions and the TSV/TGV region is dedicated to supply and ground routing as much as possible. [0156] 99. Embedded component interposer (See FIG. #1), shown here to communicate that the embedded components are not integrated into the pitch translation substrate [0157] 100. Routing regions for signals. These regions are outside of the die area to allow room for the passive component routing directly above the die.
FIG. 19: Cut Away View of the Modified Pitch Translation Substrate for Embodiment #2
[0158] 101. Upper redistribution layers (opposite of die) for fan-out from the TSV/TGV to the interface pad to the ECI and probe card [0159] 102. Though via section of the pitch translation substrate [0160] 103. Lower redistribution layers (closest to the die) for fan-out from the die pads to the TSV/TGV [0161] 104. Die pads for interface the probes [0162] 105. “Keep-out” region for signal muting. This area in both redistribution regions and the TSV/TGV region is dedicated to supply and ground routing as much as possible. [0163] 106. Embedded components mounted on the pitch translation substrate (See FIG. #5). [0164] 107. Routing regions for signals. These regions are outside of the die area to allow room for the passive component routing directly above the die.
FIG. 20: Cut Away View of the Modified Pitch Translation Substrate for Embodiment #3
[0165] 108. Though via section of the pitch translation substrate [0166] 109. Lower redistribution layers (closest to the die) for fan-out from the die pads to the TSV/TGV [0167] 110. Die pads for interface the probes [0168] 111. “Keep-out” region for signal routing. This area in both redistribution regions and the TSV/TGV region is dedicated to supply and ground routing as much as possible. [0169] 112. Embedded components mounted on the pitch translation substrate (See FIG. #5). [0170] 113. Routing regions for signals. These regions are outside of the die area to allow room for the passive component routing directly above the die.
[0171] The present invention provides for basically three embodiments with some variations or modifications for an improved pitch translation substrate and for locating or embedding passive components closer to the pitch translation substrate. Each embodiment addresses a slightly different aspect of the overall wafer probe application. For each embodiment, however, the critical improvement of this disclosure is the location of the passive components used for supply filtering/decoupling relative to the prior art. All three basic embodiments of the present invention require embedding the passive components in either close proximity to the pitch translation substrate or physically within the pitch translation substrate. In this way the present invention provides a structure whereon passive electrical components, such as discrete capacitors, can be placed significantly closer to a die under test by embedding and thus shortening the physical distance between the passive components and the die under test. The present invention provides various embodiments for implementing such embedded structures and methodology.
[0172] Referring to the drawings of FIGS. 1-20, FIGS. 1-4 describes basically a first embodiment of the present invention in which the decoupling components and planes are embedded in a interposer structure that also acts as an attach mechanism between the pitch translation substrate and the probe card. This first embodiment has the benefit of inter-changeability, as the pitch translation substrate can be a wear item in high volume testing. While better than prior art, some performance degradation occurs relative to other embodiments. This first embodiment may work with any form of pitch translation substrate. However, the short electrical lengths of glass and silicon substrates give the greatest benefit.
[0173] FIGS. 1-4 basically describe a first embodiment of the present invention with three minor deviations using sectional views of the improved method for signal loading and power supply delivery using the first major implementation: a discrete interposer with embedded components (passive) attached to a glass or silicon based pitch translator substrate, based on a “TSV”, “TGV” or like technology. (TSV=through silicon via, TGV=through glass via). FIG. 1 describes the individual component pieces. FIG. 2 shows FIG. 1 assembled in “mission mode”. FIGS. 3 and 4 describe a minor deviation, whereby the compliant interconnect has been replaced by a more permanent connection of any form but commonly solder and copper pillar. In the embodiment of FIG. 1 there are two essential differences over the prior art of FIG. 11. First instead of the traditional pitch translation substrate of FIG. 11, the embodiment of FIG. 1 has a new pitch translation substrate 12 much thinner in width than the prior art substrate of FIG. 11 The new thinner substrate 12 if FIG. 1 is 50 to 100 micrometers thick compared to the 1 to 2 millimeters in thickness of the prior art substrate of FIG. 1
[0174] Second in the embodiment of FIG. 1 the capacitance 8 or passive components 8 are located in an interposer 9. Thus because of the thinner substrate 12 and the location of the capacitance or passive elements 8 on the interposer 9 the capacitance 8 are much closer to the probe card than the prior art structure of FIG. 11 and are 200-300 micro meters distance from the probe card compared with of 44 mm or 4.5 mm to 9 mm distance of the prior art structure of FIG. 11. Thus the structure of this first embodiment improves power supply filtering and decoupling, such that the die under test may operate at faster speeds, including package-level speeds. This structure has an extremely thin pitch translation substrate connects to passive decoupling components and reduces electrical length/delay in the supply path. In this structure the fan-out routing of the signals extends to the periphery of the pitch translation substrate for the purposes of prioritizing on power and ground routing directly above the die. Further in this structure the supply loop impedance is reduced such that the die may operate at faster speeds including package-level speeds. This structure allows a die to be tested with performance criteria consistent with “Known Good Die” testing and thus allowing performance level testing close to die to die interconnects in multi-die packages.
[0175] Another advantage of the novel structure of the embodiment of FIG. 1 is that substrate 12 is a wear item and is replaceable while the prior art substrate of FIG. 11 is not replaceable. FIG. 2 is the same embodiment of FIG. 1 in fully assembled form.
[0176] FIG. 3 is similar to the embodiment of FIGS. 1 and 2 except that the pitch translation substrate 12 is soldered to the passive component interposer 9. The entire circuitry is soldered together. The embodiment of FIG. 3 is more economical as it is there is no need to add in any complaint interconnects.
[0177] FIG. 4 is a similar embodiment to that of FIG. 3 except in FIG. 3 the circuit structure can be removed from the probe card and replaced. In FIG. 4 embodiment the entire circuit structure is soldered to the probe card 21. This makes this embodiment more reliable.
[0178] A second basic embodiment of the present invention is illustrated in FIGS. 5-7. Two minor deviations using sectional views of the improved method for signal loading and power supply delivery using the second major embodiment: a glass or silicon based pitch translator substrate (PTS), based on a “TSV”, “TGV”, or like technology with passive components mounted directly onto the pitch translator. The components may be in either a die or packaged form. A stiffening element with electrical conductivity paths permanently attached to the pitch translator substrate for mechanical strengthening, better durability, and coarse pitch translation, as required. FIG. 5 describes the individual component pieces. FIG. 6 shows FIG. 5 assembled in “mission mode”, FIG. 7 describe a minor deviation, where by the compliant interconnect has been replaced by a more permanent connection of any form but commonly solder and copper pillar.
[0179] In FIG. 5 labels 34-38, 46 describe necessary functional items associated with the present invention but specifically included in the disclosure. These items are shown because they are necessary to describe both function and improvements over prior art.
[0180] FIG. 5 shows a partially exploded sectional view of a second embodiment of the present invention of a structure for decoupling passive components 41 such as capacitors 41 to directly attach on top the upper surface pitch translation substrate 44 this eliminates the need for an interposer as used in the embodiment of FIGS. 1-4 of the present invention. The passive components can be attached to the top of the pitch translation substrate 44 by one of two methods. The first method is by soldering the components to the top of the substrate. The second is by thermal sonic bonding which is a known technique in the art. And which heats up capacitors so that it spot welds to the top of the substrate. The dimensional thickness for the substrate is the same as for this embodiment as for the first embodiment of FIGS. 1-4 of the present invention.
[0181] FIG. 6 is the same embodiment as shown on FIG. 5 except it is a fully assembled view of the second embodiment of the present invention.
[0182] FIG. 7 is the similar to the embodiment from FIGS. 5 and 6 except the structure is all soldered together as one package to provide for better reliability.
[0183] FIGS. 8-11 basically describe a third embodiment of the present invention in which the passive components [65] are embedded directly into the pitch translation substrate [66]. This requires that the pitch translation substrate [65] be compatible with component embedding and that thin redistribution layers be built-up between the components and the lower/bottom surface of the pitch translation substrate [65]. Using thin layers (sub.Math.5 um) creates the closest possible location of the passive embedded components [65] to the wafer/die [59]. Unlike the first and second embodiments of the present invention this third embodiment does not use a thin pitch translation substrate—only thin build-up layers, as shown in FIG. 20. Third embodiment also requires the routing method shown in FIG. 17 where the center portion (directly above the die) of the pitch translation substrate prioritizes on power and ground routing. Third embodiment has all of the distance gains of second embodiment plus, on average, 125 um to account for the effective thickness of the pitch translation substrate.
[0184] As shown in FIG. 12A, this third embodiment achieves the lowest possible supply loop impedance from the die to the passive components—outperforming both the first and second embodiments of the present invention and all prior art. FIGS. 13A, 14 A, and 15 A compare the data eye of the third embodiment to the prior art for a random data stream—667 MBs, 1000 MBs, and 2000 MBs, respectively. FIG. 16 A compares clock data for the third embodiment to the prior art.
[0185] All embodiments embed the passive decoupling and filtering components in as way as to locate them much closer to the die itself. The first and second embodiments achieve this via embedding and with the use of a thin pitch translation substrate. The third embodiment achieves this via embedding within the pitch translation substrate, while using thin, very dense redistribution layers. In all cases, the embodiments reduce the supply loop impedance significantly—at minimum by a factor of 5 (first embodiment) and up to a factor of 20 (third embodiment) (See FIG. 12).
[0186] FIG. 8 shows a sectional exploded view of a third embodiment in which a structure has passive components 65 fully embedded directly to a pitch translation substrate 66, formed of thin build-up layers, as shown in FIG. 20, directly beneath thin electrical signal redistribution layers, the pitch translation substrate again has preferably the same width dimensions described in the pitch translation substrate of the first embodiment of FIG. 1 of the present invention. This third embodiment of the present invention shown in FIG. 8 provides the highest performance as the passive components 65 such as capacitors 65 are embedded directly into the pitch translation substrate 66. FIG. 9 shows the embodiment of FIG. 8 in a fully assembled view FIG. 10 is similar to FIG. 8 embodiment all soldered together as one unit. FIG. 11 is the prior art structure previously discussed.
[0187] While presently preferred embodiments have been described for purposes of the disclosure, numerous changes in the arrangement of method steps and those skilled in the art can make apparatus parts. Such changes are encompassed within the spirit of the invention as defined by the appended claims.
