Article Comprising a Photodiode-side Integrated Fuse for Avalanche Photodetector Focal Plane Array Pixels and Method Therefor

Abstract

A scalable fuse design for individual pixels of a focal plane array of photodiodes comprises a fuse disposed on the upper surface of each photodiode in the array, wherein the fuse is situated proximal to a side of each photodiode. The fuse of each photodiode is electrically coupled to the active region thereof via a first bus and is electrically coupled to an ROIC via a second bus.

Claims

1. An article comprising : a pixel of a photodiode array, the pixel comprising a photodiode and having a planar upper surface; and a fuse disposed on the planar upper surface, wherein the fuse is disposed proximal to an edge of the pixel, and wherein the fuse is electrically coupled to an active region of the pixel.

2. The article of claim 1 wherein the active region of the pixel is accessed proximal to a center of the pixel.

3. The article of claim 1 and further comprising a first bus, wherein the first bus electrically couples the fuse to the active region.

4. The article of claim 1 and further wherein the fuse is electrically coupled to a read-out integrated circuit via an offset electrical connection.

5. The article of claim 4 and further comprising a second bus, wherein the second bus electrically couples the fuse to the offset electrical connection.

6. The article of claim 1 wherein the photodiode array comprises an array of avalanche photodiodes.

7. The article of claim 1 wherein each pixel in the photodiode array includes a fuse.

8. The article of claim 1 and further wherein an isolation trench surrounds each pixel in the photodiode array, and wherein a distance between the fuse and the isolation trench is about one micron.

9. The article of claim 1 wherein the fuse comprises aluminum.

10. The article of claim 9 wherein a ratio of a length of the fuse to a cross-sectional area of the fuse is in a range of about 3.2×10.sup.9 to 2.1×10.sup.8 m.sup.−1.

11. An article comprising: an array of avalanche photodiodes, each avalanche photodiode in the array having a substantially planar upper surface; and a plurality of fuses, wherein one fuse is disposed on the substantially planar upper surface of each of the avalanche photodiodes in the array, wherein, on each avalanche photodiode, the one fuse is electrically coupled to an active region thereof and is also electrically coupled to a read-out integrated circuit.

12. The article of claim 11 comprising: a first bus, wherein the first bus electrically couples the fuse to the active region of the avalanche photodiode; and a second bus, wherein the second bus electrically couples the fuse to the read-out integrated circuit through an offset electrical connection.

13. The article of claim 12 wherein a ratio of a width of the first bus or the second bus to a width of the fuse is at least 2.

14. The article of claim 11 wherein the first and second bus comprise a material selected from the group consisting of gold and silver.

15. A method comprising: forming an array of photodiodes, wherein at least some of the photodiodes in the array are formed to have an upper surface that is atomically flat; depositing a first passivating/insulating layer on said some photodiodes; depositing a metal stack on a portion of the passivating/insulating layer of each of said some photodiodes, wherein the metal stack comprising plural layers of different metals, and wherein: (a) a first portion of the metal stack defines a fuse having a first end and a second end, (b) a second portion of the metal stack extends beyond the first end of the fuse, and (c) a third portion of the metal stack extends beyond a second end of the fuse; depositing a first bus on the second portion of the metal stack, wherein the first bus electrically couples the fuse to an active region of the photodiode; depositing a second bus on the third portion of the metal stack, wherein the second bus terminates in a pad that receives a metal bump for electrical connection with read-out circuitry for the array of photodiodes; and depositing, on each of said some photodiodes, a second passivating/insulating layer except for on the pad.

16. The method of claim 15 wherein depositing a metal stack further comprises depositing the first portion of the metal stack proximal to a first edge of each of said some photodiodes.

17. The method of claim 16 wherein depositing a metal stack further comprises depositing the second portion of the metal stack proximal to a second edge of each of said photodiodes and depositing the third portion of the metal stack proximal to a third edge of each of said photodiodes.

18. The method of claim 15 wherein depositing a second bus stack further comprises disposing the pad in a location on the photodiode that is off-center.

19. The method of claim 15 wherein the metal stack comprises aluminum.

20. The method of claim 15 wherein a length of the fuse is in a range of about 6.5 microns to about 25 microns.

21. The method of claim 15 wherein a length of the fuse is in a range of about 1 micron to about 30 microns.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0008] FIG. 1A depicts a top view of a conventional 4×5, backside illuminated, APD PDA.

[0009] FIG. 1B depicts, in greater detail, a single pixel from the APD PDA of FIG. la.

[0010] FIG. 2A through 2B and 2D through 2F depict a fabrication sequence for a photodiode-side integrated fuse for individual pixels in an APD PDA, in accordance with the illustrative embodiment of the present invention.

[0011] FIG. 2C depicts an embodiment of a layer structure for the integrated fuse.

[0012] FIG. 3 depicts a thermal equivalent circuit model of the integrated fuse depicted in FIGS. 2B and 2C.

[0013] FIG. 4 depicts a truncated, schematic-level cross-sectional view of the fully integrated fuse.

[0014] FIG. 5 depicts the fully integrated fuse shown in FIG. 4 with materials and dimensions for an exemplary embodiment.

[0015] FIGS. 6A and 6B depict the scalable nature of fuses in accordance with the present invention.

DETAILED DESCRIPTION

[0016] The following terms are defined for use in this disclosure and the appended claims: [0017] A “photodiode focal plane array” comprises, among other elements, an array of photodiodes, an array of micro lenses for focusing photons onto the photodiodes in the area, a read-out integrated circuit (“ROIC”). [0018] A “photodiode array” comprises an array of photodiodes. [0019] A “pixel” is a basic unit of an array. In the context of a photodiode array, the term “pixel” references a single photodiode of the array. In the context of a photodiode focal plane array, the term “pixel” collectively references a single photodiode in the photodiode array and a pixel in the ROIC, at a minimum. In the illustrative embodiment, there is a one-to-one correspondence between pixels in the photodiode array and pixels in the ROIC.

[0020] FIG. 1A depicts a top view of a conventional, backside illuminated, avalanche photodetector (APD) focal plane array 100. The exemplary array depicted in FIG. 1A comprises twenty pixels 102 in a 4×5 array. FIG. 1B depicts further detail of a single pixel 102 from array 100 of FIG. 1A.

[0021] As seen in these Figures, etched isolation trench 108 having an exemplary width of 6 microns separates each pixel 102. FIG. 1B depicts pixel 102 and a half width (i.e., 3 microns) of etched isolation trench 108.

[0022] An exemplary width of each pixel 102 is 50 microns. It is notable that active region 106 is centered within the pixel; this is important for limiting leakage currents. In the illustrative embodiment, surface 104 of pixel 102 comprises InP. In typical bump-bonded devices, active region 106 is coated with a metal film, and a metal bump is affixed concentrically to the top of this stack to enable bump-bonded contact with a CMOS ROIC.

[0023] FIGS. 2A through 2B and 2D through 2F depict a method for fabricating a photodiode-side integrated fuse for individual pixels 102 in an APD PDA, in accordance with the present teachings. Beginning with the basic pixel structure depicted in FIG. 1B, surface 104, which in the illustrative embodiment is InP, is coated with a passivating/insulating layer 210 in FIG. 2A. In some other embodiments, the avalanche photodiodes are based on other materials systems (i.e., materials other than InP). It is within the capabilities of those skilled in the art to adapt the present teachings to APD based on such other materials systems. In the illustrative embodiment, layer 210 comprises silicon nitride, SiN.sub.x. SiN.sub.x may be deposited via a variety of processes, including plasma enhanced chemical vapor deposition (PECVD), inductively coupled plasma chemical vapor deposition (ICP CVD), reactive ion beam deposition (RIBD), or physical vapor deposition (PVD) (also known as “sputtering”). Opening 212 is patterned in layer 210 to keep active area 106 exposed. In some other embodiments, passivating/insulation layer 210 comprises SiO.sub.2, although SiN.sub.x is generally preferred.

[0024] As depicted in FIG. 2B, fuse 214 is deposited along one edge of (each) pixel 102. In the illustrative embodiment, the fuse is deposited on the passivating/insulating layer of SiN.sub.x. In some alternative embodiments, polyimide is spun on the SiN.sub.x (or SiO.sub.2). As depicted in FIG. 2C, the fuse is embodied as stack 218 having multiple layers 220, 222, and 224 of metals, which are deposited as thin films. In the illustrative embodiment, stack 218 comprises thin-film layer 220 of titanium, thin-film layer 222 of aluminum over the titanium, and thin-film layer 224 of nickel over the aluminum. In the illustrative embodiment, layer 220 is used as an adhesion promoter (to layer 210) and layer 224 is used to prevent oxidation of the aluminum (i.e., layer 222). In some other embodiments, layer 220 is tantalum and/or layer 224 is chromium. In the illustrative embodiment, layer 222—aluminum—can be considered to be the primary fuse material. In some other embodiments, layer 222 is, without limitation, nickel, titanium, palladium, tin, platinum, germanium, or gold. Bus regions 216 extend from opposite ends of fuse 214 along opposed edges of pixel 102. In the illustrative embodiment, the width W.sub.B of buses 216 is 4 microns.

[0025] It is important that an apron or border region 226 having a minimum width of about one micron as measured between the “outer” edge of fuse 214 or buses 216 and the nearest edge of trench 108 is present. The border region ensures that the fuse will be deposited on a sufficiently flat surface and therefore not overlap the trench. The minimum width of about 1 micron between potentially interacting features is based on current photolithography mask registration tolerances. In the illustrative embodiment, the width W.sub.A of apron region 226 is 2 microns. With filet features, a 6-micron trench and 2-microns clearance on a 50-micron pitch pixel, the length L.sub.F of fuse 214 is about 25 microns.

[0026] As shown in FIG. 2D, buses 228A and 228B, which each comprise one or more layers of electrically conductive metal(s), such as titanium, platinum, and gold, extend from respective ends of fuse 214, being deposited over buses 216. Within buses 228A and 228B, the gold is primarily used to transport current. The titanium and platinum are used as diffusion barriers to prevent gold/indium from diffusing into the underlying InP of the APD. In an alternative embodiment, silver replaces gold as the primary current-transport layer and a tungsten/titanium alloy is used as the diffusion barrier. Alternatively, the upper layer of tungsten/titanium alloy is replaced by layers of titanium (40 nm), nickel (200 nm), and gold (100 nm). Bus 228A connects active region 106 (see, e.g., FIG. 2A) to fuse 214. Bus 228A terminates in circular portion 230 that overlies active region 106. In the illustrative embodiment, the diameter D.sub.O of circular portion 230 is 8 microns. Bus 228B extends to form conductive base or pad 230 for an offset metal bump for eventual connection to read-out circuitry (not depicted). In the illustrative embodiment, diameter D.sub.P of pad 232 is 18 microns. With the aforementioned dimensions, gap G between the circular portion 230 and pad 232 is 2 microns.

[0027] Per FIG. 2E, passivation/insulation layer 234 is deposited on top of all features except for pad 232. Passivation/insulation layer 234 is used to provide electrical and thermal insulation. For example, layer 234 further insulates the active-area bus (i.e., 228A/230) from direct contact with the ROIC-side bus (i.e., 228B/232). In the illustrative embodiment, layer 234 comprises SiNX. In other embodiments, other materials can suitably be used, such as and without limitation, polyimide and SiO.sub.2.

[0028] Finally, per FIG. 2F, bump 236, which is comprises an electrically conductive material, such as indium, is affixed to the top of pad 232, enabling electrical connection between the photodiode 102 and the eventual bump-bonded CMOS circuitry (i.e., the ROIC). Other materials known to those skilled in the art may suitably be used in place of indium for bump 236. For example and without limitation, bump 236 can comprise: SnPb37, InAg, AuSn80/20, SnAg3.5, or Cu/CuSn pillars.

[0029] Specific layer thicknesses are dependent on desired fuse properties, which in turn are highly dependent on the choice of fuse material and in-depth knowledge of the underlying APD technology. The inventors have learned, from their own implementation of APD cameras, that with the inclusion of a safety margin, fuses will need to carry up to 1 mA current without adverse reaction for normal operation. However, current ROIC implementations begin to malfunction at the array level beyond 15 mA of applied current. Based on results from finite-element analysis, the inventors determined that thin-film fuses can effectively be treated as thermally insulted from their surroundings when integrated on substrates with substantially lower thermal conductivities. Highly electrically- and thermally-conductive fuse materials surrounded by material of a lower electrical and thermal conductivity will allow for a build-up of heat in the fuse before dissipation, enabling the temperature at the center of the fuse to be calculated using a two-element equivalent thermal circuit. FIG. 3 depicts equivalent circuit 340 for the illustrative fuse implementation.

[0030] Because the fuse can be treated as though it is surrounded by a perfect thermal insulator for the duration of its joule heating, the maximum temperature T.sub.max will be reached in its center. The thermally conductive path length to thermal “ground” is therefore equal to L/2, where L is the total length of the fuse.

[0031] In this implementation, the thermal equivalent circuit is governed by:

PR.sub.Θ=(T.sub.max−T.sub.RT)   [1]

[0032] where: P is heat flow; [0033] R.sub.Θis the thermal resistance; and [0034] T.sub.RT is the temperature of the fuse at its end points.
With the length of the thermally conductive path to thermal ground equal to L/2, the equation governing the temperature difference between the center of the fuse and its end points is thus:

[00001]$\begin{array}{cc}{T}_{\max }-T_{\mathrm{RT}}=\frac{P\left(L.Math.\text{/}.Math.2\right)}{\kappa .Math..Math.A}& \left[2\right]\end{array}$

[0035] where: K is thermal conductivity; and [0036] A is the cross-sectional area.

[0037] In the case of joule heating, P=I.sup.2R, where: P is power, I is current, and R is the total electrical resistance of the fuse. Using R=ρL/A, where ρ is electrical resistivity, and recognizing that the melting point, thermal conductivity, and electrical resistivity are determined by the choice of fuse material, the necessary length-to-area ratio of the fuse can be expressed as a function of prescribed electrical current and fuse material:

[00002]$\begin{array}{cc}L.Math.\text{/}.Math.A=\sqrt{2.Math.\frac{\Delta .Math..Math.T.Math..Math.\kappa }{I^2.Math.\rho }}& \left[3\right]\end{array}$

[0038] where: ΔT=(T.sub.melt−T.sub.RT) [0039] T.sub.melt is the melting point of the fuse material.

[0040] Ideally, a thin-film fuse is relatively straightforward to fabricate (i.e., on a flat surface), with a lower melting point, higher thermal conductivity, and lower electrical resistivity than its surroundings. Using aluminum as an example, having a melting point of 993 K, a thermal conductivity of 205 W/m.Math.K, and an electrical resistivity of 2.82×10.sup.−8 Ω.Math.m, and with a desired current in the range of about 1 to about 15 mA, a desired L/A ratio is in the range of about 3.2×10.sup.9 to about 2.1×10.sup.8 m.sup.−1. Using a practical minimum for area dimensions, a fuse thickness of five nanometers (nm) and a fuse width of 0.25 microns, a minimum range of necessary fuse lengths in the range of about 0.3 to about 4 microns is obtained. Allowing for some margin on thickness and/or width, the length requirement increases, emphasizing a need to design a layout that maximizes available length for the fuse.

[0041] FIGS. 4 and 5 depict an exemplary integrated fuse 214 in cross-section (see also, FIG. 2C), with FIG. 5 depicting exemplary materials and layer thicknesses.

[0042] In the illustrative embodiment, fuse comprises aluminum, deposited to a thickness of about 10 nm. A very thin layer of titanium is used as an adhesive layer between passivation/insulation layer 210 (e.g., silicon nitride, etc.) and the aluminum. The titanium must be thick enough to enable adhesion between the underlying substrate and the fuse material. In the illustrative embodiment, a thickness of 2 nm was sufficient. In other embodiments in which a different substrate is used, a slightly thicker layer might be required to produce a flat, cohesive adhesion film. A thickness in the range of about 2 to 10 nm is expected to be sufficient for most substrates. However, one skilled in the art can readily verify the thickness requirement via simple experimentation. A very thin layer of nickel is deposited on the aluminum to protect the fuse against aluminum oxidation. The capping layer of nickel must be thick enough to prevent oxygen transport to the fuse. A layer of nickel having a thickness of 2 nm was determined by experimentation to be sufficient for this purpose. If a different material is used for as the capping layer, a different thickness might be required to prevent oxygen transport. In such situations, those skilled in the art will be able to determine the required thickness via simple experimentation.

[0043] The bus metals (titanium, platinum, and gold in the illustrative embodiment) of circular portion 230 of bus 228A provide electrical connection to the APD (at the left in FIGS. 4 and 5) and the bus metals of pad 232 of bus 2288 provides electrical connection to the ROIC (at the right in FIGS. 4 and 5). In the illustrative embodiment, buses 228A and 2288 comprise a layer of titanium having a thickness of 30 nm, a layer of platinum having a thickness of 40 nm on top of the titanium, and a layer of gold having a thickness of 100 nm on top of the platinum. The aforementioned layer thicknesses are for the illustrative embodiment. For all such layers, there is a minimum thickness that must be exceeded in order to ensure that the layer, as deposited, contains no pinholes that reach to the underlying layer. That minimum is about 10 nm. There is no particular maximum thickness; the maximum is bounded by the specifics of other depositions in the overall process. An upper bound for the thickness of the titanium and platinum layers is about 100 nm for each layer. An upper bound for the thickness of the gold layer is about 1 micron.

[0044] In the illustrative embodiment, passivation/insulation layer 210 comprises silicon nitride having a thickness of 150 nm and passivation/insulation layer 234 comprises silicon nitride having a thickness of about 170 nm. Once again, the aforementioned layer thicknesses are for the illustrative embodiment. As previously discussed, there is a minimum thickness that must be exceeded in order to ensure that the layer, as deposited, contains no pinholes that reach to the underlying layer. And the maximum is bounded by the specifics of other depositions in the overall process. A range for the thickness of these layers is typically between about 10 nm and about 1 micron. In the illustrative embodiment, lower layer 210 must be thinner than bus 228A (i.e., the stack of Ti+Pt+Au), which is 170 nm. Hence, a thickness of 150 nm was selected for layer 210). And upper layer 234 is ideally about the same thickness as bus 228B. Hence, a thickness of 170 nm was selected for layer 234.

[0045] FIGS. 6A and 6B depict how, with the aforementioned reasonable fabrication limits on trace deposition, the design is readily scalable to a PDA with 25 micron pitch. The resistance of the fuse can be kept within the design range at shorter fuse lengths by reducing its width. For example, for a PDA having a plurality of pixels with a 50 micron pitch, the fuse length L.sub.F is about 25 microns and fuse width W.sub.F is 2 microns. For a PDA having a plurality of pixels with a 25 micron pitch, the fuse length L.sub.F is about 6.5 microns and fuse width W.sub.F is 0.5 microns. It is expected that for most applications, fuse length L.sub.F will be in the range of about 1 micron to 30 microns.

[0046] The following guidelines are provided for the scalable design: [0047] a minimum 1 micron clearance between fuse and pixel isolation trench; [0048] a minimum 2 micron clearance between the two Ti/Pt/Au circular regions; [0049] SiN.sub.x covers the fuse and the central Ti/Pt/Au deposition to ensure electrical isolation from bump 236 (providing connection to the ROIC); [0050] a minimum 1 micron trench width; [0051] a minimum bus width-to-fuse width ratio of 2; and [0052] a minimum filet radius of curvature equal to bus width.
Acceptable margins between critical features can be maintained down to a pixel pitch of about 25 microns.

[0053] It is to be understood that the disclosure teaches just one example of the illustrative embodiment and that many variations of the invention can easily be devised by those skilled in the art after reading this disclosure and that the scope of the present invention is to be determined by the following claims.