Power stabilization circuit and method

Abstract

A power stabilization circuit including a first reference power supply, a second reference power supply, and a combiner circuit coupled to the first reference power supply and the second reference power supply. The first reference power supply is configured to receive a first control signal, generate a first reference signal based on the first control signal, and provide the first reference signal to a first output power supply. The second reference power supply is configured to receive a second control signal, generate a second reference signal based on the second control signal, and provide the second reference signal to a second output power supply. The combiner circuit is configured to generate a combined reference signal based on the first reference signal and the second reference signal and drive a reference load based on the combined reference signal.

Claims

1. A power stabilization circuit comprising: a first reference power supply configured to receive a first control signal, generate a first reference signal based on the first control signal, and provide the first reference signal to a first output power supply; a second reference power supply configured to receive a second control signal, generate a second reference signal based on the second control signal, and provide the second reference signal to a second output power supply; and a combiner circuit coupled to the first reference power supply and the second reference power supply, the combiner circuit configured to generate a combined reference signal based on the first reference signal and the second reference signal and drive a reference load based on the combined reference signal.

2. The power stabilization circuit of claim 1 wherein an output impedance of at least one of the first reference power supply and the second reference power supply is greater than ten percent of an impedance of the reference load.

3. The power stabilization circuit of claim 1 wherein the first reference signal has a different frequency range than the second reference signal.

4. The power stabilization circuit of claim 1 wherein the combiner circuit includes an inductor coupled in series between the first reference power supply and the reference load.

5. The power stabilization circuit of claim 4 wherein the combiner further includes a capacitor coupled in series between the second reference power supply and the reference load.

6. The power stabilization circuit of claim 5 wherein the first reference power supply is a low-speed reference power supply and the second reference power supply is a high-speed reference power supply.

7. The power stabilization circuit of claim 1 wherein the first reference power supply includes a first frequency limiting circuit to limit the first control signal to a first frequency range.

8. The power stabilization circuit of claim 7 wherein the first reference power supply further includes a buffer coupled to the first frequency limiting circuit.

9. The power stabilization circuit of claim 7 wherein the second reference power supply includes a second frequency limiting circuit to limit the second control signal to a second frequency range, the first frequency range being different than the second frequency range.

10. The power stabilization circuit of claim 9 wherein the second reference power supply further includes a buffer coupled to the second frequency limiting circuit.

11. The power stabilization circuit of claim 1 wherein the first output power supply and the second output power supply are coupled to an output power combiner circuit.

12. The power stabilization circuit of claim 11 wherein a frequency response of the first reference power supply substantially matches a frequency response of the first output power supply.

13. The power stabilization circuit of claim 12 wherein a frequency response of the second reference power supply substantially matches a frequency response of the second output power supply.

14. The power stabilization circuit of claim 11 wherein the output power combiner circuit is configured to drive an output load and an impedance of the reference load is at least an order of magnitude more than an impedance of the output load.

15. A method of operation in a power stabilization circuit comprising: receiving a first control signal and a second control signal; generating a first reference signal based on the first control signal; generating a second reference signal based on the second control signal; combining the first reference signal and the second reference signal to generate a combined reference signal; driving a reference load with the combined reference signal; and providing the first reference signal and the second reference signal to at least one power supply circuit.

16. The method of claim 15 wherein generating the second reference signal includes generating the second reference signal having a different frequency range than the first reference signal.

17. The method of claim 15 wherein generating the first reference signal includes filtering the first control signal to limit the first control signal to a first frequency range.

18. The method of claim 17 wherein generating the second reference signal includes filtering the second control signal to limit the second control signal to a second frequency range, the second frequency range being different from the first frequency range.

19. The method of claim 15 wherein providing the first reference signal and the second reference signal to the at least one power supply circuit includes providing the first reference signal to a first power supply circuit and providing the second reference signal to a second power supply circuit.

20. The method of claim 19 further comprising limiting a frequency of the first reference signal to match a frequency response of the first power supply circuit and limiting a frequency of the second reference signal to match a frequency response of the second power supply circuit that is different than the frequency response of the first power supply circuit.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The teachings of the embodiments of the present disclosure can be readily understood by considering the following detailed description in conjunction with the accompanying drawings.

(2) FIG. 1A illustrates a power supply system, according to an embodiment of the present disclosure.

(3) FIG. 1B illustrates the power supply system of FIG. 1A in more detail, according to an embodiment of the present disclosure.

(4) FIG. 2 illustrates a RF PA system that includes the power supply system of FIG. 1A, according to an embodiment of the present disclosure.

DETAILED DESCRIPTION OF EMBODIMENTS

(5) The Figures (FIG.) and the following description relate to preferred embodiments of the present disclosure by way of illustration only. It should be noted that from the following discussion, alternative embodiments of the structures and methods disclosed herein will be readily recognized as viable alternatives that may be employed without departing from the principles of the disclosed embodiments.

(6) Reference will now be made in detail to several embodiments of the present disclosure, examples of which are illustrated in the accompanying figures. It is noted that wherever practicable similar or like reference numbers may be used in the figures and may indicate similar or like functionality. The figures depict embodiments of the present disclosure for purposes of illustration only. One skilled in the art will readily recognize from the following description that alternative embodiments of the structures and methods illustrated herein may be employed without departing from the principles of the embodiments described herein.

(7) Embodiments of the present disclosure relate to a power supply system with a power output stage that combines power output from a low-speed power supply and a high-speed power supply to generate a combined power output for driving a load. The power outputs are combined with a L-C circuit that can cause resonance in the combined power output. To prevent this resonance, a power stabilization stage is added before the final power output stage that substantially mirrors the power output stage and shares the same resonance characteristics as the power output stage.

(8) FIG. 1A illustrates a power supply system 100, according to an embodiment of the present disclosure. The power supply system 100 receives a predetermined supply control signal 110 representing the desired output voltage V.sub.OUTC at the output of the power supply system 100 and generates an output voltage V.sub.OUTC in accordance with the predetermined supply control signal 110. The output voltage V.sub.OUTC provides power to and drives an output load Z.sub.2. For example, the output load Z.sub.2 can be a digital circuit or PA that has rapidly changing power requirements.

(9) As shown, the power supply system 100 includes three circuit stages: a feedback stage 102, a power stabilization stage 104 and power output stage 106. The feedback stage 102 uses negative feedback to regulate the output of the power supply system 100 and includes an error amplifier 112, a loop compensation (Loop Comp) block 116, a low pass filter (LPF) 114 and a high pass filter (HPF) 118. The error amplifier 112 compares a feedback signal 112 with a predetermined supply control signal 110 representing the desired output voltage V.sub.OUTC at the output of the power supply system 100. The error amplifier 104 generates an error voltage 124 based on the difference between the feedback signal 112 and the supply control signal 110.

(10) The loop compensation (Loop Comp) block 116, the LPF 114, and the HPF 118 generate a low-speed power supply control signal 120 and a high-speed power supply control signal 122 based on the error voltage 124. The low-speed power supply control signal 120 and the high-speed power supply control signal 122 operate in different frequency ranges. The low-speed power supply control signal 120 is passed through the LPF 114, which causes the low-speed power supply control signal 120 to include low-frequency and DC components for controlling a low-speed power path of the power supply system 100. The high-speed power supply control signal 122 is passed through the HPF 118, which causes the high-speed power supply control signal 122 to include high-frequency components for controlling a high-speed power path of the power supply system 100.

(11) The loop compensation block 116 shapes a frequency response of the overall loop of the power supply system 100 to enhance stability. This function includes gain reduction at high frequencies as required by any control loop. Portions of the desired frequency shaping may naturally occur within any of the blocks in the power supply system 100, and therefore this function may be distributed within these blocks. In this case, the loop compensation block 116 may not be needed.

(12) The power stabilization stage 104 stabilizes the output of the power supply system 100 and includes a low-speed reference supply 130, a high-speed reference supply 132, and a reference combiner circuit 142. Low-speed reference supply 130 generates a low-speed reference voltage signal V.sub.REF1 from the low-speed power supply control signal 120. The low-speed reference supply 130 operates in a low frequency range and has a frequency response that matches the frequency response of the low-speed power supply 150. As a result, the low-speed reference voltage V.sub.REF1 has a frequency response that is limited by the frequency response of the low-speed reference supply 130. High-speed reference supply 132 generates a high-speed reference voltage signal V.sub.REF2 from the high-speed power supply control signal 122. The high-speed reference supply 132 operates in a high frequency range and has a frequency response that matches the frequency response of the high-speed power supply 152. As a result, the high-speed reference voltage V.sub.REF2 has a frequency response that is limited by the frequency response of the high-speed reference supply 132. There may be overlap between the two different frequency ranges, but the highest end of the high-frequency range is generally higher than the highest end of the low-frequency range.

(13) There are also output impedances Z.sub.x and Z.sub.y located at the respective outputs of the low-speed reference supply 130 and the high-speed reference supply 132. As will be explained by reference to FIG. 1B, the output impedances Z.sub.x and Z.sub.y reduce resonance within the power supply system 100, thereby increasing the stability of the power supply system 100.

(14) The high-speed reference voltage signal V.sub.REF1 and low-speed reference voltage signal V.sub.REF2 are combined in the reference combiner circuit 142 to produce a combined reference voltage signal V.sub.REFC. The reference combiner circuit 142 provides isolation between the output of the low-speed reference supply 130 and the output of the high-speed reference supply 132 while still combining the reference voltages V.sub.REF1 and V.sub.REF2. The combined reference voltage signal V.sub.REFC drives a reference load Z.sub.1. The reference load Z.sub.1 may be a dummy load within the power supply system 100 instead of an active device (e.g. PA or electronic circuit).

(15) The power output stage 106 includes a low-speed power supply 150 paired with a high-speed power supply 152, both of which are coupled to a power combiner circuit 154. The low-speed power supply 150 receives the low-speed reference voltage signal V.sub.REF1 and uses the low-speed reference voltage signal V.sub.REF1 to control a level of its output voltage V.sub.OUT1. The high-speed power supply 152 receives the high-speed reference voltage signal V.sub.REF2 and uses the high-speed reference voltage signal V.sub.REF2 to control a level of its output voltage V.sub.OUT2. In one embodiment, the low-speed power supply 150 and high-speed power supply 152 have unitary voltage gain (but large current gain) and produce output voltages V.sub.OUT1 and V.sub.OUT2 that match their respective reference voltages V.sub.REF1 and V.sub.REF2.

(16) The low-speed power supply 150 can be a SMPS, such as a buck converter, a boost converter, flyback converter, or other switching regulator. A SMPS typically has high power efficiency but a low frequency response, resulting in slow transient response time. The low-speed power supply 150 is operated in a low frequency range to compensate for slow changes to the desired output voltage V.sub.OUTC The high-speed power supply 152 can be a linear regulator that is less power efficient than a SMPS but has a higher frequency response and therefore faster transient response time than a SMPS. One example of a linear regulator is a push-pull regulator that can both sink and source current. The high-speed power supply 152 is operated in a higher frequency range to compensate for fast changes in the desired output voltage V.sub.OUTC.

(17) The output voltages V.sub.OUT1 and V.sub.OUT2 are combined in the power combiner circuit 154 to produce the combined output voltage V.sub.OUTC. The combined output voltage V.sub.OUTC is used to drive the output load Z.sub.2. The combined output voltage V.sub.OUTC is sensed via a sensor 156 and fed back as a feedback signal 112 to the feedback stage 102. Sensing via sensor 156 may be simply a wired connection, or may be accomplished with a resistive divider, for example.

(18) FIG. 1B illustrates the power supply system 100 of FIG. 1A in more detail, according to an embodiment of the present disclosure. As shown, reference combiner circuit 142 includes an inductor L.sub.1 connected in series with the output of the low-speed reference supply 130 to form a low pass network and a capacitor C.sub.1 connected in series with the output of the high-speed reference supply 132 to form a high pass network. The inductor L.sub.1 selectively passes power at low frequencies from the low-speed reference supply 130, and the capacitor C.sub.1 selectively passes power at high frequencies from the high-speed reference supply 132. The inductor L.sub.1 prevents the high-speed reference supply 132 from driving high frequency voltage into the output of the low speed reference supply 130, and the capacitor C.sub.2 prevents the low-speed reference supply 130 from driving low-frequency voltage into the output of the high-speed reference supply 132.

(19) Low-speed reference supply 130 includes a buffer amplifier 134 that generates a buffered output signal from the low-speed power supply control signal 120. The high-speed reference supply 132 also includes a buffer amplifier 138 that generates a buffered output signal from the high-speed power supply control signal 122. Examples of buffer amplifiers 134 and 138 include voltage follower amplifiers or emitter follower amplifiers that have a unitary voltage gain but provide some amount of current gain. The amount of current output supported by the buffer amplifiers 134 and 138 may be fairly low, so long as it is sufficient for providing power to the reference load Z.sub.1.

(20) The low-speed reference supply 130 and the high-speed reference supply 132 include respective frequency limiting circuits F.sub.x and F.sub.y. The frequency limiting circuit F.sub.x limits the frequency response of the low-speed reference supply 130 (e.g., by limiting the frequency response of the buffer 134 output) so that it is substantially matches the frequency response of the low-speed power supply 150. The frequency limiting circuit F.sub.y limits the frequency response of the high-speed reference supply 132 (e.g., by limiting the frequency response of the buffer 138 output) so that it is substantially matches the frequency response of the high-speed power supply 152. The frequency limiting circuits F.sub.x and F.sub.y can be, for example, gyrator circuits or other discrete frequency matching circuitry.

(21) As previously mentioned, output impedances Z.sub.x and Z.sub.y are located at the respective outputs of the low-speed reference supply 130 and high-speed reference supply 132. The L-C configuration of the reference combiner circuit 142 can create unwanted resonance if proper phase and amplitude relationships are not maintained between the reference voltages V.sub.REF1 and V.sub.REF2. The output impedances Z.sub.x and Z.sub.y dampen resonant energy in the reference combiner circuit 142 to control the level of reference voltages V.sub.REF1 and V.sub.REF2 such that the resonance is minimized. Simulation results have generally shown that the output impedances Z.sub.x and Z.sub.y should be set to a value that is greater than 10% of the impedance of the reference load Z.sub.1 to effectively dampen the resonance. In one embodiment, output impedances Z.sub.x and Z.sub.y are 16.6% of the impedance of the reference load Z.sub.1. Additionally, the output impedances Z.sub.x and Z.sub.y may be different from each other or be the same. Additionally, in some embodiments only one of the two output impedances Z.sub.x and Z.sub.y is present.

(22) Power combiner circuit 154 also includes an inductor L.sub.2 connected in series with the output of the low-speed power supply 150 to form a low pass network and a capacitor C.sub.2 connected in series with the output of the high-speed power supply 152 to form a high pass network. The inductor L.sub.2 selectively passes power at low frequencies from the low-speed power supply 150, and the capacitor C.sub.2 selectively passes power at high frequencies from the high-speed power supply 152.

(23) As shown in FIG. 1B, reference combiner circuit 142 and reference load Z.sub.1 are essentially a scaled replica of power combiner circuit 154 and output load Z.sub.2. The amount of the scaling is represented by the ratio k, where k is the impedance ratio of the reference load Z.sub.1 to the output load Z.sub.2 and is typically much greater than 1. The reference load Z.sub.1 has a substantially greater impedance than the output load Z.sub.2 For example, the impedance of reference load Z.sub.1 can be 1000 times greater than the impedance of output load Z.sub.2. The high impedance of the reference load Z.sub.1 means the power stabilization stage 104 consumes much less power than the power output stage 106. Higher impedances of the reference load Z.sub.1 result in less power consumption but greater amounts of noise in the power supply system 100. Additionally, the inductance of inductor L.sub.1 is k times greater than the inductance of inductor L.sub.2. The capacitance of capacitor C.sub.1 is k times less than the capacitance of capacitor C.sub.2.

(24) Because the reference combiner circuit 142 and reference load Z.sub.1 are a scaled version of the power combiner circuit 154 and output load Z.sub.2, both circuits have similar resonance characteristics. Resonance in the power stabilization stage 104 is prevented with the use of output impedances Z.sub.x and Z.sub.y. However, output impedances are not needed in the power output stage 106 to prevent resonance. This is because reference voltages V.sub.REF1 and V.sub.REF2, which are already resonance stabilized, are used as references for generating output voltages V.sub.OUT1 and V.sub.OUT2. Low-speed power supply 150 and high-speed power supply 152 both have unitary gain and have frequency responses that match their respective reference voltages V.sub.REF1 and V.sub.REF2, which results in V.sub.OUT1=V.sub.REF1 and V.sub.OUT2=V.sub.REF2 and guarantees that V.sub.OUT1 and V.sub.OUT2 are also resonance stabilized. Additionally, V.sub.REFC=V.sub.OUTC, although the current through intermediate load Z.sub.1 will be much lower than the current through output load Z.sub.2.

(25) Despite the additional circuitry in the power stabilization stage 104, using the power stabilization stage 104 to prevent resonance in the power output stage 106 is still more power efficient than increasing the output impedance of the low-speed power supply 150 and high-speed power supply 152. This is because the power output stage 106 drives a high amount of current into the output load Z.sub.2 so any additional impedance in the power output stage 106 consumes a high amount of power. On the other hand, the power stabilization stage 104 drives very little current into the reference load Z.sub.1 and therefore does not consume much power.

(26) FIG. 2 illustrates a RF PA system 200 that includes the power supply system 100 of FIG. 1A, according to an embodiment of the present disclosure. The RF PA system 200 includes a PA 202 that amplifies a RF input signal 204 to generate a RF output signal 206. The RF PA system 202 uses envelope tracking to adjust the supply voltage or bias to the PA 202 so that it tracks the changing envelope of the RF input signal 204. To this end, the amplitude detector circuit 208 detects an envelope amplitude of the RF input signal 204 and generates an amplitude signal 210 that is indicative of the envelope amplitude of the RF input signal 204. In one embodiment, the amplitude detector 208 calculates the envelope amplitude as a function of digital modulation components (I and Q) of a baseband signal used to generate the RF input signal 208.

(27) The power supply control circuit 212 uses the amplitude signal 210 to generate the supply control signal 110 that is indicative of a desired output voltage. In one embodiment, the power supply control circuit 212 may use a look up table that maps values of the amplitude signal 210 to values for the control signal 110. The power supply system 100 then uses the supply control signal 110 to generates a combined output voltage V.sub.OUT2 that serves as the supply voltage or bias to the PA 202.

(28) Upon reading this disclosure, those of ordinary skill in the art will appreciate still additional alternative structural and functional designs for stabilizing a power combining power supply system through the disclosed principles of the present disclosure. Thus, while particular embodiments and applications of the present disclosure have been illustrated and described, it is to be understood that the embodiments are not limited to the precise construction and components disclosed herein. Various modifications, changes and variations which will be apparent to those skilled in the art may be made in the arrangement, operation and details of the method and apparatus of the present embodiments disclosed herein without departing from the spirit and scope of the disclosure as defined in the appended claims.