Source driver and source drive method of liquid crystal panel of unequal row drive width

Abstract

The present invention provides a source driver and a source drive method of a liquid crystal panel of unequal row drive width. By providing the input signal decoding control unit electrically coupled to the plurality of data signal output channels and encoding the data signal output channel start address signal and the data signal output channel end address signal in the transport packages of the data signal to be transported to the input signal decoding control unit, the input signal decoding control unit controls the amount of activated data signal output channels to adjust the row drive width for each scan according to the received data signal output channel start address signal and the received data signal output channel end address signal. The row drive width of scan for each row can be dynamically adjusted to transport the data signal to the pixels required to display in each row. It is applicable for non rectangular display for reducing the output power of the liquid crystal panel and the source driver of the liquid crystal panel of unequal row drive width is derived from the present drive structure design. The structure is simple.

Claims

1. A source driver of a liquid crystal panel of unequal row drive width, comprising an input signal decoding control unit and a plurality of data signal output channels electrically coupled to the input signal decoding control unit; the input signal decoding control unit receives a data signal output channel start address signal, a data signal output channel end address signal and a data signal input sequence control signal; the input signal decoding control unit outputs a data signal output sequence control signal; the input signal decoding control unit controls an amount of activated data signal output channels to adjust a row drive width for each scan according to the received data signal output channel start address signal and the received data signal output channel end address signal; wherein the input signal decoding control unit comprises a combination switch, and the combination switch comprises a first thin film transistor, a second thin film transistor and a third reverse thin film transistor; a gate of the first thin film transistor is electrically coupled to the data signal output channel start address signal, and a source is electrically coupled to the data signal input sequence control signal, and a drain is electrically coupled to a register of the data signal output channel corresponding to a start address and a source of the third reverse thin film transistor; a gate of the second thin film transistor is electrically coupled to the data signal output channel end address signal, and a source is electrically coupled to the data signal output sequence control signal, and a drain is electrically coupled to a register of the data signal output channel corresponding to an end address and a drain of the third reverse thin film transistor; a gate of the third reverse thin film transistor is electrically coupled to the data signal output channel start address signal, and the source is electrically coupled to the drain of the first thin film transistor, and the drain is electrically coupled to the drain of a second thin film transistor.

2. The source driver of the liquid crystal panel of unequal row drive width according to claim 1, wherein the data signal output channel start address signal and the data signal output channel end address signal are encoded in transport packages of data signal and transported with the data signal together.

3. The source driver of the liquid crystal panel of unequal row drive width according to claim 2, wherein a length setting mode is added by amending decoding topology of a mini-LVDS transport protocol, and the length setting mode is employed for transporting the data signal output channel start address signal and the data signal output channel end address signal.

4. The source driver of the liquid crystal panel of unequal row drive width according to claim 2, wherein a 3-to-8 line decoder is employed to decode the data signal output channel start address signal and the data signal output channel end address signal which are encoded in the transport packages of the data signal.

5. The source driver of the liquid crystal panel of unequal row drive width according to claim 1, wherein the data signal output channels comprise: a shift register and a main latch circuit electrically coupled to the input signal decoding control unit, a sub latch circuit, a voltage potential conversion circuit electrically coupled to the sub latch circuit, a digital to analog converter electrically coupled to the voltage potential conversion circuit, an output buffer circuit electrically coupled to the digital to analog converter and an output circuit electrically coupled to the output buffer circuit.

6. A source driver of a liquid crystal panel of unequal row drive width, comprising an input signal decoding control unit and a plurality of data signal output channels electrically coupled to the input signal decoding control unit; the input signal decoding control unit receives a data signal output channel start address signal, a data signal output channel end address signal and a data signal input sequence control signal; the input signal decoding control unit outputs a data signal output sequence control signal; the input signal decoding control unit controls an amount of activated data signal output channels to adjust a row drive width for each scan according to the received data signal output channel start address signal and the received data signal output channel end address signal; wherein the input signal decoding control unit comprises a combination switch, and the combination switch comprises a first thin film transistor, a second thin film transistor and a third reverse thin film transistor; a gate of the first thin film transistor is electrically coupled to the data signal output channel start address signal, and a source is electrically coupled to the data signal input sequence control signal, and a drain is electrically coupled to a register of the data signal output channel corresponding to a start address and a source of the third reverse thin film transistor; a gate of the second thin film transistor is electrically coupled to the data signal output channel end address signal, and a source is electrically coupled to the data signal output sequence control signal, and a drain is electrically coupled to a register of the data signal output channel corresponding to an end address and a drain of the third reverse thin film transistor; a gate of the third reverse thin film transistor is electrically coupled to the data signal output channel start address signal, and the source is electrically coupled to the drain of the first thin film transistor, and the drain is electrically coupled to the drain of a second thin film transistor; wherein the data signal output channels comprise: a shift register and a main latch circuit electrically coupled to the input signal decoding control unit, a sub latch circuit, a voltage potential conversion circuit electrically coupled to the sub latch circuit, a digital to analog converter electrically coupled to the voltage potential conversion circuit, an output buffer circuit electrically coupled to the digital to analog converter and an output circuit electrically coupled to the output buffer circuit.

7. The source driver of the liquid crystal panel of unequal row drive width according to claim 6, wherein the data signal output channel start address signal and the data signal output channel end address signal are encoded in transport packages of data signal and transported with the data signal together.

8. The source driver of the liquid crystal panel of unequal row drive width according to claim 7, wherein a length setting mode is added by amending decoding topology of a mini-LVDS transport protocol, and the length setting mode is employed for transporting the data signal output channel start address signal and the data signal output channel end address signal.

9. The source driver of the liquid crystal panel of unequal row drive width according to claim 7, wherein a 3-to-8 line decoder is employed to decode the data signal output channel start address signal and the data signal output channel end address signal which are encoded in the transport packages of the data signal.

10. A source drive method of a liquid crystal panel of unequal row drive width, comprising steps of: step 1, providing a source driver of the liquid crystal panel of unequal row drive width; the source driver of a liquid crystal panel of unequal row drive width, comprising an input signal decoding control unit and a plurality of data signal output channels electrically coupled to the input signal decoding control unit; step 2, inputting a data signal output channel start address signal, a data signal output channel end address signal and a data signal input sequence control signal to the input signal decoding control unit; step 3, decoding the received data signal output channel start address signal and the received data signal output channel end address signal and setting a data signal output channel start address and a data signal output channel end address by the input signal decoding control unit; step 4, inputting the data signal corresponding to the data signal channels between the data signal output channel start address and the data signal output channel end address, and transporting the data signal to the corresponding pixels; wherein in the step 2, the data signal output channel start address signal and the data signal output channel end address signal are encoded in transport packages of data signal and transported with the data signal together.

11. The source drive method of the liquid crystal panel of unequal row drive width according to claim 10, wherein the input signal decoding control unit comprises a combination switch, and the combination switch comprises a first thin film transistor, a second thin film transistor and a third reverse thin film transistor; a gate of the first thin film transistor is electrically coupled to the data signal output channel start address signal, and a source is electrically coupled to the data signal input sequence control signal, and a drain is electrically coupled to a register of the data signal output channel corresponding to a start address and a source of the third reverse thin film transistor; a gate of the second thin film transistor is electrically coupled to the data signal output channel end address signal, and a source is electrically coupled to the data signal output sequence control signal, and a drain is electrically coupled to a register of the data signal output channel corresponding to an end address and a drain of the third reverse thin film transistor; a gate of the third reverse thin film transistor is electrically coupled to the data signal output channel start address signal, and the source is electrically coupled to the drain of the first thin film transistor, and the drain is electrically coupled to the drain of a second thin film transistor.

12. The source drive method of the liquid crystal panel of unequal row drive width according to claim 10, wherein in the step 2, a length setting mode is added by amending decoding topology of a mini-LVDS transport protocol, and the length setting mode is employed for transporting the data signal output channel start address signal and the data signal output channel end address signal.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The technical solution and the beneficial effects of the present invention are best understood from the following detailed description with reference to the accompanying figures and embodiments.

(2) In drawings,

(3) FIG. 1 is a structural diagram of a source driver according to prior art;

(4) FIG. 2 is a pixel arrangement diagram of an irregular liquid crystal panel;

(5) FIG. 3 is a structural diagram of a source driver of a liquid crystal panel of unequal row drive width according to the present invention;

(6) FIG. 4 is a circuit diagram of the combination switch in the source driver of the liquid crystal panel of unequal row drive width according to the present invention;

(7) FIG. 5 is a circuit diagram of a kind of decoder in the source driver of the liquid crystal panel of unequal row drive width according to the present invention;

(8) FIG. 6 is a waveform diagram of a mini-LVDS transport protocol according to prior art;

(9) FIG. 7 is a waveform diagram of a mini-LVDS transport protocol after improvement according to the present invention;

(10) FIG. 8 is an output waveform diagram of transmission according to the mini-LVDS transport protocol shown in FIG. 7;

(11) FIG. 9 is a row drive width waveform diagram of the source driver of the liquid crystal panel of unequal row drive width according to the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

(12) For better explaining the technical solution and the effect of the present invention, the present invention will be further described in detail with the accompanying drawings and the specific embodiments.

(13) Please refer to FIG. 3. The present invention first provides a source driver of a liquid crystal panel of unequal row drive width, comprising an input signal decoding control unit 10 and a plurality of data signal output channels 20 electrically coupled to the input signal decoding control unit 10.

(14) The input signal decoding control unit 10 receives a data signal output channel start address signal SET_start, a data signal output channel end address signal SET_end and a data signal input sequence control signal DIO_in; the input signal decoding control unit 10 outputs a data signal output sequence control signal DIO_out; the input signal decoding control unit 10 controls an amount of activated data signal output channels 20 to adjust a row drive width for each scan according to the received data signal output channel start address signal SET_start and the received data signal output channel end address signal SET_end.

(15) Specifically, the data signal output channels 20 comprise: a shift register and a main latch circuit electrically coupled to the input signal decoding control unit 10, a sub latch circuit, a voltage potential conversion circuit electrically coupled to the sub latch circuit, a digital to analog converter electrically coupled to the voltage potential conversion circuit, an output buffer circuit electrically coupled to the digital to analog converter and an output circuit electrically coupled to the output buffer circuit.

(16) Please refer to FIG. 4. The input signal decoding control unit 10 comprises a combination switch SW_MUX, and the combination switch SW_MUX comprises first thin film transistor T1, a second thin film transistor T2 and a third reverse thin film transistor T3. A gate of the first thin film transistor T1 is electrically coupled to the data signal output channel start address signal SET_start, and a source is electrically coupled to the data signal input sequence control signal DIO_in, and a drain is electrically coupled to a register of the data signal output channel corresponding to a start address and a source of the third reverse thin film transistor T3; a gate of the second thin film transistor T2 is electrically coupled to the data signal output channel end address signal SET_end, and a source is electrically coupled to the data signal output sequence control signal DIO_out, and a drain is electrically coupled to a register of the data signal output channel corresponding to an end address and a drain of the third reverse thin film transistor T3; a gate of the third reverse thin film transistor T3 is electrically coupled to the data signal output channel start address signal SET_start, and the source is electrically coupled to the drain of the first thin film transistor T1, and the drain is electrically coupled to the drain of a second thin film transistor T2.

(17) Furthermore, the data signal output channel start address signal SET_start and the data signal output channel end address signal SET_end are encoded in transport packages of data signal Data and transported with the data signal Data together. Preferably, the data signal output channel start address signal SET_start, the data signal output channel end address signal SET_end and the data signal are transported by improving the mini-LVDS transport protocol. Please refer to FIG. 6. Generally, the mini-LVDS transport modes can be categorized into two kinds of RESET and DataSampling. Please refer to FIG. 7. The present invention improves the mini-LVDS transport modes in general definition. A length setting mode LENGTH DEFINE is added by amending decoding topology (protocol) of the mini-LVDS transport protocol, and the length setting mode LENGTH DEFINE is employed for transporting the data signal output channel start address signal SET_start and the data signal output channel end address signal SET_end.

(18) A decoder is employed to decode the data signal output channel start address signal SET_start and the data signal output channel end address signal SET_end which are encoded in the transport packages of the data signal Data to acquire a data signal output channel start address and a data signal output channel end address.

(19) Specifically, please refer to FIG. 5. FIG. 5 is a circuit diagram of a 3-to-8 line decoder according to the present invention. The input end of the decoder comprises a first, a second and a third input channels, and each channel are divided into a forward channel and a reverse channel, which include a first, a second and a third forward input channels D0, D1, D2 and a first, a second and a third reverse input channels D0′, D1′, D2′. As transporting the digital signal “0” and “1” through the forward input channel, the signals are unchanged; as transporting through the reverse input channel, “0” will be reversed to be “1”, and “1” will be reversed to be “0”. The output end of the decoder comprises a first to an eighth output channels Y0 to Y7, and Each output channel receives input signals from three of the sixth channels, the first, the second, the third forward input channels D0, D1, D2 and the first, the second, the third reverse input channels D0′, D1′, D2′. The combination of the three channels of receiving the input signals for each output channel is different from the others. The first output channel Y0 is illustrated. The first output channel Y0 receives signals transported from the first, the second, the third reverse input channels D0′, D1′, D2′, i.e. Y0=D0′, D1′, D2′; as all the signals transported from the first, the second, the third reverse input channels D0′, D1′, D2′ are “1”, i.e. all the signals inputted into the first, the second, the third input channels are “0”, which “3′ b000” signal is inputted into the decoder, Y0=1, and the first output channel Y0 is activated to control the data signal output channel of corresponding address to be opened. Similarly, the relationships between all the input signals of the decoder and activated output channels are listed in the following table 1. The input signals of the decoder are the data signal output channel start address signal SET_start and the data signal output channel end address signal SET_end.

(20) TABLE-US-00001 TABLE 1 D2D1D0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 3′b000 1 3′b001 1 3′b010 1 3′b011 1 3′b100 1 3′b101 1 3′b110 1 3′b111 1

(21) On a basis of the source driver of the liquid crystal panel of unequal row drive width, the present invention further provides a source drive method of a liquid crystal panel of unequal row drive width, comprising steps of:

(22) step 1, referring to FIG. 3, FIG. 4, together, providing a source driver of the liquid crystal panel of unequal row drive width;

(23) The source driver of a liquid crystal panel of unequal row drive width, comprising an input signal decoding control unit 10 and a plurality of data signal output channels 20 electrically coupled to the input signal decoding control unit 10.

(24) The data signal output channels 20 comprise: a shift register and a main latch circuit electrically coupled to the input signal decoding control unit 10, a sub latch circuit, a voltage potential conversion circuit electrically coupled to the sub latch circuit, a digital to analog converter electrically coupled to the voltage potential conversion circuit, an output buffer circuit electrically coupled to the digital to analog converter and an output circuit electrically coupled to the output buffer circuit.

(25) The input signal decoding control unit 10 comprises a combination switch SW_MUX, and the combination switch SW_MUX comprises a first thin film transistor T1, a second thin film transistor T2 and a third reverse thin film transistor T3. A gate of the first thin film transistor T1 is electrically coupled to the data signal output channel start address signal SET_start, and a source is electrically coupled to the data signal input sequence control signal DIO_in, and a drain is electrically coupled to a register of the data signal output channel corresponding to a start address and a source of the third reverse thin film transistor T3; a gate of the second thin film transistor T2 is electrically coupled to the data signal output channel end address signal SET_end, and a source is electrically coupled to the data signal output sequence control signal DIO_out, and a drain is electrically coupled to a register of the data signal output channel corresponding to an end address and a drain of the third reverse thin film transistor T3; a gate of the third reverse thin film transistor T3 is electrically coupled to the data signal output channel start address signal SET_start, and the source is electrically coupled to the drain of the first thin film transistor T1, and the drain is electrically coupled to the drain of a second thin film transistor T2.

(26) step 2, inputting a data signal output channel start address signal SET_start, a data signal output channel end address signal SET_end and a data signal input sequence control signal DIO_in to the input signal decoding control unit 10.

(27) In the step 2, the data signal output channel start address signal SET_start and the data signal output channel end address signal SET_end are encoded in transport packages of data signal Data and transported with the data signal Data together. Preferably, A length setting mode LENGTH DEFINE is added by amending decoding topology of the mini-LVDS transport protocol, and the length setting mode LENGTH DEFINE is employed for transporting the data signal output channel start address signal SET_start and the data signal output channel end address signal SET_end.

(28) step 3, decoding the received data signal output channel start address signal SET_start and the received data signal output channel end address signal SET_end and setting a data signal output channel start address and a data signal output channel end address by the input signal decoding control unit 10.

(29) Specifically, a 3-to-8 line decoder as shown in FIG. 5 is employed to decode the data signal output channel start address signal SET_start and the data signal output channel end address signal SET_end which are encoded in the transport packages of the data signal Data to acquire a data signal output channel start address and a data signal output channel end address.

(30) step 4, inputting the data signal Data corresponding to the data signal channels 20 between the data signal output channel start address and the data signal output channel end address, and transporting the data signal Data to the corresponding pixels.

(31) Please refer to FIG. 8 and FIG. 9. FIG. 8 is an output waveform diagram of transmission according to the improved mini-LVDS transport protocol of the present invention. FIG. 9 is a row drive width waveform diagram of the source driver according to the present invention. As shown in FIG. 8, FIG. 9, the outputted row drive width of the present invention changes as the data signal output channel start address and the data signal output channel end address change. The dynamical adjustment to the row drive width of scan for each row can be realized.

(32) In conclusion, in the source drive method of the liquid crystal panel of unequal row drive width according to the present invention, by providing the input signal decoding control unit electrically coupled to the plurality of data signal output channels and encoding the data signal output channel start address signal and the data signal output channel end address signal in the transport packages of the data signal to be transported to the input signal decoding control unit, the input signal decoding control unit controls the amount of activated data signal output channels to adjust the row drive width for each scan according to the received data signal output channel start address signal and the received data signal output channel end address signal. The row drive width of scan for each row can be dynamically adjusted to transport the data signal to the pixels required to display in each row and not to transport the data signal to the pixels which are not required to display in each row. It is applicable for non rectangular display for reducing the output power of the liquid crystal panel and the source driver of the liquid crystal panel of unequal row drive width is derived from the present drive structure design. The structure is simple.

(33) Above are only specific embodiments of the present invention, the scope of the present invention is not limited to this, and to any persons who are skilled in the art, change or replacement which is easily derived should be covered by the protected scope of the invention. Thus, the protected scope of the invention should go by the subject claims.