Overcurrent detection circuit, host using the same, and method of detecting overcurrent

Abstract

An overcurrent detection circuit installed in a host for supplying power to a device is disclosed. The overcurrent detection circuit includes: a detection resistor disposed on a power supply line; a current monitoring unit that compares a detected voltage that is a voltage drop across the detection resistor with a variable threshold voltage and asserts an overcurrent detection signal if the detected voltage exceeds the threshold voltage; and a control unit including a timer. The control unit is switchable among (i) a first state where the threshold voltage is set to a first value that is in accord with a reference value for overcurrent protection, (ii) a second state where the threshold voltage is set to a second value that is greater than the first value, and (iii) a third state where the threshold voltage is set to a third value that is less than the first value.

Claims

1. An overcurrent detection circuit installed in a host for supplying power to a device, the circuit comprising: a detection resistor disposed on a power supply line; a current monitoring unit that compares a detected voltage that is a voltage drop across the detection resistor with a variable threshold voltage and asserts an overcurrent detection signal if the detected voltage exceeds the threshold voltage; and a control unit including a timer, wherein the control unit is switchable among (i) a first state where the threshold voltage is set to a first value is in accordance with a reference value for overcurrent protection, (ii) a second state where the threshold voltage is set to a second value that is greater than the first value, and (iii) a third state where the threshold voltage is set to a third value that is less than the first value, wherein the control unit is configured to: (a) in the first state, if the overcurrent detection signal is asserted, transition to the second state while initiating clocking by the timer; (b) in the second state, (i) if the overcurrent detection signal is asserted, transition to an overcurrent detection state, and (ii) if the overcurrent detection signal remains negated for a predetermined first time period, transition to the third state while initiating clocking by the timer; and (c) in the third state, (i) if the overcurrent detection signal is asserted, transition to the overcurrent detection state, and (ii) if the overcurrent detection signal remains negated for a predetermined second time period, transition to the first state.

2. The circuit of claim 1, further comprising: a switch disposed on the power supply line in series to the detection resistor, wherein the control unit turns off the switch in the overcurrent detection state.

3. The circuit of claim 1, wherein the host is compliant with a universal serial bus power delivery (USB-PD) specification.

4. A host compliant with a USB-PD specification, the host comprising: a detection resistor and a switch disposed on a power supply line in series to each other; a USB-PD controller that controls the switch and negotiates a bus voltage and a supply current to be supplied via the power supply line, with a device compliant with the USB-PD specification via the power supply line; a converter that has an output terminal connected to the power supply line and generates the bus voltage; and a converter controller that controls the converter so that a voltage level determined by the negotiation is output, wherein the converter controller comprises a current monitoring unit that compares a detected voltage that is a voltage drop across the detection resistor with a variable threshold voltage and asserts an overcurrent detection signal if the detected voltage exceeds the threshold voltage, and wherein the USB-PD controller comprises a timer and is switchable among (i) a first state where the threshold voltage is set to a first value that is in accordance with a reference value for overcurrent protection, (ii) a second state where the threshold voltage is set to a second value that is greater than the first value by a predetermined percentage, and (iii) a third state where the threshold voltage is set to a third value that is less than the first value by a predetermined percentage, wherein the USB-PD controller is configured to: (a) in the first state, if the overcurrent detection signal is asserted, transition to the second state while initiating clocking by the timer; (b) in the second state, (i) if the overcurrent detection signal is asserted, turn off the switch, and (ii) if the overcurrent detection signal remains negated for a predetermined first time period, transition to the third state while initiating clocking by the timer; and (c) in the third state, (i) if the overcurrent detection signal is asserted, turn off the switch, and (ii) if the overcurrent detection signal remains negated for a predetermined second time period, transition to the first state.

5. A method of detecting an overcurrent performed in a host compliant with a USB specification, the method comprising: setting an overcurrent threshold value to a first value that is a reference value; comparing a supply current flowing through a power supply line with the first value; setting the overcurrent threshold value to a second value that is larger than the reference value by a predetermined percentage while initiating clocking by a first timer if the supply current exceeds the threshold value; (i) determining an overcurrent state if the supply current exceeds the threshold value before a time counted by the first timer reaches a predetermined first time, and (ii) setting the overcurrent threshold value to a third value that is less than the reference value by a predetermined percentage while initiating clocking by a second timer if the supply current remains less than the threshold value for the first time; and (i) determining an overcurrent state if the supply current exceeds the threshold value before a time counted by the second timer reaches a predetermined second time, and (ii) setting the overcurrent threshold value to the first value, if the supply current remains less than the threshold value for the second time.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 describes a circuit diagram of a conventional overcurrent detection circuit.

(2) FIG. 2 depicts a circuit diagram of an overcurrent detection circuit according to one embodiment of the present disclosure.

(3) FIG. 3 illustrates a flowchart describing overcurrent detection by the overcurrent detection circuit shown in FIG. 2.

(4) FIG. 4 depicts a state-transition diagram of the overcurrent detection circuit shown in FIG. 2.

(5) FIGS. 5A to 5C are waveform diagrams showing overcurrent detection by the overcurrent detection circuit shown in FIG. 2.

(6) FIG. 6 describes a block diagram of a host employing the overcurrent detection circuit shown in FIG. 2.

(7) FIG. 7 is a perspective view of a note-type computer as an example of the host.

DETAILED DESCRIPTION

(8) Various embodiments of the present disclosure will be described below in detail with reference to the accompanying drawings. Throughout the drawings, the same or similar elements, members, and processes are denoted by the same reference numerals and redundant descriptions thereof may be omitted. The disclosed embodiments are not limited to the present disclosure, and are provided for the purpose of illustration, and all features and combinations thereof described in the embodiments should not be necessarily construed as describing the gist of the present disclosure.

(9) As used herein, the expression “a member A is connected with a member B” may mean that member A is physically and directly connected to member B, or that member A is connected to member B via another member without substantially affect the electrical connection or without harming the functionality or effects that may be achieved by the connection.

(10) Similarly, the expression “a member C is interposed between a member A and a member B” may indicate that the member A is directly connected to the member C or the member B is directly connected to the member C, and that the members are indirectly connected via another member without substantially affect the electrical connection or without harming the functionality or effects that may be achieved by the connections.

(11) FIG. 2 depicts a circuit diagram of an overcurrent detection circuit 100 according to one embodiment of the present disclosure. The overcurrent detection circuit 100 is installed in a USB host (source device) compliant with the USB-PD specification, and is disposed between an output terminal of a power source 102 for feeding power and a USB port 104. The overcurrent detection circuit 100 includes a power supply line 10, a detection resistor R1, a switch SW1, a current monitoring unit 20 and a control unit 30.

(12) The detection resistor R1 and the switch SW1 are connected in series on the power supply line (V.sub.BUS line) 10. A voltage drop Vs (hereinafter referred to as detected voltage) across the detection resistor R1 is generated in proportion to a supply current I.sub.OUT flowing through the power supply line 10. The switch SW1 may be configured with a field effect transistor (FET) switch.

(13) The current monitoring unit 20 compares the detected voltage Vs, i.e., the voltage drop across the detection resistor R1 with a variable threshold voltage V.sub.TH and asserts an overcurrent detection signal S1 if the detected voltage Vs exceeds the threshold voltage V.sub.TH.

(14) The control unit 30 includes a timer 32 and a state machine 34. The state machine 34 is able to switch between a first state φ1 to a third state φ3 and an overcurrent detection state φ4. The state machine 34 is configured to: (i) in the first state φ1, set the threshold voltage V.sub.TH of the current monitoring unit 20 to a first value V.sub.TH1 associated with a limit current I.sub.OC which is a reference value for overcurrent protection; (ii) in the second state φ2, set the threshold voltage V.sub.TH to a second value V.sub.TH2 greater than the first value V.sub.TH1 by a predetermined percentage α, i.e., V.sub.TH1×α/100, where α>100%; and (iii) in the third state φ3, set the threshold voltage V.sub.TH to a third value V.sub.TH3 less than the first threshold voltage V.sub.TH1 by a predetermined percentage β, i.e., V.sub.TH1×β/100, where β<100%. The control unit 30 outputs a control signal S2 indicative of the threshold voltage V.sub.TH of the current monitoring unit 20 in each of the states.

(15) The state machine 34 is also configured to: (a) in the first state φ1, upon the overcurrent detection signal S1 being asserted, transition to the second state and initiate clocking by the timer 32; (b) in the second state φ2, (i) upon the overcurrent detection signal S1 being asserted, transition to the overcurrent detection state φ4, and (ii) if the overcurrent detection signal S1 remains negated for a predetermined first time T.sub.IMAX, transition to the third φ3 state and initiate clocking by the timer 32; and (c) in the third state φ3, (i) upon the overcurrent detection signal S1 being asserted, transition to the overcurrent detection state φ4, and (ii) if the overcurrent detection signal S1 remains negated for a predetermined second time T.sub.ILO, transition to the first state φ1.

(16) In the overcurrent detection state φ4, the control unit 30 turns off the switch SW1. The configuration of the overcurrent detection circuit 100 has been described above. The operation of the overcurrent detection circuit 100 will be described in detail below.

(17) FIG. 3 illustrates a flowchart describing overcurrent detection by the overcurrent detection circuit 100 shown in FIG. 2. FIG. 4 depicts a state-transition diagram of the overcurrent detection circuit 100 shown in FIG. 2.

(18) When the overcurrent detection circuit 100 initiates an operation, the state machine 34 transitions to the first state φ1, in which V.sub.TH=V.sub.TH1 is set, and the overcurrent detection threshold value I.sub.TH becomes a limit value I.sub.OC, which is a reference value (S100). It is determined whether Vs is greater than V.sub.TH in step S102. If no (No in S102), the first state φ1 is maintained. If it is determined that Vs>V.sub.TH, i.e., I.sub.OUT>I.sub.OC (Yes in S102), the current monitoring unit 20 asserts an overcurrent detection signal S1 and the state machine 34 transitions to the second state φ2. In the second state φ2, V.sub.TH=V.sub.TH2 is set, and the overcurrent detection threshold value I.sub.TH becomes the current limit I.sub.MAX (S104). A timer 32 for counting a first time T.sub.IMAX (hereinafter referred to as T.sub.IMAX timer 32a) is initiated (S106).

(19) In the second state φ2, if it is determined that Vs>V.sub.TH, i.e., I.sub.OUT>I.sub.MAX (Yes in S108), the current monitoring unit 20 asserts an overcurrent detection signal S1 and the state machine 34 transitions to the overcurrent detection state φ4, such that an overcurrent protection process is carried out (S112). The overcurrent protection process may include turning off the switch SW1, interrupting the power source 102, notifying a microcomputer or a CPU of the overcurrent state, and so on.

(20) In the second state φ2, while the T.sub.IMAX timer 32a counts the first time T.sub.IMAX (No in S110), the state machine 34 monitors the overcurrent detection signal S1 (S108), and remains in the second state φ2 for Vs<V.sub.TH (No in S108). In the second state φ2, if the T.sub.IMAX timer 32a expires (times out) before the overcurrent detection signal S1 is asserted, i.e., the first time T.sub.IMAX elapses (Yes in S110), the state machine 34 transitions to the third state φ3.

(21) In the third state φ3, V.sub.TH=V.sub.TH3 is set, and the overcurrent detection threshold value I.sub.TH becomes the limit value I.sub.LO (S114). A timer 32 for counting a second time T.sub.ILO (hereinafter referred to as T.sub.ILO timer 32b) is initiated (S116).

(22) In the third state φ3, if it is determined that Vs>V.sub.TH, i.e., I.sub.OUT>I.sub.LO (Yes in S118), the current monitoring unit 20 asserts an overcurrent detection signal S1 and the state machine 34 transitions to the overcurrent detection state φ4, such that the overcurrent protection process is carried out (S112).

(23) In the third state φ3, while the T.sub.ILO timer 32b counts the second time T.sub.ILO (No in S120), the state machine 34 keeps monitoring the overcurrent detection signal S1 (S118), and remains in the third state φ3 while V.sub.s<V.sub.TH (No in S118). In the third state φ3, if the T.sub.ILO timer 32b expires (times out) before the overcurrent detection signal S1 is asserted, i.e., the second time T.sub.ILO elapses (Yes in S120), the state machine 34 transitions to the first state φ1.

(24) The basic operation of the overcurrent detection circuit 100 has been described above. An exemplary operation of the overcurrent detection circuit 100 will be described with reference to waveform diagrams.

(25) FIGS. 5A to 5C are waveform diagrams showing overcurrent detection by the overcurrent detection circuit 100 shown in FIG. 2. FIG. 5A shows waveforms when it is determined that no overcurrent occurs, and FIGS. 5B and 5C show waveforms when it is determined that an overcurrent occurs.

(26) Initially, reference is made to FIG. 5A. Prior to time t0, the state machine 34 is in the first state φ1. If the supply current I.sub.OUT exceeds the threshold value I.sub.TH=I.sub.OC at time t0, the state machine 34 transitions to the second state φ2, in which I.sub.TH=I.sub.MAX. In the second state φ2, if the first time T.sub.IMAX elapses while I.sub.OUT<I.sub.TH (I.sub.OUT<I.sub.MAX), the state machine 34 transitions to the third state φ3, in which I.sub.TH=I.sub.LO (at time t1). In the third state φ3, if the second time T.sub.ILO elapses while I.sub.OUT<I.sub.TH (I.sub.OUT<I.sub.LO), the state machine 34 returns to the first state φ1 (at time t2).

(27) Next, reference is made to FIG. 5B. Prior to time t0, the same operation is performed as in FIG. 5A. At time t0, the state machine 34 transitions to the second state φ2. In the second state φ2, if it is determined that I.sub.OUT>I.sub.TH (I.sub.OUT>I.sub.MAX) occurs at time t3 before the first time T.sub.IMAX elapses, the state machine 34 transitions to the overcurrent detection state φ4.

(28) Subsequently, reference is made to FIG. 5C. Prior to time t1, the same operation is performed as in FIGS. 5A and/or 5B. At time t1, the state machine 34 transitions to the third state φ3. In the third state φ3, if it is determined that I.sub.OUT>I.sub.TH (I.sub.OUT>I.sub.LO) occurs at time t4 before the second time T.sub.ILO elapses, the state machine 34 transitions to the overcurrent detection state φ4.

(29) The operation of the overcurrent detection circuit 100 has been described above.

(30) According to the overcurrent detection circuit 100, the overcurrent detection that meets the peak current requirement of the USB-PD specification is possible. Additionally, the overcurrent detection circuit 100 can be fully compliant with other specifications.

(31) More specifically, unlike the overcurrent detection circuit 100r shown in FIG. 1, which is unable to detect an overcurrent during the masking time, the overcurrent detection circuit 100 does not mask the overcurrent detection signal S1 and thus can securely detect an overcurrent state even during masking time. As such, the overcurrent detection circuit 100 can improve system stability.

(32) In addition, the threshold value of the current monitoring unit 20 may be set as desired by the control unit 30, and thus a precise current control is possible adaptively. As a result, power consumption can be saved.

(33) (Applications)

(34) Applications of the overcurrent detection circuit 100 will be described.

(35) FIG. 6 is a block diagram of a USB host 200 employing the overcurrent detection circuit 100 shown in FIG. 2. The USB host 200 is compliant with the USB-PD specification and is connected to a USB device 302 via a USB cable 300.

(36) The USB host 200 includes a power supply line 202, a USB port 203, a data line 204, a switch SW1, a detection resistor R1, a USB-PD controller 206, a converter 208, a converter controller 210, and a USB transceiver 212.

(37) The switch SW1 and the detection resistor R1 are connected in series on the power supply line 202.

(38) The USB-PD controller 206 negotiates a bus voltage V.sub.BUS and a supply current I.sub.OUT to be supplied via the power supply line 10, with a device (device in synchronization) 302 compliant with the USB-PD specification via the power supply line 202. The USB-PD controller 206 includes a logic unit 214, a communication unit 216, and a timer 232. The communication unit 216 is coupled with the power supply line 202 and communicates with the USB device 302 by superimposing a modulation signal on the bus voltage V.sub.BUS (the FSK scheme).

(39) The logic unit 214 controls the switch SW1. In addition, the logic unit 214 notifies the converter controller 210 of a set value of the bus voltage V.sub.BUS which is the result of the negotiation. The logic unit 214 corresponds to the state machine 34 shown in FIG. 2.

(40) An output terminal of the converter 208 is connected to the power supply line 202 to generate the bus voltage V.sub.BUS. The converter 208 may be an AC/DC converter that converts an AC voltage into a DC voltage, for example. Alternatively, the converter 208 may be a DC/DC converter that steps down or steps up a battery voltage or a DC voltage from an external adaptor, for example. The topology of the converter 208 is not particularly limited herein.

(41) The converter controller 210 controls the converter 208 so that the converter 208 outputs the voltage level determined by the negotiation. Again, the configuration of the converter controller 210 is not particularly limited herein, and any suitable known converter controller may be employed.

(42) The converter controller 210 includes a current monitoring unit 220 that compares the detected voltage Vs, i.e., the voltage drop across the detection resistor R1 with a variable threshold voltage V.sub.TH and asserts an overcurrent detection signal S1 if the detected voltage Vs exceeds the threshold voltage V.sub.TH. The current monitoring unit 220 corresponds to the current monitoring unit 20 shown in FIG. 2.

(43) The USB-PD controller 206 includes a timer 232. The logic unit 214 has the functionality of the state machine 34 shown in FIG. 2 and is able to switch between a first state φ1 to a third state φ3 and an overcurrent detection state φ4. In addition, the logic unit 214 is able to transition between the first state φ1 to the third state φ3 and the overcurrent detection state φ4 based on the same conditions as the state machine 34. The logic unit 214 turns off the switch SW1 in the overcurrent detection state φ4.

(44) The configuration of the USB host 200 has been described above. The operation of the USB host 200 will be described in detail below. As a result of the negotiation between the USB-PD controller 206 and the USB device 302, overcurrent protection conditions are determined, as well as the capacity of the bus voltage V.sub.BUS or the supply current I.sub.OUT.

(45) The overcurrent protection conditions contain the following information: The ratio α of the limit value I.sub.MAX to the reference value I.sub.OC (=I.sub.MAX/I.sub.OC) The ratio β of the limit value I.sub.LO to the reference value I.sub.OC (=I.sub.LO/I.sub.OC) The first time T.sub.IMAX The duty ratio γ between the second time T.sub.ILO and the first time T.sub.IMAX

(46) These conditions may be expressed in two-bit data S3, for example:
(S3=00) α=100%, β=N/A, T.sub.IMAX=1 ms,
(S3=01) α=130%, β=70%, T.sub.IMAX=1 ms, T.sub.ILO=1 ms, (γ=50%)
(S3=10) α=150%, β=83%, T.sub.IMAX=1 ms, T.sub.ILP=3 ms, (γ=25%)
(S3=11) α=200%, β=95%, T.sub.IMAX=1 ms, T.sub.ILO=19 ms (γ=5%)
where the abbreviation N/A stands for “Not Available,” which means there is no setting.

(47) According to this USB host 200, by employing the overcurrent detection circuit 100, it is possible to support the peak current requirement of the USB-PD specification.

(48) FIG. 7 shows a perspective view of a note-type computer 400 as an example of the USB host 200.

(49) A secondary battery 402 is, for example, a lithium-ion battery, a nickel-hydrogen battery, etc., and outputs a battery voltage V.sub.BAT. The converter 208 and the converter controller 210 steps up or steps down the battery voltage V.sub.BAT and generates the bus voltage V.sub.BUS. To the USB port 203, a device (not shown) is connected via a USB cable.

(50) The present disclosure has been described with reference to the exemplary embodiments.

(51) It should be understood by those skilled in the art that the above embodiments are merely examples and a variety of modifications may be made to combinations of the elements and processes disclosed herein, and that such modifications also fall within the scope of the present disclosure. Hereinafter, such modifications are described.

(52) (First Modification)

(53) In the above exemplary embodiments, the control unit 30 includes the state machine 34 as a part of it. However, the configuration of the control unit 30 is not limited thereto. Instead of the state machine 34, other architectures such as a combination of software and hardware, etc. may be employed.

(54) (Second Modification)

(55) Although the switch SW1 is connected between the detection resistor R1 and the USB port 104 in the above-described embodiments, the present disclosure is not limited thereto. The switch SW1 may be connected between the detection resistor R1 and the power source 102. Alternatively, if the power source 102 is an AC/DC converter or a DC/DC converter, a switching transistor included in the power source of the converters may also be served as the switch SW1. Or, if the power source 102 is a low drop output (LDO), the output transistor (power transistor) may also be used as the switch SW1.

(56) (Third Modification)

(57) In the above exemplary embodiment, as shown in FIG. 6, the USB host 200 and the USB device 302 communicate with each other by superimposing a modulation signal on the bus voltage V.sub.BUS (the FSK scheme) according to the USB-PD specification. However, the present disclosure is not limited thereto. The present disclosure can also be compliant with other future specifications. For example, the USB host 200 may communicate with the USB device 302 via a dedicated communication channel installed separately from the power supply line 202.

(58) (Fourth Modification)

(59) The note-type computer 400 has been described as an application of the overcurrent detection circuit 100. However, the USB host 200 may include a mobile phone terminal, a tablet terminal, a digital camera, a digital video camera, a television receiver etc.

(60) According to some aspects of the present disclosure, overcurrent detection that meets the peak current requirement of the USB-PD specification is possible

(61) While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the disclosures. Indeed, the novel methods and apparatuses described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the disclosures. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the disclosures.