Energy accumulator emulator and method for emulation of an energy accumulator

Abstract

Various aspects of the present disclosure are directed to energy accumulator emulators. In one embodiment, an energy accumulator emulator is disclosed including a DC-to-DC converter having a number of power switches, a control unit that calculates a reference current from electrical variables of the DC-to-DC converter, and a battery model connected to the control unit. The battery model receives and processes the reference current and communicates a referenced voltage to the control unit. The control unit includes a voltage controller that processes the reference voltage and controls a current, on the basis of which the control unit controls the power switches via switching pulses to control an output voltage. The energy accumulator emulator further includes a PPPC unit that is connected to the voltage controller. The PPPC unit provides a number of pulse patterns, selects a pulse pattern, and controls the power switches according to the selected pulse pattern.

Claims

1. An energy accumulator emulator comprising: a DC-to-DC converter including a number of power switches, the DC-to-DC converter configured and arranged to provide an output voltage and an output-side load current; a control unit configured and arranged to calculate a reference current from electrical variables of the DC-to-DC converter; a battery model connected to the control unit and configured and arranged to obtain and process the reference current from the control unit and to provide the control unit with a reference voltage, wherein the control unit includes a voltage controller configured and arranged to processes the reference voltage and controls a current, on a basis of which the control unit is further configured and arranged to control the power switches via switching pulses in order to control the output voltage; and a Predictive Pulse Pattern Control Unit (PPPC unit) connected to the voltage controller, the PPPC unit including a PPPC controller, a pulse generator and a selection unit, the selection unit is configured and arranged to provide a number of pulse patterns, and the PPPC unit is configured and arranged to select a pulse pattern of the number of pulse patterns of the selection unit on a basis of a current predefined by the voltage controller and to control the power switches via the pulse generator by means of the switching pulses according to the selected pulse pattern.

2. The energy accumulator emulator of claim 1, wherein the PPPC controller is further configured and arranged to freely select the pulse pattern from the number of pulse patterns, thereby improving higher dynamics and accuracy in the control of the output voltage.

3. The energy accumulator emulator of claim 1, wherein the PPPC unit is further configured and arranged to select switching times of the selected pulse patterns of the power switches on a basis of a current.

4. The energy accumulator emulator of claim 1, wherein the DC-to-DC converter is a four-phase synchronous converter further including parallel half bridges and associated chokes, wherein a switching behavior of a half-bridge is configured and arranged to control a phase current of an associated one of the chokes.

5. The energy accumulator emulator of claim 4, wherein the half bridges of the DC-to-DC converter each include an upper power switch, a lower power switch and one or more freewheeling diodes.

6. The energy accumulator emulator of claim 5, wherein the upper and lower switches of a respective half bridge are configured and arranged to switch in an alternating order to prevent a short circuit.

7. The energy accumulator emulator of claim 4, wherein the sum of the phase currents at the chokes is the output-side load current.

8. The energy accumulator emulator of claim 4, wherein the control unit is further configured and arranged to receive string currents, the output-side load current, and the output voltage as input variables, and uses a combination of inner and outer control loops to control the output voltage.

9. The energy accumulator emulator of claim 8, wherein the outer control loop includes the voltage controller superimposed on an inner control loop which is formed by the PPPC unit, and the voltage controller is configured and arranged to receive the reference voltage from the battery model and the output voltage and the output-side load current from the battery emulator, and controls the current.

10. The energy accumulator emulator of claim 1, wherein each of the number of pulse patterns has a sequence of switching pulses that covers an entire possible range of the output voltage.

11. The energy accumulator emulator of claim 1, wherein each of the switching pulses switches only once from active to inactive and from inactive to active during a given switching period.

12. The energy accumulator emulator of claim 1, wherein a first pulse pattern of the number of pulse patterns includes switching pulses timed so that no active phase or at the most one active period occurs at the same time during a given phase, a second pulse pattern of the number of pulse patterns includes switching pulses with one or two phases with simultaneously active periods, a third pulse pattern of the number of pulse patterns includes switching pulses with two or three phases with simultaneously active periods, and a fourth pulse pattern of the number of pulse patterns includes switching pulses with three or four phases with simultaneously active periods.

13. The energy accumulator emulator of claim 1, wherein the PPPC controller is configured and arranged to estimate which of the number of pulse patterns provided by the selection unit should be selected, and corresponding switching times in order to minimize the deviation of the generated current from the current specified by the voltage controller at a next sampling time.

14. A method for emulation of an energy accumulator device comprising the steps of: controlling output voltage of a DC-to-DC converter via a control unit; calculating a reference current, at the control unit, from electrical variables of the DC-to-DC converter; communicating the reference current to a battery model; processing the reference current at the battery model; calculating reference voltage from the reference current at the battery model; transmitting the reference current from the battery model to a voltage controller; processing the reference voltage at the voltage controller; and controlling a current (i1*) via the voltage controller, on a basis of which the control unit controls power switches via switching pulses to control the output voltage; selecting a pulse pattern from a number of predefined pulse pattern on a basis of a current specified by the voltage controller via a Predictive Pulse Pattern Control Unit (PPPC unit); and controlling the power switches of the DC-to-DC converter according to the selected pulse pattern via the PPPC unit, and thereby controlling the output voltage.

15. The method according to claim 14, further including selecting switching times of the selected pulse patterns of the power switches on a basis of a current at the PPPC unit.

16. The method according to claim 14, further including supplying the output voltage to an electrical load.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The present invention is described in greater detail below on the basis of FIGS. 1 to 3b, which show advantageous exemplary embodiments of the invention in a schematic and non-limiting manner. Figures:

(2) FIG. 1 shows an energy accumulator emulator,

(3) FIG. 2 shows a PCCC unit,

(4) FIG. 3a shows a selection of pulse patterns,

(5) FIG. 3b shows values of the phase currents estimated from them.

DETAILED DESCRIPTION

(6) FIG. 1 discloses a possible configuration of an energy accumulator emulator which provides an electrical load 5, for example a (partially) electrical drive train of a vehicle, with an output voltage v.sub.2 or a load current i.sub.L. The electrical load 5 is modeled here, for example, by a load capacitance C.sub.L and a load resistor R.sub.L. For this purpose, for example, the load current i.sub.L and the output voltage v.sub.2 are determined and provided to a control unit 2, which in turn calculates a reference current i.sub.2R for a battery model 3 from the load current i.sub.L and provides it to the battery model 3. This conversion depends, of course, on the type of battery model 3. The battery model 3 calculates a reference voltage v.sub.2R from the load current i.sub.L and supplies it to the control unit 2, which, on this basis, controls the power switches S.sub.o1, S.sub.o2, S.sub.o3, S.sub.o4, S.sub.u1, S.sub.u2, S.sub.u3, S.sub.u4 of a well-known multi-phase DC-to-DC converter 1 via the binary switching pulses S.sub.1, S.sub.2, S.sub.3, S.sub.4.

(7) A basic exemplary structure of a battery model 3 can be found, for example, in AT 510 998 A2 or AT 513 676 A2.

(8) The DC-to-DC converter 1 generates the required output voltage v.sub.2 and provides it to the load 5. On the input side, for example, a three-phase AC voltage is rectified by means of a rectifier 4 and a smoothing capacitor Co to form a DC voltage v.sub.0. The smoothing capacitor Co is assumed to be sufficiently large so that the dynamics of the rectifier 4 can be neglected, and the DC voltage v.sub.0 can be assumed to be constant. The DC voltage v.sub.0 supplies the DC-to-DC converter 1.

(9) In this exemplary embodiment, the DC-to-DC converter 1 is in the form of a four-phase synchronous converter, consisting of parallel half bridges HB.sub.1, HB.sub.2, HB.sub.3, HB.sub.4 and associated chokes, L1, L2, L3, L4, whose phase currents i.sub.L1, i.sub.L2, i.sub.L3, i.sub.L4 are each controlled by the switching behavior of the associated half-bridge HB.sub.1, HB.sub.2, HB.sub.3, HB.sub.4. The half bridges HB.sub.1, HB.sub.2, HB.sub.3, HB.sub.4 each consist of an upper power switch S.sub.o1, S.sub.o2, S.sub.o3, S.sub.o4 and a lower power switch S.sub.u1, S.sub.u2, S.sub.u3, S.sub.u4 and any associated freewheeling diodes D.sub.o1, D.sub.u1, D.sub.o2, D.sub.u2, D.sub.o3, D.sub.u3, D.sub.o4, D.sub.u4. One half bridge HB.sub.1, HB.sub.2, HB.sub.3, HB.sub.4 and one inductor L.sub.1, L.sub.2, L.sub.3, L.sub.4 each are thus provided per phase, the inductors L.sub.1, L.sub.2, L.sub.3, L.sub.4 being connected to a half bridge HB.sub.1, HB.sub.2, HB.sub.3, HB.sub.4 between the upper power switches S.sub.o1, S.sub.o2, S.sub.o3, S.sub.o4 on the one hand and the lower power switches S.sub.u1, S.sub.u2, S.sub.u3, S.sub.o4 on the other hand and furthermore to one another on the output side. The output current i.sub.1 is thus the sum of the phase currents i.sub.L1, i.sub.L2, i.sub.L3, i.sub.L4. Ohmic resistances of the chokes L.sub.1, L.sub.2, L.sub.3, L.sub.4 are not shown in FIG. 1 for the sake of simplicity but can also be taken into account. In addition, there is usually an output-side smoothing capacitor C.sub.2 which, together with the chokes L.sub.1, L.sub.2, L.sub.3, L.sub.4 and the output inductance L, forms an output filter of the synchronous converter. This filter receives the output current i.sub.1 or an intermediate voltage v.sub.1 at the input and also supplies an output voltage v.sub.2 and thus a load current i.sub.L. The DC-to-DC converter 1 can, of course, also be configured as a different embodiment, for example with fewer or more phases, etc.

(10) The power switches S.sub.o1, S.sub.o2, S.sub.o3, S.sub.o4, S.sub.u1, S.sub.u2, S.sub.u3, S.sub.u4 of the half bridges are controlled by a control unit 2 in order to set the desired output voltage v.sub.2, which results in the required load current i.sub.L. The upper power switches S.sub.o1, S.sub.o2, S.sub.o3, S.sub.o4 and the respectively associated lower power switches S.sub.u1, S.sub.u2, S.sub.u3, S.sub.u4 of a half bridge HB.sub.1, HB.sub.2, HB.sub.3, HB.sub.4 are switched in an alternating order to prevent a short circuit. The basic control of half bridges HB.sub.1, HB.sub.2, HB.sub.3, HB.sub.4 of a synchronous converter for generating the load current i.sub.L can be assumed as known.

(11) Usually, prior art provides for an equally well known pulse width modulation (PWM) in the control unit 2 in order to use the duty cycle of the power switches S.sub.o1, S.sub.o2, S.sub.o3, S.sub.o4, S.sub.u1, S.sub.u2, S.sub.u3, S.sub.u4 to set the output voltage v.sub.2 or the desired load current i.sub.L via the phase currents i.sub.L1, i.sub.L2, i.sub.L3, i.sub.L4. Since a PWM switches with every sampling step, this constraint also limits the sampling rate and thus the controller bandwidth. This constraint leads to poor dynamics in the control of such DC-to-DC converters 1, which means that it is often not possible to react quickly enough to interferences or transient switching processes of the load 5.

(12) For this reason, the control unit 2 does not control the power switches S.sub.o1, S.sub.o2, S.sub.o3, S.sub.o4, S.sub.u1, S.sub.u2, S.sub.u3, S.sub.u4 on the basis of a PWM but, according to the invention, via a predictive pulse pattern control (PPPC). The control unit 2 also receives the string currents i.sub.L1, i.sub.L2, i.sub.L3, i.sub.L4 (which can be measured) as well as the current load current i.sub.L (which can be measured) and the current output voltage v.sub.2 (which can be measured) as input variable. In order to achieve a faster and more precise adjustment of the output voltage v.sub.2, a combination of an inner and an outer control loop as shown in FIG. 2 is used in the control unit 2.

(13) The outer control loop has a voltage controller VR, which is superimposed on an inner control loop formed by a PPPC unit 20. The voltage controller VR receives the reference voltage v.sub.2R from the battery model 3 as well as further electrical variables of the battery emulator (for example the phase currents i.sub.L1, i.sub.L2, i.sub.L3, i.sub.L4, the output voltage v.sub.2, the load current i.sub.L, etc.) and controls a current i.sub.1* on this basis. Any suitable controller can be implemented for this purpose. A possible control strategy for the voltage controller VR is a model-predictive controller (MPC), which minimizes the error between the actual output current i.sub.1 (which is measured, for example) and the current i.sub.1* set by the voltage controller VR across the prediction horizon N.sub.P In addition, a system-related limitation of the output current i.sub.1 can be taken into account in the MPC as well. The variables required for the voltage controller VR are either measured and/or estimated on the basis of an observer, for example in the form of a Kalman filter) from measurable variables (preferably i.sub.1, i.sub.2, v.sub.1, v.sub.2, i.sub.L1, i.sub.L2, i.sub.L3, i.sub.L4, for example the load current i.sub.L).

(14) In turn, the PPPC unit 20 consists of a PPPC controller 201, a pulse generator 202 and a selection unit 200. The pulse generator 202 controls the power switches S.sub.o1, S.sub.o2, S.sub.o3, S.sub.o4, S.sub.u1, S.sub.u2, S.sub.u3, S.sub.u4 via switching pulses S.sub.1, S.sub.2, S.sub.3, S.sub.4 in order to set the desired phase currents i.sub.L1, i.sub.L2, i.sub.L3, i.sub.L4 and thus the desired load current i.sub.L or the desired output voltage v.sub.2. The pulse generator 202 can select from various predefined pulse patterns A, B, C, D made available by the selection unit 200.

(15) The PPPC controller 20 processes the current i.sub.1* specified by the voltage controller VR and selects a suitable pulse pattern A, B, C, D provided by the selection unit 200 and the suitable switching times t.sub.1, t.sub.2, t.sub.3, t.sub.4, t.sub.5, t.sub.6, t.sub.7, t.sub.k+1 of the pulse patterns A, B, C, D, with which the pulse generator 202 controls the power switches S.sub.o1, S.sub.o2, S.sub.o3, S.sub.o4, S.sub.u1, S.sub.u2, S.sub.u3, S.sub.u4 via switching pulses S.sub.1, S.sub.2, S.sub.3, S.sub.4 in accordance with these pulse patterns A, B, C, D with corresponding switching times t.sub.1, t.sub.2, t.sub.3, t.sub.4, t.sub.5, t.sub.6, t.sub.7, t.sub.k+1.

(16) Each pulse pattern A, B, C, D generates the switching pulses S.sub.1, S.sub.2, S.sub.3, S.sub.4 of each half bridge HB.sub.1, HB.sub.2, HB.sub.3, HB.sub.4 a sequence of switching pulses S.sub.1, S.sub.2, S.sub.3, S.sub.4 which ideally covers the entire possible range of the output voltage v.sub.2. Thus, between two times t.sub.k, t.sub.k+1, which preferably correspond to a sampling period T.sub.P, two switching actions per period, i.e., two changes from active to inactive, of the respective power switches S.sub.o1, S.sub.o2, S.sub.o3, S.sub.o4, S.sub.u1, S.sub.u2, S.sub.u3, S.sub.u4 are made possible, with the switching actions taking place at the freely selectable switching times t.sub.k, t.sub.1, t.sub.2, t.sub.3, t.sub.4, t.sub.5, t.sub.6, t.sub.7, t.sub.k+1. The number of switching times can be freely selected. As usual, the required output current i.sub.1 is thus generated as the sum of the phase currents i.sub.L1, i.sub.L2, i.sub.L3, i.sub.L4. By using a pulse generator 202, the switching pulses S.sub.1, S.sub.2, S.sub.3, S.sub.4 can be freely selected in accordance with the predetermined pulse patterns A, B, C, D, and the switching times t.sub.k, t.sub.1, t.sub.2, t.sub.3, t.sub.4, t.sub.5, t.sub.6, t.sub.7, t.sub.k+1 can be freely used as well. This results in an independence from a fixed sampling rate, which leads to high dynamics and flexibility.

(17) In the present embodiment, four pulse patterns A, B, C, D are defined on the selection unit 200. The pulse patterns A, B, C, D have a specific number of switching processes or switches from active periods to inactive periods or vice-versa per switching period [t.sub.k, t.sub.k+1], i.e., here for example per prediction interval T.sub.P. This means that each switching pulse S.sub.1, S.sub.2, S.sub.3, S.sub.4 switches only once from active to inactive and from inactive to active in a given switching period [t.sub.k, t.sub.k+1]. The power switches S.sub.o1, S.sub.o2, S.sub.o3, S.sub.o4, S.sub.u1, S.sub.u2, S.sub.u3, S.sub.u4 of the half bridges HB.sub.1, HB.sub.2, H.sub.B3, H.sub.B4 are controlled via the switching pulses S.sub.1, S.sub.2, S.sub.3, S.sub.4 in such a way that different phase currents i.sub.L2, i.sub.L3, i.sub.L4 are generated in the chokes L.sub.1, L.sub.2, L.sub.3, L.sub.4. As mentioned, these phase currents i.sub.L2, i.sub.L3, i.sub.L4 ultimately provide the current i.sub.1 with which subsequently an output voltage v.sub.2 and a load current i.sub.L are produced.

(18) FIG. 3a shows an exemplary selection of four pulse patterns A, B, C, D. The pulse pattern A has switching pulses S.sub.1, S.sub.2, S.sub.3, S.sub.4 in such a way that no active phase or at the most one active period occurs at the same time during a given phase. The pulse pattern B has switching pulses S.sub.1, S.sub.2, S.sub.3, S.sub.4 with one or two phases with simultaneously active periods, the pulse pattern C switching pulses S.sub.1, S.sub.2, S.sub.3, S.sub.4 with two or three phases with active periods and the pulse pattern D switching pulses S.sub.1, S.sub.2, S.sub.3, S.sub.4 with three or four phases with active periods. These pulse patterns A, B, C, D of the switching signals S.sub.1, S.sub.2, S.sub.3, S.sub.4, with which the power switches S.sub.o1, S.sub.o2, S.sub.o3, S.sub.o4, S.sub.u1, S.sub.u2, S.sub.u3, S.sub.u4 are controlled, are shown in a table in FIG. 3a. This results in a potential selection of output currents i.sub.1 which can be achieved at the next sampling time t.sub.k+1. The pulse patterns A, B, C, D allow for different output currents i.sub.1 depending on the number of periods that are active at the same time. The pulse pattern D can, for example, potentially achieve a greater output current i.sub.1 than the pulse pattern A. The PPPC controller 201 thus estimates which of these pulse patterns A, B, C, D provided by the selection unit 200 must be selected with which switching times t.sub.k, t.sub.1, t.sub.2, t.sub.3, t.sub.4, t.sub.5, t.sub.6, t.sub.7, t.sub.k+1 in order to minimize the deviation of the generated current i.sub.1 from the current i.sub.1*specified by the voltage controller VR given at the next sampling time t.sub.k+1.

(19) Only a pulse pattern A, B, C, D can generally be selected, for example, that approximates the generated output current i.sub.1 to the current i.sub.1* specified by the voltage controller VR, i.e., whose possible value range (which is specified by the different possible switching times t.sub.k, t.sub.1, t.sub.2, t.sub.3, t.sub.4, t.sub.5, t.sub.6, t.sub.7, t.sub.k+1) contains the specified current i.sub.1*. Furthermore, there is an additional degree of freedom with respect to the switching times t.sub.k, t.sub.1, t.sub.2, t.sub.3, t.sub.4, t.sub.5, t.sub.6, t.sub.7, t.sub.k+1 in order to set the output current i.sub.1 at the time t.sub.k+1. To determine the switching times t.sub.k, t.sub.1, t.sub.2, t.sub.3, t.sub.4, t.sub.5, t.sub.6, t.sub.7, t.sub.k+1 for the selected pulse patterns A, B, C, D, an optimization problem can be posed to determine the optimal switching times t.sub.k, t.sub.1, t.sub.2, t.sub.3, t.sub.4, t.sub.5, t.sub.6, t.sub.7, t.sub.k+1 for the given output current i.sub.1*. For this purpose, a cost function J.sub.K as a function of the j switching times and the output current i.sub.1, and possibly other variables, can be applied, i.e., J.sub.K=f(t.sub.j, i.sub.1*, . . . ). This cost function J.sub.K evaluates the deviation of the assigned output current i.sub.1* and of the generated output current i.sub.1 and may with regard to the switching times t.sub.1, t.sub.2, t.sub.3, t.sub.4, t.sub.5, t.sub.6, t.sub.7 (with t.sub.k, t.sub.k+1 being specified and unchangeable) be optimized, usually minimized, i.e., t=argmin|.sub.tJ.sub.K, with the switching time vector t, which contains the j switching times. For this purpose, a suitable termination criterion can be determined, for example when a deviation threshold or a number of iterations is not achieved. This results in an optimal approximation of the given output current i.sub.1* by the pulse pattern A, B, C, D.

(20) FIG. 3b shows the estimated phase currents i.sub.L1, i.sub.L2, i.sub.L3, i.sub.L4 on the basis of the pulse patterns A, B, C, D and the switching times t.sub.k, t.sub.1, t.sub.2, t.sub.3, t.sub.4, t.sub.5, t.sub.6, t.sub.7, t.sub.k+1 and the resulting estimated output current i.sub.1. The different switching times t.sub.1, t.sub.2, t.sub.3, t.sub.4, t.sub.5, t.sub.6, t.sub.7 are shown.

(21) By selecting the pulse patterns A, B, C, D and the associated switching times t.sub.1, t.sub.2, t.sub.3, t.sub.4, t.sub.5, t.sub.6, t.sub.7, t.sub.k+1, the PPPC controller can, in contrast with a customary FCS-MPC, estimate the expected values of the phase currents i.sub.L1, i.sub.L2, i.sub.L3, i.sub.L4 with variable switching times t.sub.1, t.sub.2, t.sub.3, t.sub.4, t.sub.5, t.sub.6, t.sub.7. On the basis of this estimate, the switching signals S.sub.1, S.sub.2, S.sub.3, S.sub.4 that minimize an expected error can be generated, which leads to higher accuracy and dynamics.