Power supply switching circuit and semiconductor device

Abstract

To provide a power supply switching circuit which avoids an increase in current consumption. A power supply switching circuit includes MOS transistors provided between power supply input terminals and an output terminal, which have gates connected to each other and backgates connected to each other and are connected in series.

Claims

1. A power supply switching circuit which switches power supplies of a semiconductor device supplied with the power supplies to a plurality of power supply input terminals and outputs the switched power supply to an output terminal, comprising: respective MOS transistors provided between the power supply input terminals and the output terminal, said respective MOS transistors connected to an input terminal of each respective power supply having gates directly connected to each other, and backgates connected to each other and being connected in series, respectively, and the gate of each of the respective MOS transistors is directly connected to the output terminal.

2. The power supply switching circuit according to claim 1, wherein the gate of the respective MOS transistor is connected to input terminal of another power supply.

3. A semiconductor device equipped with the power supply switching circuit according to claim 1.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a circuit diagram illustrating a power supply switching circuit of the present embodiment;

(2) FIG. 2 is a circuit diagram illustrating another example of the power supply switching circuit of the present embodiment;

(3) FIG. 3 is a circuit diagram illustrating a related art power supply switching circuit; and

(4) FIG. 4 is a sectional structure diagram of a PN junction element of a related art power supply switching circuit.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

(5) A power supply switching circuit of the present embodiment will hereinafter be described with reference to the accompanying drawings.

(6) FIG. 1 is a circuit diagram illustrating a power supply switching circuit of the present embodiment.

(7) The power supply switching circuit of the present embodiment is equipped with a main power supply input terminal 200 supplied with a voltage V0 of a main power supply, a sub power supply input terminal 201 supplied with a voltage V1 of a sub power supply, MOS transistors 100, 101, 110 and 111, and an output terminal 204 which outputs a voltage Vout.

(8) The MOS transistor 100 has a drain connected to the main power supply input terminal 200, and a source and a backgate connected to each other. The MOS transistor 101 has a gate and a drain connected to a gate of the MOS transistor 100 and the output terminal 204, and a source and a backgate connected to the source and backgate of the MOS transistor 100. The MOS transistor 110 has a drain connected to the sub power supply input terminal 201, and a source and a backgate connected to each other. The MOS transistor 111 has a gate and a drain connected to a gate of the MOS transistor 110 and the output terminal 204, and a source and a backgate connected to the source and backgate of the MOS transistor 110.

(9) The operation of the power supply switching circuit of the present embodiment will next be described.

(10) Since the MOS transistor 100 is brought to an on state in a normal operating state in which the voltage V0 is higher than the voltage V1, a drain voltage VA becomes substantially equal to the voltage V0. Since a source voltage (voltage VA) is substantially equal to the voltage V0, the MOS transistor 101 is brought to an on state, so that the voltage V0 of the main power supply is supplied to the output terminal 204.

(11) Here, since V0≈VA, no forward bias voltage is applied to a PN junction element between the drain and backgate of the MOS transistor 100. Thus, since a PNP type bipolar element in which the PN junction element between the drain and backgate of the MOS transistor 100 is assumed to be an emitter and a base, and a P region 209 of a substrate is assumed to be a collector, is not turned on, no collector current flows. Thus, an increase in current consumption of the power supply switching circuit does not occur.

(12) On the other hand, since in a path of the sub power supply, the MOS transistor 110 has a gate voltage being apparently higher than a source voltage, and a PN junction element between the drain and backgate of the MOS transistor 110 is apparently reverse-biased, no current flows into the MOS transistor 110. Thus, it becomes possible to suppress inflow current into the sub power supply input terminal 201, i.e., the sub power supply.

(13) Since the MOS transistor 110 is brought to an on state in a backup operating state in which the voltage V0 is lower than the voltage V1, a drain voltage VB becomes substantially equal to the voltage V1. The MOS transistor 111 is brought to an on state because a source voltage (voltage VB) is substantially equal to the voltage V1, so that the output terminal 204 is supplied with the voltage V1 of the sub power supply.

(14) Here, since V0≈VA, no forward bias voltage is applied to the PN junction element between the drain and backgate of the MOS transistor 110. Thus, since a PNP type bipolar element in which the PN junction element between the drain and backgate of the MOS transistor 110 is assumed to be an emitter and a base, and the P region 209 of the substrate is assumed to be a collector, is not turned on, no collector current flows. Thus, an increase in current consumption of the power supply switching circuit does not occur.

(15) On the other hand, since in a path of the main power supply, the MOS transistor 100 has a gate voltage being apparently higher than a source voltage, and the PN junction element between the drain and backgate of the MOS transistor 100 is apparently reverse-biased, no current flows into the MOS transistor 100. Thus, it becomes possible to suppress inflow current into the main power supply input terminal 200, i.e., the main power supply.

(16) According to the power supply switching circuit of the present embodiment, as described above, it is possible to provide a power supply switching circuit low in current consumption. Further, there is provided a power supply switching circuit which takes into consideration even the suppression of inflow current into each power supply.

(17) Incidentally, although the circuit of FIG. 1 has been described in the above by way of example under the presumption that it is the power supply switching circuit for the main power supply and the sub power supply, it is possible to obtain an effect similarly even with respect to three or more power supplies. For example, as with the MOS transistors 100 and 101 for the main power supply, transistors may similarly be provided in other power supplies.

(18) Further, although the gate voltage of each transistor has been described as being supplied by the output terminal 204 of the power supply switching circuit, the gate of the transistor in the path which supplies power may be supplied with a voltage lower than the output of the power supply switching circuit, and the gate of the transistor in the path which does not supply power may be supplied with a voltage higher than the output of the power supply switching circuit. As illustrated in FIG. 4, for example, the gate of the transistor may be connected to the other input terminal.