Quality evaluation method for silicon wafer, and silicon wafer and method of producing silicon wafer using the method

Abstract

After determining the size of oxygen precipitates and the residual oxygen concentration in a silicon wafer after heat treatment performed in a device fabrication process; the critical shear stress τ.sub.cri at which slip dislocations are formed in the silicon wafer in the device fabrication process is determined based on the obtained size of the oxygen precipitates and residual oxygen concentration; and the obtained critical shear stress τ.sub.cri and the thermal stress τ applied to the silicon wafer in the heat treatment of the device fabrication process are compared, thereby determining that slip dislocations are formed in the silicon wafer in the device fabrication process when the thermal stress τ is equal to or more than the critical shear stress τ.sub.cri, or determining that slip dislocations are not formed in the silicon wafer in the device fabrication process when the thermal stress τ is less than the critical shear stress τ.sub.cri.

Claims

1. A quality evaluation method for a silicon wafer, comprising the steps of: determining the size of oxygen precipitates and the residual oxygen concentration in a silicon wafer after heat treatment performed in a device fabrication process; subsequently determining the critical shear stress τ.sub.cri at which slip dislocations are formed in the silicon wafer in the device fabrication process based on the obtained size of the oxygen precipitates and residual oxygen concentration; and comparing the obtained critical shear stress τ.sub.cri and the thermal stress τ applied to the silicon wafer in the heat treatment of the device fabrication process, whereby determining that slip dislocations are formed in the silicon wafer in the device fabrication process when the thermal stress τ is equal to or more than the critical shear stress τ.sub.cri, or determining that slip dislocations are not formed in the silicon wafer in the device fabrication process when the thermal stress τ is less than the critical shear stress τ.sub.cri, wherein the critical shear stress τ.sub.cri is given by Equation (A) below, where L: the size of the oxygen precipitate, C.sub.o: the residual oxygen concentration, T: the temperature of the heat treatment, G: the modulus of rigidity, b: the Burgers vector of the slip dislocations, and k: the Boltzmann constant
τ.sub.cir=0.16×(G.Math.b/L)+6.8×10.sup.−5×C.sub.O×exp(0.91 eV/kT) (A).

2. The quality evaluation method for a silicon wafer, according to claim 1, wherein the step of determining the size L of the oxygen precipitates and the residual oxygen concentration C.sub.o after heat treatment in the device fabrication process is performed by measuring the size of the oxygen precipitate and the residual oxygen concentration in the silicon wafer after the heat treatment performed on the silicon wafer in the device fabrication process.

3. The quality evaluation method for a silicon wafer, according to claim 1, wherein the step of determining the size L of the oxygen precipitates and the residual oxygen concentration C.sub.o after the heat treatment in the device fabrication process is performed by simulation calculation.

4. The quality evaluation method for a silicon wafer, according to claim 1, wherein the thermal stress τ is estimated based on the temperature distribution in the radial direction of the silicon wafer having been heated by being loaded into a heat treatment unit.

5. The quality evaluation method for a silicon wafer, according to claim 1, wherein the thermal stress τ is estimated by simulation calculations.

6. A method of producing a silicon wafer, comprising the steps of: growing a single crystal silicon ingot under the growing conditions allowing a silicon wafer to be obtained, which wafer is determined to have no slip dislocations formed in a device fabrication process by the quality evaluation method for a silicon wafer, according to claim 1; and subjecting the grown single crystal silicon ingot to a wafer processing process.

7. The method of producing a silicon wafer, according to claim 6, wherein the size of the oxygen precipitates after heat treatment in the device fabrication process is 10 nm or more and 150 nm or less.

8. The method of producing a silicon wafer, according to claim 6, wherein the residual oxygen concentration after heat treatment in the device fabrication process is 10×10.sup.17 atoms/cm.sup.3 or more and 18×10.sup.17 atoms/cm.sup.3 or less.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) In the accompanying drawings:

(2) FIG. 1 is a flowchart of one embodiment of a quality evaluation method for a silicon wafer;

(3) FIG. 2 is a diagram showing the relationship between the residual oxygen concentration and the BMD size in sample wafers;

(4) FIG. 3 is a diagram illustrating a high-temperature three-point bending test;

(5) FIG. 4 is a diagram showing the profile of the stress applied to sample wafers in the high-temperature three-point bending test;

(6) FIG. 5 is a diagram showing the relationship between the BMD size and the critical shear stress obtained in the high-temperature three-point bending test;

(7) FIG. 6 is a diagram showing the relationship between the residual oxygen concentration and the critical shear stress obtained in the high-temperature three-point bending test;

(8) FIG. 7 is a diagram illustrating the terms in the formula of the critical shear stress, used in this disclosure;

(9) FIG. 8 is a diagram showing the relationship between the experimental value and the calculated value of the critical shear stress;

(10) FIG. 9 is a flowchart of one embodiment of a method of producing a silicon wafer;

(11) FIG. 10 is a diagram showing the profile of the stress applied to sample wafers in a high-temperature four-point bending test; and

(12) FIG. 11 is a diagram showing that the present invention can determine with high accuracy whether or not slip dislocations are formed in the device fabrication process.

DETAILED DESCRIPTION OF THE INVENTION

(13) (Quality Evaluation Method for Silicon Wafer)

(14) Embodiments will now be described with reference to the drawings. FIG. 1 shows a flowchart of one embodiment of a quality evaluation method for a silicon wafer. First, a silicon wafer W is prepared in Step S1. For the silicon wafer W, a silicon wafer having a predetermined thickness can be used, which wafer is obtained by a known processing process including peripheral grinding, slicing, lapping, etching, and mirror polishing performed on a single crystal silicon ingot I grown by the CZ process or the floating zone melting (FZ) process. In the growth of the single crystal silicon ingot I, the oxygen concentration, the carbon concentration, the nitrogen concentration, and the like can be suitably adjusted so that the silicon wafer W cut out of the grown silicon ingot I has the desired characteristics. Further, suitable dopants may be added to obtain a wafer having a conductivity type of n-type or p-type.

(15) Next, the BMD size L and the residual oxygen concentration C.sub.O in the silicon wafer W after heat treatment performed in the device fabrication process is determined in Step S2. Here, the BMD size L and the residual oxygen concentration C.sub.O in the silicon wafer W “after heat treatment performed in the device fabrication process” is determined.

(16) The BMD size L and the residual oxygen concentration C.sub.O “after heat treatment in the device fabrication process” herein can be determined by actually performing a heat treatment performed in a device fabrication process on the silicon wafer W or a heat treatment designed to emulate the heat treatment performed in the device fabrication process and by measuring the BMD size L and the residual oxygen concentration C.sub.O after the heat treatment. Such a heat treatment can be performed using a system such as a rapid thermal annealing (RTA) system.

(17) In general, a heat treatment performed in a device fabrication process includes a plurality of steps in each of which heating is performed from an start temperature to a predetermined heat treatment temperature, and the heat treatment temperature is kept for a certain period of time, followed by cooling to an end temperature. In this disclosure, when a heat treatment performed in a device fabrication process includes a plurality of steps, the heat treatment temperature is the temperature at which the thermal stress τ is highest.

(18) The residual oxygen concentration C.sub.O of oxygen left in the silicon wafer W after such a heat treatment is measured based on the infrared absorption spectroscopy in accordance with ASTM F121-1979 using a Fourier transform infrared spectrometer (FT-IR). The BMD size L can be determined by the transmission electron microscopy (TEM).

(19) Alternatively, the BMD size L and the residual oxygen concentration C.sub.O after heat treatment can be obtained by simulation calculation without actually performing heat treatment on the silicon wafer W in the device fabrication process. Specifically, the above values can be obtained using a known numerical analysis technique (for example, see Sumio Kobayashi, Journal of Crystal Growth, 1997, Vol. 174, p. 163). Using such simulation calculation, as compared with the case of performing heat treatment on the silicon wafer W, the BMD size L and the residual oxygen concentration C.sub.O can be determined more simply and in a shorter time.

(20) Note that when the BMD size L and the residual oxygen concentration C.sub.O after heat treatment performed in the device fabrication process is determined by simulation calculation, the silicon wafer W need not be actually prepared in Step S1. Namely, Step S1 can be omitted, and only the data of the initial oxygen concentration, the thermal history during the growth, and the dopant concentration of a single crystal silicon ingot grown under certain conditions are required.

(21) Subsequently, in Step S3, the critical shear stress τ.sub.criat which slip dislocations are formed in the silicon wafer in the device fabrication process is determined based on the BMD size L and the residual oxygen concentration C.sub.O determined in Step S2. As described above, in the previous application (JP 2011-238664 A, JP 5533210 B), the inventors found that the critical shear stress τ.sub.cri at which slip dislocations are formed in a device fabrication process is closely related to the ratio of the residual oxygen concentration C.sub.O (concentration of oxygen left in a wafer having been subjected to heat treatment performed in the wafer production stage) with respect to the BMD size L, expressed as C.sub.O/L (that is, the product of the reciprocal of L, i.e., 1/L and C.sub.O).

(22) As a result of further studies to determine τ.sub.cri with more high accuracy, the inventors found that it is significantly effective to formulate the critical shear stress τ.sub.cri, at which slip dislocations are formed in the device fabrication process, as the sum of the reciprocal of the BMD size L, i.e., 1/L and the residual oxygen concentration C.sub.O in a silicon wafer after heat treatment performed in the device fabrication process. Experiments that made it possible to obtain the above finding will now be described.

(23) First, samples of many silicon wafers shown in FIG. 2 (hereinafter referred to as “sample wafer(s)”) that have different BMD sizes L and residual oxygen concentrations C.sub.O were prepared. These sample wafers were subjected to a high-temperature three-point bending test at a temperature in the range of 700° C. to 1200° C. The “high-temperature three-point bending test” is a method in which a stress can be applied to sample wafers at a given temperature, which allows the critical shear stress τ.sub.cri at which slip dislocations are formed at the temperature to be determined.

(24) Specifically, each sample wafer was cut out in a 10 mm×40 mm piece and the obtained sample piece 1 was placed on support rods 2 with their support points at intervals of 30 mm as shown in FIG. 3. The thus placed sample piece 1 was placed in a heat treatment furnace (not shown), which is set to a given temperature, and was loaded with a stress as shown in FIG. 3. After being loaded with the stress, the sample piece 1 was cooled to room temperature and taken out to be subjected to selective etching, which caused slip dislocations to be formed from BMDs. Since the slip locations became visible as a band of dislocation pits with the point of action being the center, the width of the band of the visible dislocation pits was measured. In the three-point bending test, the stress has a profile shown in FIG. 4. The limit stress at which dislocation pits are formed, that is, the critical stress of slip dislocations formed from BMDs, is a stress applied to edges of the band. Accordingly, τ.sub.cri can be determined from the formula (1) below.
τ.sub.cri=τ.sub.max×(L/L−X) (1)

(25) where τ.sub.max is the shear stress applied to the sample piece 1 in the test, L is the distance between the support points, and X is the width of the band of the dislocation pits. In this test, the applied load is read using a load cell and the read value was converted to a shear stress. Slip dislocations in silicon are formed on the (111) plane in the <110> direction. Considering this, the maximum shear stress τ.sub.max was determined by the following formula.
τ.sub.max=(3×P×L)/(2×b×d.sup.2)×0.40825 (2)

(26) where P is the maximum load read by the load cell, b is the width of the sample piece 1, and d is the thickness of the sample piece 1. Using the method, the maximum shear stress τ.sub.max was calculated, and the distance between the support points and the width of the dislocation pits were measured, thereby calculating the critical shear stress τ.sub.cri.

(27) FIG. 5 shows the relationship between the BMD size L and the critical shear stress τ.sub.cri of the sample wafer, estimated in the high-temperature three-point bending test. This diagram shows that the critical shear stress τ.sub.cri decreases as the BMD size increases. FIG. 6 shows the relationship between the residual oxygen concentration C.sub.O and the critical shear stress τ.sub.cri of the sample wafer, estimated in the high-temperature three-point bending test. This diagram shows that the critical shear stress τ.sub.cri decreases as the residual oxygen concentration C.sub.O decreases.

(28) It has been known that a BMD size L is almost the same as the size of punched-out dislocations emitted from BMDs (for example, see M. Tanaka et al., J. Mater. Res., 25(2010)2292). Accordingly, in a case where the critical shear stress τ.sub.cri changes as the BMD size L changes as shown in FIG. 2, provided that the BMD size L (the size of punched-out dislocations) is the length of dislocations serving as Frank-Read sources, the stress τ.sub.FR required for the formation of slip dislocations from punched-out dislocations can be expressed by the formula (3) below.
τ.sub.FR=A(G.Math.b/L) (3)

(29) where A is a constant, G is the modulus of rigidity, b is the Burgers vector of the slip dislocations, and L is the BMD size.

(30) Meanwhile, the effect of change in the residual oxygen concentration C.sub.O on the critical shear stress τ.sub.cri can be regarded as the behavior of the stress (locking force) by which oxygen in the BMDs locks (closely holds) punched-out dislocations serving as Frank-Read sources. The locking force can be expressed by the formula (4) below.
τ.sub.SL=B×C.sub.O×exp(0.91 eV/kT) (4)

(31) where B is a constant, k is the Boltzmann constant, and T is the temperature.

(32) The combination of those two formulae is considered to make it possible to express the critical shear stress τ.sub.cri. For example, τ.sub.cri can be expressed as the product of τ.sub.FR and τ.sub.SL. However, in that case, the critical shear stress τ.sub.cri is 0 if the residual oxygen concentration C.sub.O is 0, and this is physically unnatural because slip dislocations are formed without a load of stress. Accordingly, the inventors thought of formulating τ.sub.cri as the sum of τ.sub.FR and τ.sub.SL. Specifically, the critical shear stress τ.sub.cri is formulated as the formula (5) below.
τ.sub.cri=τ.sub.FR+τ.sub.SL=A(G.Math.b/L)+B×C.sub.O×exp(0.91 eV/kT) (5)

(33) In the above formula (5), the critical shear stress τ.sub.criat which slip dislocations are formed in the device fabrication process is expressed as the sum of the stress component τ.sub.FR required for the formation of slip dislocations from punched-out dislocations caused by BMDs and the stress component τ.sub.SL for releasing the formed punched-out dislocations from the locking by oxygen in the BMDs. This formula is physically very natural. Further, as shown in Examples below, the critical shear stress τ.sub.criat which slip dislocations are formed in the device fabrication process can be estimated with exceedingly high accuracy by the above formula (5).

(34) This formula (5) will be described in more detail with reference to FIG. 7. FIG. 7 shows a configuration image of the formula (5) in which the two broken lines show the behavior of the critical shear stress τ.sub.cri of when the BMD size L varies depending on different residual oxygen concentrations C.sub.O in the formula (5). As described above, in the formula (5), the second term τ.sub.SL represents the locking force of the punched-out dislocations formed from the BMDs, which varies depending on C.sub.O. According to the formula (5), even if the BMD size L on the horizontal axis is infinitely large, slip dislocations are not formed unless a stress exceeding the locking force is applied. The effect of the BMD size L appears as a slope A only after a stress exceeding the locking force is applied. As the BMD size L is lower, slip dislocations are not formed unless a higher stress is applied.

(35) As a result of determining the constants A and B in the above formula (5) by the regression analysis, the critical shear stress τ.sub.cri at which slip dislocations are formed in the device heat treatment process is expressed as in the formula (6) below.
τ.sub.cri=0.16×(G.Math.b/L)+6.8×10.sup.−5×C.sub.O×exp(0.91 eV/kT) (6)

(36) FIG. 8 shows the relationship between the calculated value of the critical shear stress τ.sub.cri obtained by the above formula (6) and the experimental value thereof obtained from the above-described high-temperature three-point bending test. This diagram shows that the critical shear stress τ.sub.cri within the temperature range of 700° C. to 1200° C. can be calculated with good reproducibility using the above formula (6). Here, the critical shear stress τ.sub.cri at which slip dislocations are formed in the device fabrication process is determined using the above formula (6).

(37) Subsequently, the obtained critical shear stress τ.sub.cri and the thermal stress τ applied to the silicon wafer W in the device fabrication process are compared. The thermal stress τ applied to the silicon wafer in the device fabrication process can be determined as follows. Specifically, first, the silicon wafer is loaded into a heat treatment unit such as an RTA apparatus to heat the silicon wafer to apply thermal stress thereto. Under the heating conditions in normal RTA, the heating distribution is adjusted so that the temperature does not vary in the wafer plane; however, here, thermal stress is designed to be generated with an uneven heating profile. Next, the temperature distribution T(r′) in the radial direction of the silicon wafer is measured using a thermocouple. The stresses in the radial direction and the circumferential direction are given by the following respective formulae (7) and (8).

(38) $\begin{matrix} σ_{r} (r) = α E {\frac{1}{R^{2}} \int_{0}^{R} T (r^{'}) r^{'} ⅆ r^{'} - \frac{1}{r^{2}} \int_{0}^{r} T (r^{'}) r^{'} ⅆ r^{'}} & (7) \\ σ_{θ} (r) = α E {- T (r) + \frac{1}{R^{2}} \int_{0}^{R} T (r^{'}) r^{'} ⅆ r^{'} + \frac{1}{r^{2}} \int_{0}^{r} T (r^{'}) r^{'} ⅆ r^{'}}, & (8) \end{matrix}$

(39) where r is the position in the radial direction of the silicon wafer, and R is the radius of the silicon wafer, α is the coefficient of thermal expansion, and E is the Young's modulus.

(40) In a single crystal body like a silicon wafer, the planes and the direction in which slip dislocations are formed are limited, so that an analysis considering the slip planes is required. Slip dislocations in silicon are formed on the {111} planes in the <110> direction. Excluding the equivalents, there are three slip slopes in the <110> direction each for four {111} planes. Accordingly, 12 types of shear stresses are required to be determined.

(41) The stress estimated using the above cylindrical coordinate system is converted to the Cartesian coordinate system, thereby determining the shear stresses on the respective slip planes in the respective slip directions as in the formula (9) below. Note that a slip plane is denoted by (ijk) and the slip direction is denoted by [lmn].

(42) $\begin{matrix} τ_{(ijk) [lmn]} = \frac{\begin{matrix} [l (i σ_{xx} + j σ_{xy} + k σ_{xz}) + m (i σ_{yx} + j σ_{yy} + k σ_{yz}) + \\ n (i σ_{zx} + j σ_{zy} + k σ_{zz}) \end{matrix}}{\sqrt{(i^{2} + j^{2} + k^{2}) (l^{2} + m^{2} + n^{2})}} & (9) \end{matrix}$

(43) In this disclosure, of the 12 types of shear stresses obtained as described above, the highest shear stress was adopted as the thermal stress applied to the silicon wafer in heat treatment of the device fabrication process.

(44) The thermal stress τ applied to the silicon wafer in heat treatment of the device fabrication process can be determined by simulation calculation instead of being determined using a heat treatment unit as described above. Thus, the thermal stress τ can be estimated simply in a short time. Specifically, the radiant heat applied to the wafer from a heater and the heat conduction are analyzed by the finite element method, and the temperature distribution in the wafer plane in the heat treatment process is obtained. From the obtained temperature distribution, the thermal stress τ can be determined using the formulae (7), (8), and (9).

(45) After that, in Step S4, whether or not slip dislocations are formed in the silicon wafer W in the device fabrication process is determined. In this disclosure, when the thus obtained thermal stress τ applied to the silicon wafer W in the device fabrication process is equal to or higher than the critical shear stress τ.sub.cri determined by the formula (6), slip dislocations are formed in the silicon wafer in the device fabrication process, and silicon wafers determined to have slip dislocations formed therein are determined to be defective products. In other words, when the thermal stress τ is lower than the critical shear stress τ.sub.cri, slip dislocations are determined not to be formed even after heat treatment of the device fabrication process is performed, and silicon wafers determined to have no slip dislocations formed therein are determined to be good products.

(46) In such a way, whether or not slip dislocations are formed after performing heat treatment of the device fabrication process is determined with high accuracy, so that the quality (pass/fail) of a silicon wafer can be determined.

(47) (Method of Producing Silicon Wafer)

(48) A method of producing a silicon wafer will now be described. In the disclosed method of producing a silicon wafer, a single crystal silicon ingot is grown under the growing conditions allowing a silicon wafer to be obtained, which wafer is determined to have no slip dislocations formed in a device fabrication process by the above quality evaluation method for a silicon wafer, and the grown single crystal silicon ingot is subjected to a wafer processing process.

(49) FIG. 9 shows a flowchart of one embodiment of a method of producing a silicon wafer. The steps of the method will be described below in accordance with this flowchart. First, a single crystal silicon ingot I is grown in Step S11. The growth of the single crystal silicon ingot I can be performed by the CZ process or the floating zone melting (FZ) process. In the growth of the single crystal silicon ingot I, the oxygen concentration, the carbon concentration, the nitrogen concentration, and the like can be suitably adjusted so that the silicon wafer W cut out of the grown silicon ingot I has the desired characteristics. Further, suitable dopants may be added to obtain a wafer having a conductivity type of n-type or p-type.

(50) The grown single crystal silicon ingot I is subjected to a known processing process including peripheral grinding, slicing, lapping, etching, and mirror polishing, thereby obtaining a silicon wafer W having a predetermined thickness.

(51) The subsequent steps from Step S12 to Step S14 correspond to Steps S2 to S4 in FIG. 1, respectively. Those steps relate to the above-described quality evaluation method for a silicon wafer, so the description will not be repeated.

(52) In this disclosure, in Step S14, when whether or not slip dislocations are formed in the silicon wafer W in the device fabrication process can be determined with high accuracy, and the thermal stress τ applied to the silicon wafer W in the device fabrication process is equal to or higher than the critical shear stress τ.sub.cri determined by the formula (6); slip dislocations are determined to be formed in the silicon wafer in the device fabrication process. In other words, when the thermal stress τ is lower than the critical shear stress τ.sub.cri, slip dislocations are determined not to be formed even after heat treatment of the device fabrication process is performed.

(53) Further, a single crystal silicon ingot is grown under the growing conditions allowing a silicon wafer to be obtained, which wafer is determined to have no slip dislocations formed in a device fabrication process in Step S14, and the grown single crystal silicon ingot is subjected to a wafer processing process, thereby obtaining a silicon wafer in which slip dislocations are not formed in the device fabrication process.

(54) When the thermal stress τ is equal to or higher than the critical shear stress τ.sub.cri in Step S14, the growth conditions for the single crystal silicon ingot are changed, and the steps from Step S11 in which a single crystal silicon ingot is grown to Step S14 in which whether or not slip dislocations are formed in the device fabrication process is determined are repeated until the thermal stress τ becomes lower than the critical shear stress τ.sub.cri in Step S15.

(55) The growth conditions for the single crystal silicon ingot I are changed specifically so that the critical shear stress τ.sub.cri increases, the BMD size L decreases, and/or the residual oxygen concentration C.sub.O decreases. When the single crystal silicon ingot I is grown, for example, by the CZ process, the above change can be performed, for example, by changing the oxygen concentration, the nitrogen concentration, or the carbon concentration or by changing the rotational speed of a crucible, the pulling rate, or the like.

(56) Note that when the BMD size L and the residual oxygen concentration C.sub.O after heat treatment performed in the device fabrication process are determined by simulation calculation, the process of Steps S12 to S14 are performed without growing the single crystal silicon ingot I in Step S11; a single crystal silicon ingot is grown under the growth conditions under which a silicon wafer determined to have no slip dislocations formed can ultimately be obtained; and the grown single crystal silicon ingot is subjected to a wafer processing process. Thus, a silicon wafer in which slip dislocations are not formed in the device fabrication process can be obtained.

(57) The BMD size L after the heat treatment in the device fabrication process is preferably controlled to 10 nm or more and 150 nm or less. This can prevent slip dislocations from being formed even if a high stress is applied at a high temperature. Further, the residual oxygen concentration C.sub.O after the heat treatment in the device fabrication process is preferably controlled to 10×10.sup.17 atoms/cm.sup.3 or more and 18×10.sup.17 atoms/cm.sup.3 or less. This can prevent slip dislocations from being formed even if a high stress is applied at a high temperature.

(58) Thus, a silicon wafer in which slip dislocations are not formed after heat treatment in the device fabrication process can be produced.

(59) (Silicon Wafer)

(60) Next, a silicon wafer of this disclosure will be described. The disclosed silicon wafer is a silicon wafer having a BMD size L and a residual oxygen concentration C.sub.O at which the thermal stress τ applied in a device fabrication process is lower than the critical shear stress τ.sub.cri at which slip dislocations are formed in the device fabrication process, in which wafer, no slip dislocations are formed even after a heat treatment of the device fabrication process is performed.

(61) In the disclosed silicon wafer, the BMD size L after the heat treatment of the device fabrication process is preferably 10 nm or more and 150 nm or less. This can prevent slip dislocations from being formed even if a high stress is applied at a high temperature. Further, the residual oxygen concentration C.sub.O after the heat treatment of the device fabrication process is preferably 10×10.sup.17 atoms/cm.sup.3 or more and 18×10.sup.17 atoms/cm.sup.3 or less. This can prevent slip dislocations from being formed even if a high stress is applied at a high temperature.

EXAMPLE 1

(62) Examples of this disclosure will now be described.

(63) At a set temperature, a high-temperature four-point bending test capable of applying a given stress was performed. The high-temperature four-point bending test is a test method in which the point of action in the above-described high-temperature three-point bending test is doubled, and a stress is applied with the distance between the two points of action being 15 mm. A characteristic of the high-temperature four-point bending test is that a constant stress can be applied to a sample piece as shown in the stress profile diagram in FIG. 10. Accordingly, this is an effective technique for examining whether or not slip dislocations are formed. The high-temperature four-point bending test was performed using a number of samples having different BMD densities, initial oxygen concentrations, residual oxygen concentrations C.sub.O, precipitated oxygen concentrations ΔO.sub.i, and BMD sizes as shown in Table 1 under the conditions shown in Table 2. Here, the oxygen concentration of each sample wafer was measured based on the infrared absorption spectroscopy in accordance with ASTM F121-1979 using Fourier transform infrared spectrometry.

(64) TABLE-US-00001 TABLE 1 Initial Residuall Precipitated oxygen oxygen oxygen BMD concentration concentration C.sub.o concentration BMD density InO.sub.i (×10.sup.17 (×10.sup.17 ΔO.sub.i (×10.sup.17 size L (/cm.sup.3) atoms/cm.sup.3) atoms/cm.sup.3) atoms/cm.sup.3) (nm) 5.00E+09 10 9.9 0.1 120.9 5.00E+09 10 9.2 0.8 241.8 5.00E+09 10 8.8 1.2 276.8 5.00E+09 10 8.5 1.5 298.2 5.00E+09 10 8.0 2.0 328.2 5.00E+09 10 5.8 4.2 420.3 5.00E+09 10 5.0 5.0 445.5 5.00E+09 10 3.3 6.7 491.1 1.00E+10 12 11.9 0.1 96.0 1.00E+10 12 11.2 0.8 191.9 1.00E+10 12 10.0 2.0 260.5 1.00E+10 12 9.5 2.5 280.6 1.00E+10 12 8.3 3.7 319.8 1.00E+10 12 7.8 4.2 333.6 1.00E+10 12 6.7 5.3 360.5 1.00E+10 12 5.0 7.0 395.5 1.00E+10 12 3.1 8.9 428.5 1.50E+10 15 14.9 0.1 83.8 1.50E+10 15 13.8 1.2 191.9 1.50E+10 15 13.0 2.0 227.6 1.50E+10 15 11.5 3.5 274.2 1.50E+10 15 10.2 4.8 304.7 1.50E+10 15 9.2 5.8 324.5 1.50E+10 15 8.1 6.9 343.9 1.50E+10 15 5.9 9.1 377.1 1.50E+10 15 3.8 11.2 404.1 1.50E+10 18 17.9 0.1 83.8 1.50E+10 18 16.0 2.0 227.6 1.50E+10 18 13.8 4.2 291.4 1.50E+10 18 12.1 5.9 326.4 1.50E+10 18 11.2 6.8 342.2 1.50E+10 18 9.0 9.0 375.7 1.50E+10 18 6.0 12.0 413.5

(65) TABLE-US-00002 TABLE 2 Test temperature (° C.) Load stress (MPa) 700 80 700 60 700 40 900 20 900 10 900 5 1100 5 1100 3 1100 1.5

(66) Then, it was determined whether or not slip dislocations had been formed from BMDs after each sample wafer was loaded with a stress by subjecting each sample wafer to selective etching and then confirming the presence or absence of dislocation pits using an optical microscope. Whether or not slip dislocations are formed is shown in FIG. 11, in which the BMD size L is represented by the horizontal axis and the residual oxygen concentration C.sub.O is represented by the vertical axis. In each graph in the diagram, each “o” indicates a sample wafer in which no slip dislocations were confirmed to be formed, and each “×” indicates a sample wafer in which slip dislocations were confirmed to be formed. Further, the broken line in each graph is a line obtained by calculating C.sub.O by assigning the applied stress to τ.sub.cri and the BMD size to L in the formula (6).

(67) As can be seen from the formula (6), in each sample wafer under the above broken line, the critical shear stress τ.sub.cri is lower than the thermal stress τ applied to the silicon wafer in the device fabrication process. In this disclosure, such a wafer is determined as a silicon wafer in which slip dislocations are formed. As is apparent from FIG. 11, the broken line in each graph forms a boundary between the sample wafers in which slip dislocations are formed and the sample wafers in which slip dislocations are not formed. This shows that the formula (6) makes it possible to determine with high accuracy the critical shear stress at which slip dislocations were formed after heat treatment performed in the device fabrication process, thereby determining the presence or absence of the slip dislocations with high accuracy.

EXAMPLE 2

(68) Sample wafers were subjected to heat treatment designed to emulate a standard device fabrication process, and whether or not slip dislocations were formed from BMDs was determined. Here, the heat treatment in the emulated device fabrication process was constituted by two processes A and B. Here, the process A was constituted by four heat treatment steps, in which different baking temperatures and heat treatment times were used. Meanwhile, the process B was is constituted by six heat treatment steps, in which different baking temperatures and heat treatment times were used as in the process A, and the last step was an RTA step.

(69) In the process A, the loading temperature and the unloading temperature of a sample wafer were both 600° C. and the heating rate and the cooling rate were both 8° C./min in the first to third steps. The loading temperature and the unloading temperature of the sample wafer were 800° C. and the heating rate and the cooling rate were 15° C./min in the fourth step. In the process B, the loading temperature and the unloading temperature of the sample wafer were both 600° C. and the heating rate and the cooling rate were both 8° C./min in the first to fifth steps; and the loading temperature and the unloading temperature of the sample wafer were both 650° C., the heating rate was 150° C./s, and the cooling rate was 75° C./s in the sixth step. The heat treatment conditions in the processes A and B are shown in Tables 3 and 4, respectively. The initial oxygen concentration InO.sub.i, the residual oxygen concentration C.sub.O, and the BMD size L of the sample wafers having been subjected to the processes A and B are shown in Tables 5 and 6, respectively.

(70) TABLE-US-00003 TABLE 3 Heat treatment Heat treatment Step temperature (° C.) time (min) 1 650 100 2 900 20 3 1150 600 4 1100 240

(71) TABLE-US-00004 TABLE 4 Heat treatment Heat treatment Step temperature (° C.) time (min) 1 650 100 2 900 20 3 1150 600 4 1100 240 5 1050 60 6 (RTA) 1000 1

(72) TABLE-US-00005 TABLE 5 Initial oxygen Residuall oxygen Critical shear stress τ.sub.cri concentration InO.sub.i concentration C.sub.O BMD size obtained by Formula (6) (×10.sup.17 atoms/cm.sup.3) (×10.sup.17 atoms/cm.sup.3) L (nm) (MPa) τ.sub.cri > τ Slip dislocations 14.5 11.5 911 5.2 Not satisfied Formed Sample wafer 1 13.0 9.6 782 6.0 Ssatisfied Not formed Sample wafer 2 12.1 8.3 675 6.9 Ssatisfied Not formed Sample wafer 3

(73) TABLE-US-00006 TABLE 6 Initial oxygen Residuall oxygen Critical shear stress τ.sub.cri concentration InO.sub.i concentration C.sub.O BMD size obtained by Formula (6) (×10.sup.17 atoms/cm.sup.3) (×10.sup.17 atoms/cm.sup.3) L (nm) (MPa) τ.sub.cri > τ Slip dislocations 13.5 8.7 328 15.5 Not satisfied Formed Sample wafer 4 12.8 10.8 291 17.7 Ssatisfied Not formed Sample wafer 5 10.7 9.6 263 18.9 Ssatisfied Not formed Sample wafer 6

(74) For the thermal stress τ in the device fabrication process, the in-place temperature of each sample wafer loaded into a heat treatment furnace was measured with a thermocouple using the formulae (7) to (9). As a result, a stress of 5.5 MPa was applied at a baking temperature of 1100° C. in the fourth step in the process A. On the other hand, a thermal stress of 16.5 MPa was found to be applied at a baking temperature of 1000° C. in the sixth step in the process B.

(75) With respect to the sample wafers having been subjected to the processes A and B, Table 5 shows the results of determining whether or not the thermal stress τ applied to each silicon wafer in heat treatment of the device fabrication process was lower than τ.sub.cri calculated using the formula (6) and Table 6 shows the results of whether or not slip dislocations were actually formed.

(76) As described above, in this disclosure, when the thermal stress τ applied to a sample wafer in heat treatment of a device fabrication process is lower than the critical shear stress τ.sub.cri, i.e., when τ<τ.sub.cri is satisfied; slip dislocations are determined not to be formed in the silicon wafer on which heat treatment is performed in the device fabrication process. As is apparent from Tables 5 and 6, the determination results of this disclosure are completely consistent with the results of whether or not slip dislocations were actually formed. This shows that whether or not slip dislocations originated from BMDs are formed can be determined using the formula (6) with high accuracy.

(77) Further, a single crystal silicon ingot was grown at a lower oxygen concentration than the case of growing sample wafers 1 and 3 in which slip dislocations were formed in Tables 5 and 6. The critical shear stress τ.sub.cri of a silicon wafer W having a lower initial oxygen concentration taken out of the grown ingot was determined based on the BMD size and the residual oxygen concentration after heat treatment in the device fabrication process. As a result, the critical shear stress τ.sub.cri was higher than that obtained under the unchanged growth conditions, i.e., τ<τ.sub.cri was satisfied. Thus, the silicon wafer W was obtained, in which no slip dislocations were formed even after heat treatment in the device fabrication process was performed thereon.

INDUSTRIAL APPLICABILITY

(78) The critical shear stress at which slip dislocations are formed in a device fabrication is determined with high accuracy, thereby determining with high accuracy whether or not slip dislocations are formed in a silicon wafer due to heat treatment of the device fabrication process. Accordingly, this technique is useful in the semiconductor industry.

Quality evaluation method for silicon wafer, and silicon wafer and method of producing silicon wafer using the method

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H01L21/3225

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G01N3/24

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C30B29/06

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C30B15/00

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H01L29/16

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C30B13/00

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H01L29/32

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H01L21/66

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H01L29/16

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H01L29/32

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H01L21/322

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Abstract

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