Cmos-based process for manufacturing a semiconductor gas sensor

Abstract

A CMOS-based process for manufacturing a semiconductor gas sensor includes the steps of: I) providing a semi-product, II) etching a substrate to remove a portion of the substrate and a portion of a first insulation layer so as to form a gas-sensing cavity, thereby to expose at least one sensing electrode; and III) depositing a gas-sensitive layer to cover the at least one sensing electrode.

Claims

1. A CMOS-based process for making a semi-product for manufacturing a semiconductor gas sensor, comprising the steps of: (a) preparing a substrate made from a semiconductor material and having a first surface and a second surface opposite to the first surface; (b) depositing a first insulation layer on the first surface of the substrate; (c) forming in an integrated circuit area an N-type doped region and a P-type doped region under the first surface of the substrate; (d) simultaneously forming on the first insulation layer a plurality of gate electrodes and at least one sensing electrode using a depositable conductive material, each of the gate electrodes being located above a corresponding one of the N-type and P-type doped regions, the at least one sensing electrode being located in a sensing area; (e) depositing a second insulation layer on the first insulation layer so as to cover the gate electrodes and the at least one sensing electrode; (f) forming a P-type doped source sub-region and a P-type doped drain sub-region in the N-type doped region and an N-type doped source sub-region and an N-type doped drain sub-region in the P-type doped region; (g) forming a plurality of via holes each of which extends through the first and second insulation layers and communicates with a corresponding one of the P-type doped source sub-region, the P-type doped drain sub-region, the N-type doped source sub-region, and the N-type doped drain sub-region; (h) simultaneously forming on the second insulation layer a micro-heater and a plurality of connecting ends of connecting portions using a resistive heating material, the micro-heater being in the sensing area and above the at least one sensing electrode, each of the connecting portions extending to fill a corresponding one of the via holes; and (i) depositing a third insulation layer on the second insulation layer to cover the micro-heater while leaving the connecting ends of the connecting portions exposed.

2. The method according to claim 1, wherein the depositable conductive material is polycrystalline silicon.

3. The method according to claim 1, wherein the resistive heating material is selected from the group consisting of tantalum nitride, tungsten, and a combination thereof.

4. A CMOS-based process for manufacturing a semiconductor gas sensor, comprising the steps of: (I) providing a semi-product made by the method according to claim 1; (II) etching from the second surface of the substrate to remove a portion of the substrate and a portion of the first insulation layer so as to form a gas-sensing cavity, thereby to expose the at least one sensing electrode; and (III) depositing a gas-sensitive layer to cover the at least one sensing electrode.

5. The method according to claim 4, wherein in step (II), the first insulation layer is etched via deep reactive ion etching or inductively coupled plasma etching.

6. A semiconductor gas sensor manufactured by the method according to claim 4.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Other features and advantages of the disclosure will become apparent in the following detailed description of the embodiment(s) with reference to the accompanying drawings, of which:

(2) FIG. 1 is a schematic sectional view illustrating a conventional gas sensor;

(3) FIG. 2 is a schematic sectional view illustrating another conventional gas sensor;

(4) FIG. 3 is a flow diagram of an embodiment of a CMOS-based process for manufacturing a semiconductor gas sensor according to the disclosure; and

(5) FIGS. 4-13 are schematic sectional views showing consecutive steps of the embodiment.

DETAILED DESCRIPTION

(6) As required, detailed embodiments of the present invention are disclosed herein; however, it is to be understood that the disclosed embodiments are merely exemplary of the invention that may be embodied in various and alternative forms. The figures are not necessarily to scale; some features may be exaggerated or minimized to show details of particular components. Therefore, specific structural and functional details disclosed herein are not to be interpreted as limiting, but merely as a representative basis for teaching one skilled in the art to variously employ the present invention.

(7) Before the disclosure is described in greater detail, it should be noted that where considered appropriate, reference numerals or terminal portions of reference numerals have been repeated among the figures to indicate corresponding or analogous elements, which may optionally have similar characteristics.

(8) Referring to FIG. 3, the embodiment of a CMOS-based process for manufacturing a semiconductor gas sensor according to the disclosure includes the steps of: I) providing a semi-product; II) form a gas-sensing cavity; and III) depositing a gas-sensitive layer. Specifically, the CMOS-based process is a standard CMOS-MEMS process (a complementary metal-oxide-silicon and microelectromechanical system process).

(9) Referring to FIGS. 4-10, the semi-product provided in step I) is made by a CMOS-based process which includes following steps a), b), c), d), e), f), g), h), and i).

(10) Referring to FIG. 4, in step a), a substrate 21 is prepared, which is made from a semiconductor material and which has a first surface 211 and a second surface 212 opposite to the first surface 211. In the embodiment, the substrate 21 illustrated is a silicon substrate.

(11) Referring to FIG. 5, in step b), a first insulation layer 231 is deposited on the first surface 211 of the substrate 21.

(12) Referring to FIG. 6, in step c), in an integrated circuit area (A), an N-type doped region 221 and a P-type doped region 221′ is formed under the first surface 211 of the substrate 21 by an ion diffusion procedure usually used for making a CMOS transistor in a standard IC process. One N-type doped region 221 and one P-type doped region 221′ are illustrated in the embodiment. However, the number of the N-type doped region 221 and the number of the P-type doped region 221′ are not to be limited.

(13) Referring to FIG. 7, in step d), a plurality of gate electrodes 223 and a plurality of sensing electrode 234 are simultaneously forming on the first insulation layer 231 using a depositable conductive material by a masking technology usually used in the standard CMOS-MEMS process. The depositable conductive material used in the embodiment is polycrystalline silicon. Two gate electrodes 223 are illustrated in the embodiment and each of the gate electrodes 223 is located above a corresponding one of the N-type and P-type doped regions 221, 221′. The sensing electrodes 234 are located in a sensing area (B).

(14) Referring to FIG. 8, in step e), a second insulation layer 232 is deposited on the first insulation layer 231 so as to cover the gate electrodes 223 and the sensing electrodes 234.

(15) In step f), a P-type doped source sub-region 222 and a P-type doped drain sub-region 222′ is formed in the N-type doped region 221 and an N-type doped source sub-region 225 and an N-type doped drain sub-region 225′ is formed in the P-type doped region 221′ by the ion diffusion procedure.

(16) Referring to FIG. 9, in step g), a plurality of via holes 226 are formed by a lithography and etching process. Each of the via holes 226 extends through the first and second insulation layers 231, 232 and communicates with a corresponding one of the P-type doped source sub-region 222, the P-type doped drain sub-region 222′, the N-type doped source sub-region 225, and the N-type doped drain sub-region 225′.

(17) In step h), a micro-heater 235 and a plurality of connecting ends 2241 of connecting portions 224 are simultaneously formed on the second insulation layer 232 using a resistive heating material by the masking technology. The resistive heating material suitably used in the disclosure is selected from the group consisting of tantalum nitride, tungsten, and a combination thereof. The micro-heater 235 is in the sensing area (B) and above the sensing electrodes 234, and may be configured in a meandering shape. Each of the connecting portions 224 formed from resistive heating material extends to fill a corresponding one of the via holes 226.

(18) Referring to FIG. 10, in step i), a third insulation layer 233 is deposited on the second insulation layer 232 to cover the micro-heater 235 while leaving the connecting ends 2241 of the connecting portions 224 exposed so as to make the semi-product.

(19) Referring to FIGS. 11 and 12, in step II), the semi-product is processed by etching from the second surface 212 of the substrate 21 to remove a portion of the substrate 21 and a portion of the first insulation layer 231 so as to form a gas-sensing cavity 213, thereby to expose the sensing electrodes 234. The gas-sensing cavity 213 may be formed by a wet etching method or a dry etching method, such as a DRIE (deep reactive ion etching) method or an ICP (inductively coupled plasma) etching method.

(20) Referring to FIG. 13, in step III), a gas-sensitive layer 236 is deposited to cover the sensing electrodes 234 so as to manufacture the semiconductor gas sensor.

(21) As shown in FIG. 13, the semiconductor gas sensor manufactured by the embodiment of the CMOS-based process according to the disclosure includes the substrate 21, the first insulation layer 231, the second insulation layer 232, the third insulation layer 233, a heating-and-sensing unit 23, and an electronic circuit unit 22.

(22) The substrate 21 has the first surface 211 and the second surface 212 opposite to the first surface 211 and defines the gas-sensing cavity 213 which extends from the first surface 211 to the second surface 212 and which has a first opening 214 at the first surface and a second opening 125 at the second surface 212.

(23) The first insulation layer 231 is deposited on the first surface 211 of the substrate.

(24) The second insulation layer 232 is deposited on the first insulation layer 231.

(25) The third insulation layer 233 is deposited on the second insulation layer 232.

(26) The heating-and-sensing unit 23 is located in the sensing area (B) and includes the micro-heater 235, the sensing electrodes 234, and the gas-sensitive layer 236. The micro-heater 235 is formed on the second insulation layer 232 and is covered by the third insulation layer 233. The sensing electrodes 234 are formed on the second insulation layer 232, opposite to the micro-heater 235, and within the gas-sensing cavity 213 of the substrate. The gas-sensitive layer 236 covers the sensing electrodes 234 and is within the gas-sensing cavity 213 of the substrate 21.

(27) The electronic circuit unit 22 is located in the integrated circuit area (A) and is used for driving, controlling and transducing functions. The electronic circuit unit 22 includes the N-type doped region 221, the P-type doped region 221′, the gate electrodes 223, the P-type doped source sub-region 222 and the P-type doped drain sub-region 222′ in the N-type doped region 221, and the N-type doped source sub-region 225 and the N-type doped drain sub-region 225′ in the P-type doped region 221′.

(28) As described above, the gate electrodes 223 and the sensing electrodes 234 may be simultaneously formed using the depositable conductive material, and the micro-heater 235 and the connecting portions 224 may be simultaneously formed using the resistive heating material in the CMOS-based process according to the disclosure. Therefore, the components including the sensing electrodes 234 and the micro-heater 235 in the semiconductor gas sensor may be formed in the CMOS-based process according to the disclosure without any additional post-CMOS-MEMES processing step.

(29) Furthermore, since the sensing electrodes 234 and the micro-heater 235 covering the sensing electrodes 234 are formed within the gas-sensing cavity 213 of the substrate, the size of the semiconductor gas sensor manufactured by the CMOS-based process according to the disclosure may be desirably minimized.

(30) In the description above, for the purposes of explanation, numerous specific details have been set forth in order to provide a thorough understanding of the embodiment(s). It will be apparent, however, to one skilled in the art, that one or more other embodiments may be practiced without some of these specific details. It should also be appreciated that reference throughout this specification to “one embodiment,” “an embodiment,” an embodiment with an indication of an ordinal number and so forth means that a particular feature, structure, or characteristic may be included in the practice of the disclosure. It should be further appreciated that in the description, various features are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of various inventive aspects.

(31) While the disclosure has been described in connection with what is (are) considered the exemplary embodiment(s), it is understood that this disclosure is not limited to the disclosed embodiment(s) but is intended to cover various arrangements included within the spirit and scope of the broadest interpretation so as to encompass all such modifications and equivalent arrangements.

(32) While exemplary embodiments are described above, it is not intended that these embodiments describe all possible forms of the invention. Rather, the words used in the specification are words of description rather than limitation, and it is understood that various changes may be made without departing from the spirit and scope of the invention. Additionally, the features of various implementing embodiments may be combined to form further embodiments of the invention.