Amplifying device and amplifying system comprising the same

Abstract

The present invention relates to an amplifying device and to an amplifying system comprising the same. According to the present invention, an amplifier line-up is presented comprising four amplifying units which is operable in a Doherty mode and an outphasing mode. By integration of Chireix compensating elements in the matching networks used in the amplifying units a bandwidth improvement can be obtained.

Claims

1. An amplifying device for providing an amplified signal to a load, the amplifying device comprising: a first input and a second input; a plurality of packaged amplifying units, each amplifying unit of the plurality of amplifying units comprising a respective amplifier, wherein each of a first amplifying unit and a second amplifying unit of the plurality of amplifying units has an input connected to the first input, and wherein each of a third amplifying unit and a fourth amplifying unit of the plurality of amplifying units has an input connected to the second input; a plurality of impedance matching networks, each impedance matching network of the plurality of impedance matching networks being coupled to a respective amplifier of the plurality of amplifying units; wherein the amplifying device is configured to be operable in: (i) an outphasing mode in which the amplifiers of the second and third amplifying units are operational and in which the amplifiers of the first and fourth amplifying units are off, and wherein the amplifiers of the second and third amplifying units cooperate to form an outphasing amplifier, and (ii) a Doherty mode in which the amplifiers of the first and second amplifying units cooperate to form a first Doherty amplifier and in which the amplifiers of the third and fourth amplifying units cooperate to form a second Doherty amplifier; the amplifying device further comprising a first Chireix compensating element and a second Chireix compensating element for compensating a reactive part of a load seen by the amplifier of the second amplifying unit and the amplifier of the third amplifying unit, respectively, for a predefined outphasing angle when operating in the outphasing mode; wherein signals amplified by the plurality of packaged amplifying units are combined in a combining node; wherein outputs of the impedance matching networks that are coupled to the amplifiers of the first and fourth packaged amplifying units are coupled to the combining node via respective impedance inverters; wherein each respective matching network of the plurality of matching networks is incorporated in the same packaged amplifying unit as the amplifier it is connected to, and wherein the first Chireix compensating element and the second Chireix compensating element are incorporated in the matching networks for the amplifiers of the second and third amplifying units, respectively; wherein each matching network of the plurality of matching network comprises a class E matching network, and wherein each class E matching network comprises: (i) a respective series inductor having a first terminal coupled to an output of the respective amplifier and a second terminal; and (ii) a respective shunt capacitor coupled in between the second terminal and ground, wherein the first and second Chireix compensating elements are realized by a difference in inductance of the series inductors for the second and third packaged amplifying units.

2. The amplifying device according to claim 1, wherein outputs of the impedance matching networks that are coupled to the amplifiers of the second and third packaged amplifying units are coupled to the combining node directly.

3. The amplifying device according to claim 1, wherein the series inductors of the class E matching networks for the second and third packaged amplifying units are realized using one or more bondwires, and wherein the first and second Chireix compensating elements are realized by using a different length, height, or shape for the one or more bondwires that form the series inductors.

4. The amplifying device according to claim 1, wherein the amplifiers of the first and fourth packaged amplifying units are identical and wherein an inductance value of the series inductors of the matching networks of the first and fourth amplifying units equals L1; wherein L1 is derived from q=1/(ω(L1Cd){circumflex over ( )}0.5), wherein Cd is an output capacitance of the first amplifier, q a constant between 1.2 and 1.4, and ω is an operational frequency of the amplifying device.

5. The amplifying device according to claim 4, wherein the amplifiers of the second and third packaged amplifying units are identical to the amplifiers of the first and fourth packaged amplifying units, and wherein an inductance value of the series inductors of the matching networks of the second and third packaged amplifying units equals L1+dL and L1−dL, respectively, wherein +dL and −dL correspond to an increase and decrease of the inductance value of the series inductor for realizing the first and second Chireix compensating elements, respectively.

6. The amplifying device according to claim 1, wherein the second terminals of the series inductors of respective class E matching networks incorporated in the second and third packaged amplifying units are connected to each other.

7. The amplifying device according to claim 1, wherein the shunt capacitors of the second and third packaged amplifying units are combined into a single shunt capacitor.

8. The amplifying device according to claim 1, wherein the second and third packaged amplifying units are realized using a single first package, wherein the amplifier and the matching network of the first packaged amplifying unit are realized using a single second package, and wherein the amplifier and the matching network of the fourth packaged amplifying unit are realized using a single third package.

9. The amplifying device according to claim 8, wherein each of the first, second, and third packages comprises: a package substrate; one or more first semiconductor dies on which the amplifier(s) of the amplifying unit(s) comprised by the respective package are integrated, wherein the one or more first semiconductor dies are mounted on the package substrate; one or more input leads; and one or more output leads.

10. The amplifying device according to claim 1, wherein (i) an electrical length between an output of the amplifier of the first packaged amplifying unit and the combining node and (ii) an electrical length between an output of the amplifier of the fourth packaged amplifying unit and the combining node each substantially equals m times 180 degrees, with m being an integer >0; and wherein an electrical length between an output of the amplifier of the second packaged amplifying unit and the combining node substantially equals (2n−1) times 90 degrees minus a first predefined value, and wherein an electrical length between an output of the amplifier of the third packaged amplifying unit and the combining node substantially equals (2n−1) times 90 degrees plus the first predefined value, with n being an integer >0.

11. The amplifying device according to claim 1, wherein the amplifiers of the second and third packaged amplifying units are biased in class B or class AB, and wherein the amplifiers of the first and fourth packaged amplifying units are biased in class C.

12. The amplifying device according to claim 1, further comprising a printed circuit board on which the packaged amplifying units are mounted, wherein the impedance inverters associated with the first and fourth packaged amplifying units are realized on the printed circuit board as quarter wavelength transmission lines.

13. The amplifying device according to claim 1, further comprising: a first splitter arranged in between the first input and the inputs of the first and second packaged amplifying units; and a second splitter arranged in between the second input and the inputs of the third and fourth packaged amplifying units; wherein the first splitter is configured to cause a phase difference between a signal inputted to the input of the first packaged amplifying unit and a signal inputted to the input of the second packaged amplifying unit, and wherein the second splitter is configured to cause a phase difference between a signal inputted to the input of the third packaged amplifying unit and a signal inputted to the input of the fourth packaged amplifying unit.

14. An amplifying system configured for generating a predefined modulated signal, the amplifying system comprising: the amplifying device according to claim 1; a signal unit for providing a first signal to the first input of the amplifying device and for providing a second signal to the second input of the amplifying device; and a controller for controlling the signal unit in order to set an operational mode of the amplifying device; wherein the signal unit is configured to: (i) when the amplifying device is operating in the outphasing mode, control an amplitude of the first and second signals to be equal and constant, and control a phase of the first and second signals to differ by 2ϕ, with ϕ being an outphasing angle of which a momentary value is chosen such that a momentary amplitude of the signal outputted by the amplifying device corresponds to the momentary amplitude of the predefined modulated signal; and (ii) when the amplifying device is operating in the Doherty mode, control a phase of the first and second signals to be equal, and control an amplitude of the first and second signals to be equal, the amplitude being controlled such that a momentary value of the amplitude of the signal outputted by the amplifying device corresponds to the momentary amplitude of the predefined modulated signal.

15. The amplifying system according to claim 14, wherein the amplifying device is configured to be operable in a linear mode in which the amplifiers of the second and third amplifying units are operational and in which the amplifiers of the first and fourth amplifying units are off; wherein the signal unit is configured to, when the amplifying device is operating in the linear mode, control a phase of the first and second signals to differ by 2ϕ, and control the amplitude of the first and second signals such that a momentary value of the amplitude of the signal outputted by the amplifying device corresponds to the momentary amplitude of the predefined modulated signal.

16. The amplifying system according to claim 14, wherein the controller is configured to determine an intended operational mode of the amplifying device in dependence of a desired or expected power level of the predefined modulated signal.

17. The amplifying system according to claim 16, further comprising a memory having stored therein a look-up table, the look-up table indicating which operational mode to use for the amplifying device in dependence of the desired or expected power level of the predefined modulated signal.

18. The amplifying system of claim 17, wherein the look-up table is constructed by measuring a performance parameter for different power levels of the predefined modulated signal obtained using different operational modes.

19. The amplifying system of claim 18, wherein the measured performance parameter is the power added efficiency or efficiency of the amplifying device.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Next, the present invention will be described in more detail referring to the appended drawings, wherein:

(2) FIG. 1 illustrates an embodiment of an amplifying device in accordance with the present invention;

(3) FIG. 2 illustrates an equivalent circuit of the device of FIG. 1;

(4) FIG. 3 illustrates an exemplary layout of the device of FIG. 1;

(5) FIG. 4 illustrates an amplifying system in accordance with the present invention; and

(6) FIG. 5 illustrates back-off performance of the system of FIG. 4.

DETAILED DESCRIPTION

(7) FIG. 1 illustrates an embodiment of an amplifying device 1 in accordance with the present invention. Device 1 comprises four packaged amplifying units 2A-2D, wherein each amplifying unit comprises a respective amplifier 3A-3D. Each amplifying unit further comprises a respective matching network 4A-4D.

(8) The exemplary layout of device 1, which is shown in FIG. 3, illustrates that amplifying unit 2A comprises a conductive package substrate 11A on which a first semiconductor die 14A and a second semiconductor die 15A are arranged. On first semiconductor die 14A, an RF power transistor is arranged for example a silicon-based laterally diffused metal-oxide-semiconductor (LDMOS) transistor or a Gallium Nitride based field-effect transistor (FET).

(9) Second semiconductor die 15A may be a passive die in the sense that it comprises no active elements. More in particular, a capacitor may be arranged on semiconductor die 15A, such as a metal-oxide-semiconductor (MOS) capacitor or a metal-insulator-metal (MIM) capacitor.

(10) Second amplifying unit 2A comprises a first plurality of bondwires 16A connecting input lead 13A to an input terminal of the transistor on first semiconductor die 14A. This connection can be a direct connection, as shown in FIG. 3, or an indirect connection in which a matching network is arranged in series in between input lead 13A and the input terminal of the transistor. A second plurality of bondwires 17A is used for connecting the RF power transistor to second semiconductor die 15A. More in particular, bondwires 17A connect the output terminal of the RF power transistor to a first terminal of the capacitor arranged on second semiconductor die 15A. A second terminal of this capacitor may be grounded and may be achieved through the conductive substrate 11A.

(11) The first terminal of the capacitor is connected, via a third plurality of bondwires 18A, to output lead 12A.

(12) In the equivalent circuit of device 1 shown in FIG. 2, the amplifier of amplifying unit 2A is referred to as transistor 3A. Moreover, the second plurality of bondwires 17A is represented by inductor L which has an inductance L1, and the capacitor on second semiconductor die 15A is represented by capacitor C having a capacitance C1.

(13) It should be noted that the present invention is not limited to the layout shown in FIG. 3. For example, in a different layout, bondwires 17A could extend between the output of the RF power transistor and output lead 12A, and third bondwires 18A could extend between output lead 12A and the first terminal of the capacitor on second semiconductor die 15A.

(14) FIG. 3 further shows that fourth packaged amplifying unit 3D is configured in a similar manner as first packaged amplifying unit. More in particular, fourth amplifying unit 2D comprises a first plurality of bondwires 16D connecting input lead 13D to an input terminal of the transistor on first semiconductor die 14D. This connection can be a direct connection, as shown in FIG. 3, or an indirect connection in which a matching network is arranged in series in between input lead 13D and the input terminal of the transistor. A second plurality of bondwires 17D is used for connecting the RF power transistor to second semiconductor die 15C. More in particular, bondwires 17D connect the output terminal of the RF power transistor to a first terminal of the capacitor arranged on second semiconductor die 15C. A second terminal of this capacitor may be grounded and may be achieved through the conductive substrate 11C.

(15) The first terminal of the capacitor is connected, via a third plurality of bondwires 18D, to output lead 12C.

(16) In the equivalent circuit of device 1 shown in FIG. 2, the amplifier of amplifying unit 2D is referred to as transistor 3D. Moreover, the second plurality of bondwires 17D is represented by inductor L which has an inductance L1, and the capacitor on second semiconductor die 15C is represented by capacitor C having a capacitance C1.

(17) It should be noted that the present invention is not limited to the layout shown in FIG. 3. For example, in a different layout, bondwires 17D could extend between the output of the RF power transistor and output lead 12C, and third bondwires 18D could extend between output lead 12C and the first terminal of the capacitor on second semiconductor die 15C.

(18) In the embodiment of FIGS. 2 and 3, first amplifier 3A and fourth amplifier 3D are substantial identical. For example, an identical or substantially identical transistor layout can be used for realizing amplifiers 3A, 3D.

(19) Second and third amplifying units 2B, 2C are realized in a single package. This package comprises two parallel paths that are arranged similar to amplifying units 3A, 3D. Each path comprises a separate first semiconductor die, referred to as first semiconductor die 14B or 14C, but both paths share the same second semiconductor die 15B.

(20) A first plurality of bondwires 16B connects input lead 13B to an input terminal of the transistor on second semiconductor die 14B. This connection can be a direct connection, as shown in FIG. 3, or an indirect connection in which a matching network is arranged in series in between input lead 13B and the input terminal of the transistor. A second plurality of bondwires 17B is used for connecting the RF power transistor to second semiconductor die 15B. More in particular, bondwires 17B connect the output terminal of the RF power transistor to a first terminal of the capacitor arranged on second semiconductor die 15B. A second terminal of this capacitor may be grounded and may be achieved through the conductive substrate 11B.

(21) In addition, a first plurality of bondwires 16C connects input lead 13C to an input terminal of the transistor on second semiconductor die 14C. This connection can be a direct connection, as shown in FIG. 3, or an indirect connection in which a matching network is arranged in series in between input lead 13C and the input terminal of the transistor. A second plurality of bondwires 17C is used for connecting the RF power transistor to second semiconductor die 15B. More in particular, bondwires 17C connect the output terminal of the RF power transistor to a first terminal of the capacitor arranged on second semiconductor die 15B. A second terminal of this capacitor may be grounded and may be achieved through the conductive substrate 11B.

(22) The first terminal of the capacitor is connected, via a third plurality of bondwires 18B, 18C to output lead 12B.

(23) In the equivalent circuit of device 1 shown in FIG. 2, the amplifiers of amplifying units 2B, 2C are referred to as transistor 3B, 3C, respectively. Moreover, the second plurality of bondwires 17B is represented by inductor L+ which has an inductance equaling L1+dL, the third plurality of bondwires 17C is represented by inductor L−dL which has an inductance equaling L1−dL In addition, the capacitor on second semiconductor die 15B is represented by capacitor 2C having a capacitance that equals 2C1.

(24) It should be noted that the present invention is not limited to the layout shown in FIG. 3. For example, in a different layout, bondwires 17B, 17C could extend between the output of the RF power transistor on first semiconductor die 14B, 14C, respectively, and output lead 12B, and third bondwires 18B, 18C could extend between output lead 12B and the first terminal of the capacitor on second semiconductor die 15B.

(25) In the embodiment of FIGS. 2 and 3, second amplifier 3B and third amplifier 3C are substantial identical. For example, an identical or substantially identical transistor layout can be used for realizing amplifiers 3B, 3C. Moreover, second amplifiers 3A-3D could all be substantial identical.

(26) As shown in FIGS. 2-3, device 1 comprises an input splitter 10A arranged between the first input (“input 1”) and the input terminals of amplifiers 3A, 3B, and an input splitter 10B arranged between the second input (“input 2”) and the input terminals of amplifiers 3C, 3D. Input splitter 10A introduces a phase delay of 90 degrees in the signal fed to amplifier 3B relative to the signal fed to amplifier 3A. Similarly, input splitter 10B introduces a phase delay of 90 degrees in the signal fed to amplifier 3C relative to the signal fed to amplifier 3D.

(27) In FIG. 1, input splitters 10A, 10B shown in FIGS. 2 and 3, are represented by an ideal splitter for which one output branch comprises a 90 degrees phase shifter 7A, 7B.

(28) Furthermore, the output of amplifying units 3A and 3D are connected via respective impedance inverters 5A, 5B to combining node C. This latter node is also connected to the outputs of amplifying units 3B, 3C and to load 8 via an optional impedance inverter 6.

(29) Impedance inverters 6, 5A, 5B can be realized using quarter-wave length transmission lines, for example realized on printed circuit board.

(30) The phase delay introduced by the matching networks 4A-4D substantially equals 90 degrees. It can then be verified that the phase delay between the first input and combining node C is identical irrespective of the path followed. The same holds for the phase delay between the second input and combining node C.

(31) Inductance value L1 is derived from q=1/(ω(L1Cd){circumflex over ( )}0.5), wherein Cd is the output capacitance of each amplifier 3A-3D, q a constant equal to 1.3, and wherein ω is an operational frequency of the amplifying device. A value for C1 is chosen such that the fundamental and harmonic admittances seen by amplifiers 3A-3D correspond to the so-called quasi-load insensitive class E configuration. These types of matching networks introduce a phase shift of substantially 90 degrees.

(32) Device 1 is operable in two modes. In an outphasing mode, first amplifier 3A and fourth amplifier 3D are off and second amplifier 3B and third amplifier 3C cooperate to form an outphasing amplifier. In this mode, the signals fed at the two inputs have substantially the same amplitude but differ in phase. These signals can for instance be generated using a dedicated signal unit on the basis of a signal to be amplified.

(33) In the outphasing mode, the signals to be fed to the first input and second input are constant envelope signals different in phase by an amount equal to 2ϕ, wherein ϕ is referred to as the outphasing angle. By varying the outphasing angle, the power delivered to the load can be controlled.

(34) To improve the efficiency at back off power levels, Chireix compensating elements are used. More in particular, the Chireix compensating elements are configured compensate for reactive impedances seen by the second amplifier 3B and third amplifier 3C. It should be noted that the reactive impedances generally vary with the outphasing angle. The compensating elements are therefore usually designed by optimizing performance, e.g. efficiency, over a certain back off power range. The actual design of Chireix compensating elements is well known in the art, see for example the PhD thesis “High Efficiency RF Power Amplifier Architectures” by Qureshi et al, TU Delft, 2012, ISBN 978-94-6203-071-8.

(35) According to the invention, in the outphasing mode, an outphasing amplifier is formed using amplifiers 3B, 3C and matching networks 4B, 4C. Furthermore, matching networks 4B, 4C each preferably correspond to a QLI class E matching network comprising a series inductor and a shunt capacitor in which, for each matching network, a respective Chireix compensating elements is integrated by varying the inductance of the series inductor. More in particular, the inductance value is changed by varying at least one of a shape, height, and length of the bondwire. In this manner, a low-complexity matching network can be obtained by which a high bandwidth can be obtained when compared to other topologies in which more bandwidth sensitive components are used.

(36) The inductance values of matching networks 4B, 4C can be represented by L+=L1+dL and L−=L1−dL, respectively, wherein L1 is a nominal value and dL the contribution associate with the Chireix compensating element. Similarly, the capacitance of the shunt capacitor can be represented by C1. As shown in FIG. 3, second and third amplifiers 3B, 3C are within the same package. This allows the shunt capacitors to be combined on a single semiconductor die 15B, resulting in a capacitor having a capacitance equal to 2C1. It should be noted that the present invention does not exclude embodiments wherein amplifiers 3B, 3C are integrated on the same semiconductor die.

(37) Because amplifiers 3A-3D are substantially identical, the same inductance and capacitance values, i.e. L1 and C1, can be used for matching network 4A and matching network 4D. The present invention does however not exclude embodiments wherein amplifiers 3A, 3D are different from 3B, 3C. For example, amplifiers 3A, 3D can be configured to output higher powers than amplifiers 3B, 3C. However, it is preferred to have amplifiers 3A and 3D of equal size and to have amplifiers 3B and 3C of equal size.

(38) When the device operates in the Doherty mode, all amplifiers 3A-3D are on. In this mode, amplifiers 3A and 3B cooperate to form a first Doherty amplifier (DPA). Amplifiers 3C and 3D cooperate to form a second DPA. When amplifiers 3A, 3D are larger than amplifiers 3B, 3C, the DPAs are asymmetrical. When all amplifiers 3A-3D are of equal size, symmetrical DPAs are formed.

(39) Impedance inverters 5A, 5B introduce the impedance modulation that is required in DPAs. Inverters 5A. 5B are arranged in between amplifiers 3A, 3D, which act as peak amplifiers of the DPAs in the Doherty mode, and combining node C. In that respect, the configuration can be referred to as an inverted DPA. Furthermore, in combination with the phase delay elements in the input part of device 1, it is ensured that the signals amplified by amplifiers 3A-3D all add up in phase at combining node C.

(40) To achieve the above described modes, amplifiers 3A, 3D are preferably biased in class C. This would ensure that amplifiers 3A, 3D only become operational at relatively high input powers. Amplifiers 3B, 3C are preferable biased in class AB or class B.

(41) FIG. 4 illustrates an amplifying system 100 in accordance with the present invention. System 100 comprises an amplifying device 1 as illustrated in FIGS. 1-4, and a signal unit 40 for generating the signals to be fed to the first and second inputs. Signal unit 40 is controlled by a controller 41, which is connected to a memory 42.

(42) A first signal to be fed to the first input of amplifying device 1 and a second signal to be fed to the second input of amplifying device 1 generally have a time-varying amplitude and phase offset.

(43) What type of signal is generated in signal unit 40 depends on the intended mode of operation and the desired modulation. In general, a signal Sout at the output of amplifying device 1 having amplitude and phase modulation of a carrier signal with carrier frequency ω can be denoted as Sout=A(t).Math.cos(ωt+θ(t)), with A(t) the time-dependent amplitude, and ωt+θ(t) the phase in which θ(t) represents the phase modulation.

(44) When operating in the outphasing mode, the first signal S1 and second signal S2 are generated corresponding to S1(t)=Amax/(2G.sub.2).Math.cos(ωt+θ(t)+ϕ(t)) and S2(t)=Amax/(2G.sub.3).Math.cos(ωt+≥(t)−ϕ(t)), wherein G.sub.2 and G.sub.3 are the identical signal gains of the second and third amplifying units, respectively. Amax the maximum amplitude, and ϕ(t)=cos.sup.−1(A(t)/Amax) the outphasing angle.

(45) When operating in the Doherty mode, the first signal S1 and second signal S2 are generated corresponding to S1(t)=S2(t)=Amax/(2G).Math.cos (ωt+θ(t)), wherein G is the signal gain of the first Doherty amplifier formed by the first and second amplifying units, which gain is equal to the signal gain of the second Doherty amplifier formed by the third and fourth amplifying units.

(46) When operating in the linear mode, the first signal S1 and second signal S2 are generated corresponding to S1(t)=A*(t)/(2G.sub.2).Math.cos(ωt+θ(t)+ϕth) and S2(t)=A*(t)/(2G.sub.3).Math.cos(ωt+θ(t)−ϕth), wherein ϕth equals a predefined and constant outphasing angle and wherein A*(t)cos(ϕth)=A(t).

(47) When the predefined modulated signal only comprises amplitude modulation, θ(t) can be set to a constant value, e.g. 0.

(48) Amplifying system 100 may comprise a look-up table that lists for each desired or expected power level of the generated modulated signal the best mode to use and corresponding parameters. This table is stored in a memory 42 and is generally pre-programmed. An exemplar) entry of this table could be Pout=50 dBm, outphasing mode, A1=100V, A2=100V, ϕ=10 degrees. Here, A1=100V expresses the amplitude to be used for the first signal which corresponds to Amax/(2G.sub.2). In addition, ϕ=10 degrees is the outphasing phase to be used, which, together with the amplitudes to be used for the first and second signals, results in the desired 50 dBm modulated signal at the output when the amplifying device operates in the outphasing mode.

(49) Similar entries could be made for other modes and other output powers. Here, output power refers to the momentary output power associated with the modulated carrier. In practice, different operational modes may be selected depending on the desired momentary value of the amplitude of the modulated signal.

(50) It should be further noted that signal unit 40 can be implemented digitally. In other implementations, signal unit 40 receives a non-modulated carrier signal from which it derives the signals for the first and second inputs of the amplifying device 1.

(51) FIG. 5 illustrates an overview of the efficiency of amplifying system 100 as a function of output power. Here, it is shown that for output powers below −14 dB back off the linear mode is used, for output powers between −14 dB and −6 dB back off the outphasing mode, and for output powers larger than −6 dB back off the Doherty mode.

(52) As explained above, the amplifying device and system of the present invention allow high efficiencies to be reached under large power back-off. This has been realized using an efficient integration of Chireix compensating elements and QLI class E matching networks and implementing these techniques in an amplifier line-up that allows multiple modes of operation.

(53) The present invention has been explained using detailed embodiments thereof. The skilled person will appreciate that various modifications to these embodiments are possible without deviating from the scope of the invention, which is defined by the appended drawings.