PHASE CONTROL THYRISTOR

Abstract

A thyristor, in particular a phase control thyristor, is disclosed with comprises: a) a semiconductor slab, in particular a semiconductor wave or die, in which a thyristor structure is formed, b) a cathode metallization formed on a cathode region on a cathode side surface of the semiconductor slab, c) a gate metallization formed on a gate region on the cathode side surface of the semiconductor slab, d) a plurality of N discrete emitter shorts, arranged at points P.sub.i in the cathode region, said points having point locations x.sub.i, with iε{1; . . . ; N}, e) the points P.sub.l defining a Delaunay triangulation comprising a plurality of triangles T.sub.j with jε{1; . . . ; M), wherein f) for a first subset of triangles T.sub.l with lεS.sub.1⊂{1; . . . ; M), g) with each triangle T.sub.l being characterized by a geometric quantity having values q.sub.T,l with lεS.sub.1⊂{1; . . . ; M), said geometric quantity having a mean value μ, and i) a coefficient of variation of the values q.sub.T,l with lεS.sub.1 is smaller than 0.1, preferably smaller than 0.05, and/or ii) an absolute value of a skewedness of the geometric quantities q.sub.T,l with lεS.sub.1 is smaller than 5, preferably smaller than 1, and/or iii) a Kurtosis of the geometric quantities q.sub.T,l with lεS.sub.1 is smaller than 20, preferably smaller than 10, and h) for a second subset of triangles T.sub.m with mεS.sub.2⊂S.sub.1, for which the respective geometric quantities q.sub.T,m with mεS.sub.2 deviate from the mean value by more than a predetermined amount, in particular by more than 30%, (1) a quotient of a standard deviation of the quantities q.sub.T,m with mεS.sub.2 and a mean squared value of the geometric quantity q.sub.T,l with lεS.sub.1 is less than 1 or less than 0.1, and/or a quotient of a number of triangles in the second subset and a number of triangles in the first subset is less than

Claims

1-17. (canceled)

18. A thyristor comprising: a) a semiconductor slab, in which a thyristor structure is formed, b) a cathode metallization formed on a cathode region on a cathode side surface of the semiconductor slab, c) a gate metallization formed on a gate region on the cathode side surface of the semiconductor slab, d) a plurality of N discrete emitter shorts, arranged at points P.sub.i in the cathode region, said points having point locations x.sub.i, with iε{1; . . . ; N}, e) the points P.sub.i being defined by a Delaunay triangulation comprising a plurality of triangles T.sub.j with jε{1; . . . ; M}, wherein f) for a first subset of triangles T.sub.l with lεS.sub.1⊂{1; . . . ; M}, or S.sub.1={1; . . . ; M}, g) with each triangle T.sub.l being characterized by a geometric quantity having values q.sub.T,l with lεS.sub.1⊂{1; . . . ; M}, said geometric quantity having a mean value μ, and i) a coefficient of variation of the values q.sub.T,l with lεS.sub.1 is smaller than 0.1, and/or ii) an absolute value of a skewedness of the geometric quantities q.sub.T,l with lεS.sub.1 is smaller than 5, and/or iii) a Kurtosis of the geometric quantities q.sub.T,l with lεS.sub.1 is smaller than 20, and h) for a second subset of triangles T.sub.m with mεS.sub.2⊂S.sub.1, for which the respective geometric quantities q.sub.T,m with mεS.sub.2 deviate from the mean value by more than 30%, (1) a quotient of a standard deviation of the quantities q.sub.T,m with mεS.sub.2 and a mean squared value of the geometric quantity q.sub.T,l with lεS.sub.1 is less than 1, and/or (2) a quotient of a number of triangles in the second subset and a number of triangles in the first subset is less than 1.0×10.sup.−2.

19. The thyristor according to claim 18, wherein h) the coefficient of variation of the values q.sub.T,l with lεS.sub.1 is larger than 0.0001, and/or i) the absolute value of the skewedness of the geometric quantities q.sub.T,l with lεS.sub.1 is larger than 0.0001, and/or j) the Kurtosis of the geometric quantities q.sub.T,l with lεS.sub.1 is larger than 3.0001, and/or k) for the second subset of triangles T.sub.m with mεS.sub.2⊂S.sub.1, for which the respective geometric quantities q.sub.T,m with mεS.sub.2 deviate from the mean value by more than 30%, (1) the quotient of a standard deviation of the quantities q.sub.T,m with mεS.sub.2 and a mean squared value of the geometric quantity q.sub.T,j with lεS.sub.1 is larger than 0.0001, and/or (2) the quotient of a number of triangles in the second subset and a number of triangles in the first subset is larger than 10.sup.−6.

20. The thyristor according to claim 18, wherein for all triangles in the first subset, the geometric quantity q.sub.T,l is defined as either a) a length D.sub.l of the longest edge in each triangle T.sub.l with lεS.sub.1, b) a smallest angle α.sub.min,l in each triangle T.sub.l with lεS.sub.1, c) a largest angle in each triangle T.sub.l with lεS.sub.1, d) a radius r.sub.min,l of a circle inscribed in each triangle T.sub.l with lεS.sub.1, e) a radius r.sub.max,l of a circle circumscribed around each triangle T.sub.l with lεS.sub.1, or f) a quality index q.sub.l given by q.sub.l=r.sub.min,l/r.sub.max,l for each triangle T.sub.l with lεS.sub.1.

21. A thyristor comprising: a) a semiconductor slab in which a thyristor structure has been formed, b) a cathode metallization formed on a cathode region on a cathode side surface of the semiconductor slab, c) a gate metallization formed on a gate region on the cathode side surface of the semiconductor slab, d) a plurality of N discrete emitter shorts, arranged at points P.sub.i in the cathode region, said points having point locations x.sub.i, with iε{1; . . . ; N}, e) the points P.sub.j defining a Delaunay triangulation comprising a plurality of triangles T.sub.j with jε{1; . . . ; M}, wherein f) for a first subset of points P.sub.l with lεS.sub.1⊂{1; . . . ; N}, in particular S.sub.1={1; . . . ; N}, g) with each point P.sub.l being characterized by a geometric quantity having values q.sub.P,l with lεS.sub.1⊂{1; . . . ; N}, said geometric quantity having a mean value μ, and i) a coefficient of variation of the values q.sub.P,l with lεS.sub.1 is smaller than 0.1, and/or ii) an absolute value of a skewedness of the geometric quantities q.sub.P,l with lεS.sub.1 is smaller than 5, and/or iii) a Kurtosis of the geometric quantities q.sub.P,l with lεS.sub.1 is smaller than 20, and h) for a second subset of points P.sub.m with mεS.sub.2⊂S.sub.1 for which the respective geometric quantities q.sub.P,m with mεS.sub.2 deviate from the mean value by more than 30%, (1) a quotient of a standard deviation of the quantities q.sub.P,m with mεS.sub.2 and a mean squared values of the geometric quantity q.sub.P,l with lεS.sub.1⊂{1; . . . ; N} is less than 1, and/or (2) a quotient of a number of points in the second subset and a number of triangles in the first subset is less than 1.0×10.sup.−2.

22. The thyristor according to claim 21, wherein i) the coefficient of variation of the values q.sub.P,l with lεS.sub.1 is larger than 0.0001, and/or ii) the absolute value of the skewedness of the geometric quantities q.sub.P,l with lεS.sub.1 is larger than 0.0001, and/or iii) the Kurtosis of the geometric quantities q.sub.P,l with lεS.sub.1 is larger than 3.0001, and h) for the second subset of points P.sub.m with mεS.sub.2⊂S.sub.1, for which the respective geometric quantities q.sub.P,m with mεS.sub.2 deviate from the mean value by more than 30%, (1) the quotient of a standard deviation of the quantities q.sub.P,m with mεS.sub.2 and a mean squared value of the geometric quantity q.sub.P,l with lεS.sub.1 is larger than 0.0001, and/or (2) the quotient of a number of points in the second subset and a number of triangles in the first subset is larger than 10.sup.−6.

23. The thyristor according to claim 21, wherein for all points in the first subset, the geometric quantities q.sub.T,l are defined as either a) a number N.sub.edges,l of edges connected to each point P.sub.l with lεS.sub.1, b) a number N.sub.triangles,l of triangles sharing each point P.sub.l with lεS.sub.1, c) a length l.sub.min,l of a shortest edge connected to each point P.sub.l with lεS.sub.1, d) a length l.sub.max,l of a longest edge connected to each point P.sub.l with lεS.sub.1, or e) a Volume V.sub.l of Voronoi cell associated with each point P.sub.l with lεS.sub.1.

24. The thyristor according to claim 18, wherein a turn function difference TFD1 between an outer boundary of the cathode region and an outer envelope of the emitter shorts distribution, which is a smallest contour enclosing all emitter short locations in the cathode region, wherein TDF1 being defined as $TFD .Math. .Math. 1 = \frac{\int .Math. Θ_{cathode, outer} - Θ_{env, outer} .Math. .Math. ds}{2 .Math. π .Math. \int_{cathode, outer} .Math. ds}$ with Θ.sub.cathode,outer being a turn function of the outer region boundary and Θ.sub.env,outer being a turn function of the outer envelope of the emitter shorts distribution and/or a turn function difference between an inner envelope of the emitter shorts distribution and an outer boundary of the gate region is less than 0.15 and larger than 10.sup.−4.

25. The thyristor according to claim 18, wherein the first subset comprises all points or all triangles located within a circle C with a diameter d.sub.C circumscribing the gate electrode, which diameter d.sub.C is smaller than a diameter d.sub.wafer of the slab or 0.75 d.sub.wafer, or within a minimal circle C.sub.min, which is a circle with a minimum diameter d.sub.C,min circumscribing the gate electrode.

26. The thyristor according to claim 25, wherein the first subset comprises all points or all triangles located within a circle C′, said circle C′ being concentric to C or C.sub.min and having a diameter d.sub.C′ with d.sub.C′>0.75d.sub.C.

27. The thyristor according to claim 18, wherein the number of points or the number of triangles in the first subset is larger than 250.

28. The thyristor according to claim 18, wherein the number of points or of triangles in the first subset is larger than 0.8 N.

29. The thyristor according to claim 18, wherein a coefficients of variation of the distance d.sub.closest between any given point on the boundary and the location of the emitter short closest to said point over the inner boundary and/or the outer boundary of the cathode region of less than 0.2.

30. The thyristor according to claim 18, wherein the Delaunay triangulation is a restricted Delaunay triangulation on the cathode region.

31. A method for manufacturing a thyristor, comprising: a) forming a thyristor structure in a semiconductor slab, b) defining a cathode region on cathode side surface of the semiconductor slab, c) defining a shorts region as a subregion of the cathode region, d) determining, by means of a meshing algorithm, a surface mesh within the shorts region, said surface mesh comprising a plurality of points P.sub.i with iε{1; . . . ; N}, e) forming a discrete emitter short at a location of each point P.sub.i with iε{1; . . . ; N}, and f) forming a cathode metallization on the cathode region wherein g) the meshing algorithm is h) a Delaunay technique algorithm or a hexagonal Delaunay triangulation algorithm, or is based on i) an advancing front method, j) a circle packing or bubble packing method, k) a paving algorithm, or on l) a quadtree method.

32. A method for manufacturing a thyristor, comprising: a) forming a thyristor structure in a semiconductor slab, b) defining a cathode region on cathode side surface of the semiconductor slab, c) defining a shorts region as a subregion of the cathode region, d) determining, by means of a meshing algorithm, a surface mesh within the shorts region, said surface mesh comprising a plurality of cells C.sub.j, with each cell delimited by a plurality of edges e.sub.jk with jε{1; . . . ; M} and kε{1; 2; 3; . . . }, e) forming a discrete emitter short at one location within each cell or at one location on each edge, and f) forming a cathode metallization on the cathode region, wherein g) the meshing algorithm is h) a Delaunay technique algorithm, or is based on i) an advancing front method, j) a circle packing or bubble packing method, k) a paving algorithm, or on l) a quadtree method.

33. The thyristor according to claim 19, wherein for all triangles in the first subset, the geometric quantity q.sub.T,l is defined as either a) a length D.sub.l of the longest edge in each triangle T.sub.l with lεS.sub.1, b) a smallest angle α.sub.min,l in each triangle T.sub.l with lεS.sub.1, c) a largest angle in each triangle T.sub.l with lεS.sub.1, d) a radius r.sub.min,l of a circle inscribed in each triangle T.sub.l with lεS.sub.1, e) a radius r.sub.max,l of a circle circumscribed around each triangle T.sub.l with lεS.sub.1, or f) a quality index q.sub.l given by q.sub.l=r.sub.min,l/r.sub.max,l for each triangle T.sub.l with lεS.sub.1.

34. The thyristor according to claim 22, wherein for all points in the first subset, the geometric quantities q.sub.T,l are defined as either a) a number N.sub.edges,l of edges connected to each point P.sub.l with lεS.sub.1, b) a number N.sub.triangles,l of triangles sharing each point P.sub.l with lεS.sub.1, c) a length l.sub.min,l of a shortest edge connected to each point P.sub.l with lεS.sub.1, d) a length l.sub.max,l of a longest edge connected to each point P.sub.l with lεS.sub.1, or e) a Volume V.sub.l of Voronoi cell associated with each point P.sub.l with lεS.sub.1.

35. The thyristor according to claim 18, wherein: i) the coefficient of variation of the values q.sub.T,l with lεS.sub.1 is smaller than 0.05, and/or ii) the absolute value of a skewedness of the geometric quantities q.sub.T,l with lεS.sub.1 is smaller than 1, and/or iii) the Kurtosis of the geometric quantities q.sub.T,j with lεS.sub.1 is smaller than 10, and h) for the second subset of triangles T.sub.m with mεS.sub.2⊂S.sub.1, for which the respective geometric quantities q.sub.T,m with mεS.sub.2 deviate from the mean value by more than 30%, (1) the quotient of a standard deviation of the quantities q.sub.T,m with mεS.sub.2 and a mean squared value of the geometric quantity q.sub.T,l with lεS.sub.1 is less than 0.1, and/or (2) the quotient of a number of triangles in the second subset and a number of triangles in the first subset is less than 0.5×10.sup.−3.

36. The thyristor according to claim 18, wherein: h) the coefficient of variation of the values q.sub.T,l with lεS.sub.1 is larger than 0.01, and/or i) the absolute value of the skewedness of the geometric quantities q.sub.T,l with lεS.sub.1 is larger than 0.01, and/or k) for the second subset of triangles T.sub.m with mεS.sub.2⊂S.sub.1, for which the respective geometric quantities q.sub.T,m with mεS.sub.2 deviate from the mean value by more than 30%, (1) the quotient of a standard deviation of the quantities q.sub.T,m with mεS.sub.2 and a mean squared value of the geometric quantity q.sub.T,l with lεS.sub.1 is larger than 0.01, and/or (2) the quotient of a number of triangles in the second subset and a number of triangles in the first subset is larger than 0.0001.

37. The thyristor according to claim 25, wherein the first subset comprises all points or all triangles located within a circle C′, said circle C′ being concentric to C or C.sub.min and having a diameter d.sub.C′ with d.sub.C′>0.9 d.sub.C.

38. The thyristor according to claim 18, wherein the number of points or the number of triangles in the first subset is larger than 1000.

Description

BRIEF DESCRIPTION OF DRAWINGS

[0106] The subject matter of the invention will be explained in more detail in the following text with reference to the attached drawings, in which:

[0107] FIG. 1 shows a cross-sectional view of doping regions and contact arrangements of a state-of-the-art phase controlled thyristor.

[0108] FIG. 2 shows a cross-sectional view of a state-of-the-art phase controlled thyristor with an amplifying gate structure.

[0109] FIG. 3 shows a cross-sectional view of a portion of a state-of-the-art phase controlled thyristor with emitter shorts.

[0110] FIG. 4 shows a top view onto an emitter shorts pattern of the phase controlled thyristor of FIG. 3.

[0111] FIG. 5 shows a partial view of a process mask as described in the state of the art

[0112] FIG. 6 shows a schematic representation of an exemplary variant of the method for manufacturing a thyristor in accordance with the present invention

[0113] FIG. 7A illustrates vector operations for extending a shape of a gate region during mesh generation;

[0114] FIG. 7B illustrates a subsequent step in vector operations for extending shape of the gate region during mesh generation;

[0115] FIG. 8A illustrates a variant for obtaining a surface mesh for use with the method in accordance with the present invention;

[0116] FIG. 8B illustrates another depiction of the FIG. 8A illustration;

[0117] FIG. 8C illustrates further depictions of the FIG. 8A illustration;

[0118] FIG. 8D-8F illustrate subsequent rows for the variant illustrated in FIG. 8C;

[0119] FIG. 9 illustrates a turn function for an exemplary polygon;

[0120] FIG. 10 shows a top view of a phase controlled thyristor 100 with emitter shorts 128 at locations obtained in accordance with prior art;

[0121] FIG. 11A illustrates turn functions for the thyristor from FIG. 10;

[0122] FIG. 11B illustrates turn functions for a thyristor in accordance with the present invention;

[0123] FIG. 12 shows a partial top view of the cathode side surface of a thyristor in accordance with the present invention;

[0124] FIG. 13 shows a portion of a surface mesh as obtained in a variant of the method in accordance with the present invention.

[0125] The reference signs used in the figures and their meaning are summarized in the list of reference signs. Generally, alike or alike-functioning parts are given the same reference signs. The described embodiments are meant as examples and shall not confine the invention.

MODES FOR CARRYING OUT THE INVENTION

[0126] FIG. 6 shows a schematic representation of an exemplary variant of the method for manufacturing a thyristor in accordance with the invention. In a first method step 91, a cathode region is defined on cathode side surface on a first main side of a semiconductor slab, in which a thyristor structure, as e.g. shown in FIG. 1 and FIG. 2 has been formed. In a subsequent method step 92, a shorts region is selected, which may be a subregion of the cathode region, or may be identical to the cathode region. In a further subsequent method step 93, a surface mesh is determined within the shorts region by a meshing algorithm, wherein said surface mesh comprises a plurality of points P.sub.i with iε{1; . . . ; N} and a plurality of cells C.sub.j, preferably triangles T.sub.j, with jε{1; . . . ; M}, i.e. with a total of N points and M cells, wherein, in general M≈N and N>500, preferably N>1000. An advancing front method as e.g. described in “NETGEN—An advancing front 2D/3D-mesh generator based on abstract rules”, Computing and Visual Science 1, 41-53 (1997), Springer-Verlag 1997, which is hereby included by reference in its entirety; a Delaunay technique or advanced Delaunay technique; or a Quadtree/Octree technique is used as meshing algorithm. In a further subsequent method step 94, a discrete emitter short is formed on the first main side of the semiconductor slab at a location of each point P.sub.i with iε{1; . . . ; N}. Finally, a cathode metallization is provided over the cathode region in a further subsequent method step 94.

[0127] Preferably, when using an advancing front method for determining the surface mesh, meshing is started from a boundary or border of the shorts region, wherein the boundary is described by curved lines, preferably by Bezier curves or NURBS, and preferably discretized according to a desired distance d.sub.max between the shorts. Then a first layer of mesh cells, preferably triangles, most preferably equilateral triangles, is created. Subsequently, additional layers of mesh cells are created, thus forming an advancing front of mesh elements. When the advancing fronts collide and the whole shorts region has been filled with mesh elements, meshing is stopped. Preferably, the triangles are re-arranged by means of a so called smoothing technique, in particular Laplacian smoothing, Poisson smoothing, mesh jiggling, and/or trapezium smoothing to improve geometrical properties of the mesh, in particular to increase homogeneity and uniformity. Preferably, the smoothing techniques employ edge swapping, edge splitting, edge collapsing and or node smoothing.

[0128] Preferably, when using a Delaunay technique algorithm for determining the surface mesh, an iterative technique is used, as e.g. based on a so called “divide and conquer” technique, as e.g. described in the article “Constrained delaunay triangulations” by Chew, L. Paul, in Algorithmica 4, no. 1-4 (1989), pp. 97-108. Alternatively, a Voronoi triangulation may be constructed in a first step, and a Delaunay triangulation subsequently determined from a dual triangulation, as e.g. described in the article “Primitives for the manipulation of general subdivisions and the computation of Voronoi” by Leonidas Guibas and Jorge Stolfi in ACM Trans. Graph. 4, 2 (April 1985), pp. 74-123.

[0129] QUADTREE/OCTREE techniques which are based on dividing a region into rectangular cells of different sizes, and subsequently dividing the rectangular cells into triangles, may also be used advantageously in obtaining the surface mesh.

[0130] For both Delaunay/Voronoi and QUADTREE/OCTREE techniques, smoothing techniques as described above may be employed to further refine the triangles obtained.

[0131] Alternatively, the surface mesh may advantageously also be determined based on one of the following methods: [0132] the so called bubble packing method as described by Kim, Jeong-Hun, et al. “Adaptive mesh generation by bubble packing method.” Structural Engineering and Mechanics 15.1 (2003): 135-150, see, in particular, FIG. 6. [0133] quadtree methods in which quadrangles are generated and subsequently cut into triangles, as described e.g. in Samet, Hanan. “The quadtree and related hierarchical data structures.” ACM Computing Surveys (CSUR) 16.2 (1984): 187-260. [0134] so called paving algorithms as described, e.g., in Randy R. Lober, Timothy J. Tautges, Courtenay T. Vaughan, Sandia Report: SAND97-0545*UC-705 Unlimited Release Printed March 1997, “Parallel Paving: An Algorithm for Generating Distributed, Adaptive, All-quadrilateral Meshes on Parallel Computers”; see, in particular, FIG. 7. [0135] circle packing, as described, e.g., in: Bern, Marshall, and David Eppstein. “Quadrilateral meshing by circle packing”, International Journal of Computational Geometry & Applications 10.04 (2000): 347-360. [0136] Hexagonal Delaunay Triangulation, as described, e.g., in SuBner, Gerd and Greiner, GUnther, “Hexagonal Delaunay Triangulation”, Proceedings of the 18th Intemational Meshing Roundtable, 2009, pp. 519-538. [0137] All references cited above are hereby included by reference in their entirety.

[0138] Preferably, a meshing algorithm producing an unstructured mesh is employed. An unstructured mesh is characterized by irregular connectivity, whereas a structured mesh is characterized by regular connectivity that can be expressed as a two or three dimensional array (like a checkerboard or hive cells). A meshing algorithm producing hybrid mesh may employed with advantage. A hybrid mesh is a mesh that contains structured portions and unstructured portions, as, e.g., detailed in Finite Element Mesh Generation, by D. S. H. Lo, Taylor & Francis, ISBN 9780415690485.

[0139] In a preferred variant of the of the method for manufacturing a thyristor in accordance with the invention, a process mask is formed prior to step 94, and used in step 94 to selectively dope a region of the semiconductor slab adjoining the cathode side surface so that discrete emitter short are formed at locations corresponding to points P.sub.i with iε{1; . . . ; N}.

[0140] In another exemplary variant of the method for manufacturing a thyristor in accordance with the invention, the mesh is obtained by means of a Delaunay technique algorithm based on an advancing front method as will be described in what follows:

[0141] In a first step, a shape of the gate region is represented by a closed set of vectors, each vector defined by its angle and length, as shown in FIG. 7A. A closed polygon representing the geometry is thus obtained. In a subsequent step, said geometry is extended by calculating a weighted normal at each vertex, i.e. at each corner of the polygon. Checks are made to ensure that a new shape thus obtained strictly contains the previous shape and that no sharp angles are artificially introduced. This is shown in FIG. 7B. Preferably, this step is repeated multiple times.

[0142] The result of these steps is shown in FIGS. 8A and 8B for the main gate geometry from FIG. 5. Given a generic geometry of the gate region, the previous steps allow to roughly predict a direction of plasma spread. A first distance d=d.sub.adv,1 by which the shape of the gate region is extended in a direction of the weighted normal is preferably set according, in particular equal, to a lithographic resolution limit, in order to maximize dV/dt capability. Subsequent distances d.sub.adv, for extending the shape are set according to the desired short spacing d.sub.max. On a first extended shape 901 obtained according to the above steps, short locations are preferably provided with distances at least approximately equaling the desired short spacing d.sub.max as shown in FIG. 8C), thus representing a first row of short locations adjacent to the gate region.

[0143] Subsequent rows are then obtained by building a Delaunay triangulation using the subsequently obtained extended shapes 902 from the above steps, as indicated in FIG. 8D)-F). A uniformity of the resulting short locations pattern can be controlled by parameters of the Delaunay triangulation. Preferably, all angles should be close to 60 degrees, i.e. within a specified tolerance. Likewise, all maximum edge lengths should be close to the desired short spacing d.sub.max, i.e. again within a specified, second tolerance.

[0144] The variant as described above leads to very uniform spacing of the short locations throughout the thyristor, wherein the shorts are also aligned in the direction of the plasma spread, to reduce the impact of the shorts on plasma propagation speed. As an optional step the short locations can preferably be further optimized using typical algorithms for Delaunay triangulation. For example, even higher short location uniformity can be obtained through techniques such as Laplacian smoothing, entropyoptimal point-location, Delaunay edge flipping.

[0145] Preferably, if any symmetries are present in the geometry of the gate region, these symmetries are also taken into account when obtaining the mesh by applying the methods according to any of the variants as described above only to a portion, preferably a portion without further symmetries, of the structure, thus obtaining a partial mesh, and by subsequently obtaining a complete mesh by symmetric mapping of the partial mesh.

[0146] Mesh quality indicative of uniformity and homogeneity of the short locations may be measured based on a variety of quantities.

[0147] The surface mesh obtained in accordance with any of the variants as described above comprises several pluralities of geometric objects, in particular a plurality of points P.sub.i with iε{1; . . . ; N} defining a Delaunay triangulation, as described, e.g., in https://en.wikipedia.org/w/index.php?title=Delaunay_triangulation&oldid=662807396 and https://en.wikipedia.org/w/index.php?title=Delaunay_triangulation&oldid=614036873 which are hereby included by reference in their entirety.

[0148] In particular, the surface mesh obtained in accordance with any of the variants as described above comprises several pluralities of geometric objects, in particular a plurality of points P.sub.i with iε{1; . . . ; N} defining a restricted Delaunay triangulation on the cathode region. Restricted Delaunay triangulations are discussed in the article by Jean-Philippe Pons, Jean-Daniel Boissonnat, “Delaunay Deformable Models: Topology-Adaptive Meshes Based on the Restricted Delaunay Triangulation”, CVPR, 2007, 2013 IEEE Conference on Computer Vision and Pattern Recognition, pp. 1-8, doi:10.1109/CVPR.2007.383019, Print ISBN: 1-4244-1179-3.

[0149] Said Delaunay triangulation in turn comprises a plurality of triangles T.sub.j with jε{1; . . . ; M}, each comprising three edges e.sub.jk with kε{1; 2; 3}. For each of the geometric objects, one or more geometric quantities may be defined. In particular, each triangle T.sub.j has an area A.sub.j. For jε{1; . . . ; M}, a radius r.sub.c,j of a circle inscribed to triangle T.sub.j may be determined according to r.sub.ic,j=A.sub.j/(2Π.sub.k=1.sup.3l.sub.jk), whereas a radius r.sub.ocj of a circumscribed circle is given by r.sub.ccj=Π.sub.k=1.sup.3l.sub.jk/(4A.sub.j). Further, for each triangle T.sub.j with jε{1; . . . ; M} a diameter D.sub.j may be defined by the length of the longest edge e.sub.jk with kε{1; 2; 3} in said triangle T.sub.j according to D.sub.j=max|.sub.k{I.sub.jk}. and having lengths l.sub.jk with kε{1; 2; 3}. Each edge e.sub.jk has a length l.sub.jk; and an angle α.sub.jk with kε{1; 2; 3} opposite each edge α.sub.jk may be calculated using Heron's formula.

[0150] Several metrics may be defined which may be used in measuring mesh quality. Preferably, these metrics are calculated based on one geometric quantity of either each triangle, each point or each edge. In particular, statistical measures such as standard deviation, skewedness, kurtosis may be used in determining the metric.

[0151] For a set of N values x.sub.l with iε{1; . . . ; N}, a mean value μ, also referred to as mean, is defined according to

[00001] $μ = \frac{1}{N} .Math. {.Math.}_{i = 1}^{N} .Math. x_{i} .$

[0152] A standard deviation σ is defined according to

[00002] $σ = \sqrt{\frac{1}{N} .Math. {.Math.}_{i = 1}^{N} .Math. {(x_{i} - μ)}^{2}}, where .Math. .Math. μ = \frac{1}{N} .Math. {.Math.}_{i = 1}^{N} .Math. x_{i} .$

[0153] As a rough guidance, for an acceptable mesh, a coefficient of variation σ/μ should be less than 0.1, preferably less than 0.05, for at least one, preferably all geometric quantities as described above.

[0154] A skewedness γ.sub.1 is defined according to:

[00003] $γ_{1} = {.Math.}_{i = 1}^{N} .Math. {(\frac{x_{i} - μ}{σ})}^{3}$

[0155] As a rough guidance, for an acceptable mesh, skewedness should be less than 5, preferably less than 1.5, and most preferably as close to 0 as possible, for at least one, preferably all geometric quantities as described above.

[0156] A kurtosis β.sub.2 is defined according to:

[00004] $β_{2} = {.Math.}_{i = 1}^{N} .Math. {(x_{i} - μ)}^{4} / {({.Math.}_{i = 1}^{N} .Math. {(x_{i} - μ)}^{2})}^{2}$

[0157] As a rough guidance, for an acceptable mesh, kurtosis should be less 20.0 and ideally less than 10.0, for at least one, preferably all geometric quantities as described above.

[0158] So called outliers, in particular a number of extreme outliers, may also be used as a basis for statistical measures. Outliers may be defined in many different ways. One preferred way is to define an outlier as a value that deviates from the mean value p by more than a predetermined amount, e.g. by more than 30% of the mean itself.

[0159] Exemplary metrics based on a set of outliers are: [0160] A standard deviation of the outliers' values/squared mean of all the values contributing to the mean value. Should be as close to 0 as possible. Less than 1 is a good value [0161] An amount of outliers, defined as the ratio of a number of outliers and a total number of values. As a rough guidance, for an acceptable mesh, the amount of outliers should be less than 10.sup.−2, preferably less than 5.0.Math.10.sup.−3 for at least one, preferably all geometric quantities as described above.

[0162] The following exemplary metrics have proven particularly efficient in characterizing mesh quality: [0163] 1. Standard deviation, skewedness and kurtosis, and amount of extreme outliers of the diameters D.sub.j of all triangles Tj with jε{1; . . . ; M}. [0164] 2. Standard deviation, skewedness, kurtosis and amount of extreme outliers of the lengths l.sub.jk of all edges in the mesh, i.e. with jkε{1; . . . ; M}×{1; 2; 3}. [0165] 3. Mean, standard deviation, skewedness, kurtosis and amount of extreme outliers of the angles α.sub.jk of all triangles in the mesh, i.e. with jkε{1; . . . ; M}×{1; 2; 3}. Preferably, the mean value equals at least approximately 60°. [0166] 4. Standard deviation, skewedness, kurtosis and amount of extreme outliers of Γ:=2*r.sub.icj/r.sub.ccj. Preferably, the value equals at least approximately 1.0 for all triangles Tj with jε{1; . . . ; M}. As a rough guidance, for an acceptable mesh, Γ should be less than 0.8 for at most 10% of all triangles Tj, preferably less than 0.85 for at most 5% of all triangles Tj [0167] 5. Standard deviation, skewedness, kurtosis and amount of extreme outliers of E:=A.sub.j.sup.2/3(Σ.sub.k=1.sup.3l.sub.jk).sup.2. As a rough guidance, for an acceptable mesh, Γ should be less than 0.8 for at most 10% of all triangles Tj; preferably less than 0.85 for at most 5% of all triangles Tj [0168] 6. Standard deviation, skewedness, kurtosis and amount of extreme outliers of ρ:=min|.sub.k{l.sub.jk}/max|.sub.k{l.sub.jk}. As a rough guidance, for an acceptable mesh, Γ should be less than 0.8 for at most 10% of all triangles Tj; preferably less than 0.85 for at most 5% of all triangles Tj. [0169] 7. Standard deviation, skewedness, kurtosis and amount of extreme outliers of a ratio of a maximum length of all edges connected to a point P.sub.i with iε{1; . . . ; N} and a mean value of the length of all edges connected to said point. An optimum value is 1.0. [0170] 8. Standard deviation, skewedness, kurtosis and amount of extreme outliers of a number N.sub.edges,i of edges connected to a point P.sub.i with iε{1; . . . ; N}. An optimum value is N.sub.edges,j=6. [0171] 9. Standard deviation, skewedness, kurtosis and amount of extreme outliers of a mean value of all angles associated with a point P.sub.i with iε{1; . . . ; N}. Preferably, the mean value equals at least approximately 60° [0172] 10. Standard deviation, skewedness, kurtosis and amount of extreme outliers of volume of a Voronoi cell associated with a point P.sub.j with jε{1; . . . ; N}. [0173] 11. Standard deviation, skewedness, kurtosis and amount of extreme outliers of a number N.sub.triangles,i of triangles that share a point P.sub.i with iε{1; . . . ; N}. An optimum value is N.sub.triangles,i=6.

[0174] A so called turn function difference may be used to assess a uniformity of the distribution of emitter shorts near the boundary of the cathode region. To determine the turn function difference, an outer envelope of the emitter shorts distribution is defined as the smallest contour, i.e. the shortest polygonal, simple closed curve, which encloses all emitter short locations in the cathode region. Similarly, an outer envelope is defined as the largest contour, i.e. the longest polygonal, simple closed curve that encloses the gate region, but encloses none of the emitter short locations in the cathode region.

[0175] As described, e.g., in the articles by Arkin, Esther M., et al., “An efficiently computable metric for comparing polygonal shapes”, IEEE Transactions on Pattern Analysis & Machine Intelligence 3 (1991): 209-216, and by Latecki, Longin Jan, and Rolf Lakämper, “Shape similarity measure based on correspondence of visual parts”, Pattern Analysis and Machine Intelligence, IEEE Transactions on 22.10 (2000): 1185-1190, which are hereby included by reference in their entirety, so called turn function Θ(s) may be defined for a polygon, wherein Θ(s) is the angle between two points of the polygon, while s is the total distance along a perimeter of the polygon. Based on this definition, is it possible to evaluate a turn functions, in particular turn functions Θ.sub.cathode,inner(s) and Θ.sub.cathode,outer(s) for the cathode region boundary, a turn function Θ.sub.gate(s) for the outer gate region boundary, and turn functions Θ.sub.env,inner(s) and Θ.sub.env,outer(s) for the inner and outer envelope, respectively, of the emitter shorts distribution. A turn function Θ(s) for an exemplary polygon 400 is illustrated in FIG. 9.

[0176] Various turn function differences may then be used as an indication of how similar or different—shapes of various geometric objects as introduced above are. In particular, a turn function difference TFD1 between the outer boundary of the cathode region and the outer envelope of the emitter shorts distribution is given by

[00005] $TFD .Math. .Math. 1 = \frac{\int .Math. Θ_{cathode, outer} - Θ_{enc, outer} .Math. .Math. ds}{2 .Math. π .Math. \int_{cathode, outer} .Math. ds}$

and gives an indication of how similar the outer boundary of the cathode region and the outer envelope of the emitter shorts distribution are, whereas a turn function difference TFD2 between an inner envelope of the emitter shorts distribution and the outer boundary of the gate region is given by

[00006] $TFD .Math. .Math. 2 = \frac{\int .Math. Θ_{gate} - Θ_{enc, inner} .Math. .Math. ds}{2 .Math. π .Math. \int_{gate} .Math. ds}$

and gives an indication of how similar the inner envelope of the emitter shorts distribution and the outer boundary of the gate region are. Turn function differences typically have values between 0 and 1.

[0177] For thyristors manufactured in accordance with the inventive methods as described herein, values smaller than 0.15, in particular smaller than 0.1, albeit preferably larger than 10.sup.−4 may be achieved for the turn function differences, in particular for TFD1 and/or TFD2, as defined above.

[0178] FIG. 10 shows a top view of the cathode side surface of a phase controlled thyristor 100 with emitter shorts 128 at locations obtained in accordance with prior art. Gate region boundary 401, inner boundary of the cathode region 411, outer boundary of the cathode region 412, inner envelope 421 and outer envelope 422 of the emitter shorts distribution are illustrated exemplary.

[0179] FIG. 11A illustrates the turn functions Θ.sub.cathode,outer(s) and Θ.sub.env,outer(s) for the phase controlled thyristor 100 from FIG. 10. A turn function difference of TFD1=0.248 was found for this example. FIG. 11B illustrates the turn functions Θ.sub.cathode,outer(s) and Θ.sub.env,outer(s) for a phase controlled thyristor similar to the one from FIG. 10, albeit with emitter shorts 128 at locations obtained in accordance with the present invention. A turn function difference of TFD1=0.091 was found for this example.

[0180] FIG. 12 shows a partial top view of the cathode side surface of a thyristor in accordance with the present invention, which may be manufactured according to one of the method variants as described above. A plurality of additional shorts 121 may be present in the further (n+)-doped emitter layer 122, mainly for controlling a non-trigger current. These are not to be regarded as emitter shorts, and do not form part of the Delaunay triangulation defined by points P.sub.i with iε{1; . . . ; N} in the cathode region at which the emitter shorts 128 are located.

[0181] FIG. 13 shows a portion of a surface mesh 910 for use in manufacturing a thyristor as shown in FIG. 9.

[0182] Exemplary diameters of the emitter shorts 128, i.e. the largest extension on the cathode side surface 102, may be between 30 μm up to 500 μm, preferably between 50 μm to 400 μm, and most preferably between 100 μm to 300 μm. A total surface area of the emitter shorts 128 is 2.5% to 20% of a surface are of the cathode region. That means that between 12 emitter shorts 128 per cm.sup.2 and 30000 dots per cm.sup.2 are provided on the cathode side surface 102. Exemplarily, if the emitter shorts 128 are small, more emitter shorts 128 will be present than if the emitter shorts 128 have a large diameter.

[0183] Preferably, in embodiments as described above and below, the conductivity types may be interchanged, i.e. all (n−)-, n-, or (n+)-layers and regions as described may be replaced by (p−)-, p-, or (p+)-layers and regions, respectively, and vice versa.

[0184] Unless stated otherwise, all doping concentrations N referred to in this patent application are net doping concentrations, where N is defined as N:=N.sub.D−N.sub.A for regions or layers in which a total density of donors N.sub.D is larger than a total density of acceptors N.sub.A, i.e. N.sub.D>N.sub.A, i.e. in particular for n-doped regions or layers; and as N:=N.sub.A−N.sub.D for regions or layers in which a total density of donors N.sub.D is smaller than a total density of acceptors N.sub.A, i.e. in particular for p-doped regions or layers. Preferably, in embodiments as described above, suffixes “−” and “+” after doping type indicators p, n are used to express relative net doping concentrations. In particular, a net doping concentration N(n+) of each (n+)-doped region or layer is larger than a net doping concentration N(n) of each (n)-doped region or layer, which in turn is larger is larger than a net doping concentration N(n−) of each (n−)-doped region or layer. Likewise, a net doping concentration N(p+) of each (p+)-doped region or layer is larger than a net doping concentration N(p) of each (p)-doped region or layer, which in turn is larger than a net doping concentration N(p−) of each (p−)-doped region or layer. Preferably. N(n+)≧N(p), N(n)≧N(p−), N(p+)≧N(n) and/or N(p)≧N(n−); most preferably, N(n+)>N(p), N(n)>N(p−), N(p+)>N(n) and/or N(p)>N(n−) also hold. On the other hand, where identical suffixes are used with regard to different layers or regions, this shall preferably not be construed to imply that the doping concentrations of said different layers or regions are identical.

[0185] Preferably, in embodiments as described above and below, where a doping concentration or net doping concentration of a region or layer is referred to, this is preferably to be understood as a maximum net doping concentration within said region or layer. In particular for doped regions or layers which were formed including a dopant diffusion process step, a local net doping concentration decays in one or more spatial directions from an area within the region or layer, in which area the local doping concentration equals the maximum net doping concentration.

[0186] Unless stated otherwise, it is assumed that throughout this patent application, a statement a≈b implies that |a−b|/(|a|+|b|)<10.sup.−1, preferably |a−b|/(|a|+|b|)<10.sup.−2, wherein a and b may represent arbitrary variables as described and/or defined anywhere in this patent application, or as otherwise known to a person skilled in the art. Further, a statement that a is at least approximately equal or at least approximately identical to b implies that a≈b, preferably a=b. Further, unless stated otherwise, it is assumed that throughout this patent application, a statement a>>b implies that a>10b, preferably a>100b; and statement a<<b implies that 10a<b, preferably 100a<b.

[0187] It should be noted that the term “comprising” does not exclude other features, in particular elements or steps, and that the indefinite article “a” or “an” does not exclude the plural. Also elements described in association with different embodiments may be combined. It should also be noted that reference signs in the claims shall not be construed as limiting the scope of the claims.

[0188] It will be appreciated by those skilled in the art that the present invention can be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The presently disclosed embodiments are therefore considered in all respects to be illustrative and not restricted. The scope of the invention is indicated by the appended claims rather than the foregoing description and all changes that come within the meaning and range and equivalence thereof are intended to be embraced therein.

[0189] Preferred embodiments of the present invention, in particular as described above, may be realized as detailed in the items listed below, advantageously in combination with one or more of the features as detailed above. [0190] 1) A thyristor, in particular a phase control thyristor, comprising: [0191] a) a semiconductor slab, in particular a semiconductor waver or die, in which a thyristor (100, 100′) structure is formed, [0192] b) a cathode metallization (114) formed on a cathode region on a cathode side (102) surface of the semiconductor slab, [0193] c) a gate metallization (118) formed on a gate region on the cathode side surface of the semiconductor slab, [0194] d) a plurality of N discrete emitter shorts (128), arranged at points P.sub.i in the cathic qu [0195] e) the points P.sub.i defining a Delaunay triangulation comprising a plurality of triangles T.sub.j with jε{1; . . . ; M}, [0196] characterized in that [0197] f) for a first subset of triangles T.sub.l with lεS.sub.1εS.sub.1⊂{1; . . . ; M}, [0198] g) with each triangle T.sub.l being characterized by a geometric quantity having values q.sub.T,j with lεS.sub.1⊂{1; . . . ; M}, said geometric quantity having a mean value μ, and [0199] i) a coefficient of variation of the values q.sub.T,l with lεS.sub.1 is smaller than 0.1, preferably smaller than 0.05, and/or [0200] ii) a skewedness of the geometric quantities q.sub.T,l with lεS.sub.1 is smaller than 5, preferably smaller than 1, and/or [0201] iii) a Kurtosis of the geometric quantities q.sub.T,J with lεS.sub.1 is smaller than 20, preferably smaller than 10, and/or [0202] iv) for a second subset of triangles T.sub.m with mεS.sub.2⊂S.sub.1, for which the respective geometric quantities q.sub.T,m with mεS.sub.2 deviate from the mean value by more than a predetermined amount, in particular by more than 30%. [0203] (1) a quotient of a standard deviation of the quantities q.sub.T,m with mεS.sub.2 and a mean squared value of the geometric quantity q.sub.T,j with lεS.sub.1 is less than 1, preferably less than 0.1, and/or [0204] (2) a quotient of a number of triangles in the second subset and a number of triangles in the first subset is less than 1.0×10.sup.−2, preferably less than 0.5×10.sup.−3. [0205] 2) A thyristor according to item 1, characterized in that for all triangles in the first subset, the geometric quantity q.sub.T,l is defined as either [0206] a) a length D.sub.l of the longest edge in each triangle T.sub.l with lεS.sub.1, [0207] b) a smallest angle α.sub.min,j in each triangle T.sub.l with lεS.sub.1, [0208] c) a largest angle in each triangle T.sub.l with lεS.sub.1, [0209] d) a radius r.sub.min,j of a circle inscribed in each triangle T.sub.l with lεS.sub.1, [0210] e) a radius r.sub.max,l of a circle circumscribed around each triangle T.sub.l with lεS.sub.1, or [0211] f) a quality index q.sub.l given by q.sub.j=r.sub.min,j/r.sub.max,j for each triangle T.sub.l with lεS.sub.1. [0212] 3) A thyristor according to one of the previous items, characterized in that the first subset comprises only triangles located within a circle C with a diameter d.sub.C circumscribing the gate electrode. [0213] 4) A thyristor according to one of the previous items, characterized in that the first subset comprises only triangles located within a circle C′, said circle C′ being concentric to C and having a diameter d.sub.C′ with d.sub.C′>0.75d.sub.C, preferably d.sub.C′>0.9d.sub.C. [0214] 5) A thyristor according to one of the previous items, characterized in that the number of triangles in the first subset is larger than 1000, preferably larger than 2000. [0215] 6) A thyristor, in particular a phase control thyristor, comprising: [0216] a) a semiconductor slab, in particular a semiconductor waver or die, in which a thyristor (100, 100′) structure has been formed, [0217] b) a cathode metallization (114) formed on a cathode region on a cathode side (102) surface of the semiconductor slab, [0218] c) a gate metallization (118) formed on a gate region on the cathode side surface of the semiconductor slab, [0219] d) a plurality of N discrete emitter shorts (128), arranged at points P.sub.i in the cathode region, said points having point locations x.sub.i, with iε{1; . . . ; N}, [0220] e) the points P.sub.i defining a Delaunay triangulation comprising a plurality of triangles T.sub.j with jε{1; . . . ; M}, [0221] characterized in that [0222] f) for a first subset of points P.sub.l with lεS.sub.1⊂{1; . . . ; N}, [0223] g) with each point P, being characterized by a geometric quantity having values q.sub.P,l with lεS.sub.1⊂{1; . . . ; N}, said geometric quantity having a mean value μ, and [0224] i) a coefficient of variation of the values q.sub.P,i with lεS.sub.1 is smaller than 0.1, preferably smaller than 0.05, and/or [0225] ii) a skewedness of the geometric quantities q.sub.P,l with lεS.sub.1 is smaller than 5, preferably smaller than 1, and/or [0226] iii) a Kurtosis of the geometric quantities q.sub.P,l with lεS.sub.1 is smaller than 20, preferably smaller than 10, and/or [0227] iv) for a second subset of triangles T.sub.m with mεS.sub.2⊂S.sub.1 for which the respective geometric quantities q.sub.P,m with mεS.sub.2 deviate from the mean value by more than a predetermined amount, [0228] (1) a quotient of a standard deviation of the quantities q.sub.P,m with mεS.sub.2 and a mean squared values of the geometric quantity q.sub.P,j with lεS.sub.1⊂{1; . . . ; N} is less than 1, preferably less than 0.1, and/or [0229] (2) a quotient of a number of triangles in the second subset and a number of triangles in the first subset is less than 1.0×10.sup.−2, preferably less than 0.5×10.sup.−3. [0230] 7) A thyristor according to item 6, characterized in that for all points in the first subset, the geometric quantities q.sub.T,l are defined as either [0231] a) a number N.sub.edges,l of edges connected to each point P.sub.l with lεS.sub.1, [0232] b) a number N.sub.triangles,l of triangles sharing each point P.sub.l with lεS.sub.1, [0233] c) a length l.sub.min,l of a shortest edge connected to each point P.sub.l with lεS.sub.1, [0234] d) a length l.sub.max,l of a longest edge connected to each point P.sub.l with lεS.sub.1, or [0235] e) a Volume V.sub.l of Voronoi cell associated with each point P.sub.l with lεS.sub.1. [0236] 8) A thyristor according to one of items 6 or 7, characterized in that the first subset comprises only triangles located within a circle C with a diameter d.sub.C circumscribing the gate electrode. [0237] 9) A thyristor according to one of items 6 through 8, characterized in that the first subset comprises only points located within a circle C′, said circle C′ being concentric to C and having a diameter d.sub.C′ with d.sub.C′>0.75d.sub.C, preferably d.sub.C>0.9d.sub.C. [0238] 10) A thyristor according to one of items 6 through 9, characterized in that the number of points in the first subset is larger than 1000, preferably larger than 2000. [0239] 11) A method for manufacturing a thyristor, in particular a phase control thyristor, the method comprising the steps of [0240] a) forming a thyristor structure in a semiconductor slab, in particular a semiconductor wafer or die, [0241] b) defining a cathode region on cathode side surface (102) of the semiconductor slab, [0242] c) defining a shorts region as a subregion of the cathode region, [0243] d) determining, by means of a meshing algorithm, a surface mesh (910) within the shorts region, said surface mesh comprising a plurality of points P.sub.i with iε{1; . . . ; N}, [0244] e) forming a discrete emitter short at a location of each point P.sub.i with iε{1; . . . ; N}, and [0245] f) forming a cathode metallization on the cathode region. [0246] 12) A method for manufacturing a thyristor, in particular a phase control thyristor, the method comprising the steps of [0247] a) forming a thyristor structure in a semiconductor slab, in particular a semiconductor wafer or die, [0248] b) defining a cathode region on cathode side surface (102) of the semiconductor slab, [0249] c) defining a shorts region as a subregion of the cathode region, [0250] d) determining, by means of a meshing algorithm, a surface mesh (910) within the shorts region, said surface mesh comprising a plurality of cells C.sub.j, with each cell delimited by a plurality of edges e.sub.jk with jε{1; . . . ; M} and kε{1; 2; 3; . . . }, [0251] e) forming a discrete emitter short at one location within each cell or at one location on each edge, and [0252] f) forming a cathode metallization on the cathode region. [0253] 13) The method according to one of items 11 or 12, characterized in that the meshing algorithm is a Delaunay technique algorithm. [0254] 14) The method according to one of items 11 through 13, characterized in that the meshing algorithm is based on an advancing front method. [0255] 15) The method according to one of items 11 through 14, characterized in that a minimum distance d.sub.gate between the gate region and the shorts region, in particular a minimum distance d.sub.gate between any parallel segments of the gate region and a boundary of the shorts region, respectively, is greater than a predetermined distance D.sub.gate.

LIST OF REFERENCE SIGNS

[0256] 100 phase controlled thyristor [0257] 100′ phase controlled thyristor with main and auxiliary transistors [0258] 102 cathode side [0259] 104 anode side [0260] 106 (n.sup.+)-doped cathode emitter layer [0261] 108, 108′ p-doped base layer [0262] 110 n-doped base layer [0263] 112 p-doped anode layer [0264] 114 cathode metalrization [0265] 116 anode metallization [0266] 118 gate metallization [0267] 120 auxiliary thyristor [0268] 121 additional shorts [0269] 122 additional (n.sup.+)-doped cathode emitter of auxiliary thyristor [0270] 124 additional cathode metallization of auxiliary thyristor [0271] 126 main thyristor [0272] 128 emitter shorts [0273] 130 gate of auxiliary thyristor [0274] 300 process mask [0275] 304 mask short location [0276] 306 mask gate region [0277] 310 mask region close to main gate beam [0278] 312 mask region close to middle line [0279] 314 middle line [0280] 316 main gate beam location in mask [0281] 318 pilot gate region in mask [0282] 330 exemplary region where two or more subregions adjoin [0283] 400 exemplary polygon [0284] 401 gate region boundary [0285] 411 inner boundary of the cathode region [0286] 412 outer boundary of the cathode region [0287] 421 inner envelope of emitter shorts distribution [0288] 422 outer envelope of emitter shorts distribution

PHASE CONTROL THYRISTOR

Inventors

Cpc classification

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H01L29/7428

ELECTRICITY

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H01L29/74

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H01L29/66363

ELECTRICITY

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H01L29/0839

ELECTRICITY

International classification

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H01L29/74

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H01L29/66

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H01L29/08

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Abstract

Claims

Description