PULSE MODULATOR

Abstract

A pulse modulator comprises a solid state power switch having a source, a drain, a gate and a separate gate drive connected to ground. One pulse modulator comprises a plurality of stages connected as an induction adder. Each stage includes a plurality of cells and at least some of the cells each include a solid state power switch having a source, a drain, a gate and a separate gate drive connected to ground to control the discharge of a capacitor. In one embodiment the solid state power switch is a power MOSFET.

Claims

1. A pulse modulator comprising: a solid state power switch having a source, a drain, a gate and a separate gate drive connected to ground.

2. The pulse modulator as claimed in claim 1, wherein the solid state power switch comprises a plurality of solid state power switches, the pulse modulator further comprising a plurality of stages, each stage including a plurality of cells, and at least some of the cells each including a-at least one of the solid state power switches.

3. The pulse modulator as claimed in claim 2, wherein the plurality of stages is connected as an induction adder.

4. The pulse modulator as claimed in claim 1, wherein the solid state power switch is a power MOSFET.

5. The pulse modulator as claimed in claim 2 wherein said at least some of the cells each include a gate driver and a balun, the gate driver being connected to the gate of the solid state power switch via the balun.

6. The pulse modulator as claimed in claim 2 wherein said at least some of the cells each include a Zener diode via which the separate gate drive is connected to ground.

7. The pulse modulator as claimed in claim 1, further including a diode in series with the solid state power switch.

8. The pulse modulator as claimed in claim 7 wherein the diode is a Schottky diode.

9. The pulse modulator as claimed in claim 2, wherein said at least some of the cells each include more than one of said solid state power switches having a source, a drain, a gate and a separate gate drive connected to ground.

10. The pulse modulator as claimed in claim 2, wherein each stage includes a magnetic induction core, a single turn primary winding and a single turn secondary winding and the secondary windings are connected in series.

11. The pulse modulator as claimed in claim 2, wherein said at least some of the cells each include a capacitor which is connected to be discharged by the solid state power switch to generate pulses.

12. The pulse modulator as claimed in claim 1, wherein the pulse modulator is operative to generate pulses having a pulse rise time of less than 5 ns and pulse length in the range 15 ns to 20 ns.

13. The pulse modulator as claimed in claim 1, wherein the pulse modulator is operative to generate pulses having repetition rate of greater than 1000 pps.

14. The pulse modulator as claimed in claim 13, wherein the pulse modulator is operative to generate pulses having repetition rate of greater than 1 megaHertz.

15. The pulse modulator as claimed in claim 1, wherein the pulse modulator is aoperative to generate pulses with a peak power of the order of tens of megawatts.

16. The pulse modulator as claimed in claim 15, wherein the pulse modulator is operative to generate pulses with a peak power in the range 30 to 40 MW.

17. The pulse modulator as claimed in claim 2, wherein each stage has dimensions of less than or equal to 120 mm×240 mm.

18. The pulse modulator as claimed in claim 2, wherein the cells of the plurality of cells are nominally identical.

19. The pulse modulator as claimed in claim 2, further including a non-linear snubber network to dissipate reflected energy in at least one of the cells.

20. A system comprising a pulse modulator as claimed in claim 1, further including a load, the pulse modulator being connected to apply pulses across the load.

21. (canceled)

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Some embodiments of the present invention will now be described by of example only, and with reference to the accompanying drawings, in which:

[0017] FIG. 1 schematically illustrates in longitudinal cross section a pulse modulator in accordance with the invention;

[0018] FIG. 2 schematically illustrates a stage of the pulse modulator of FIG. 1;

[0019] FIG. 3 is schematic diagram illustrative of the inductive adder of the pulse modulator of FIG. 1;

[0020] FIG. 4 is a schematic circuit diagram of a single FET cell;

[0021] FIG. 5 illustrates practical switching limitations of an FET;

[0022] FIG. 6 illustrates a component of the single cell shown in FIG. 4;

[0023] FIGS. 7a and 7b illustrate the outputs from alternative configurations of an FET cell;

[0024] FIG. 8 is a schematic circuit diagram of a dual FET cell of another pulse modulator in accordance with the invention; and

[0025] FIG. 9 is a schematic circuit diagram of a cell of another pulse modulator in accordance with the invention.

DETAILED DESCRIPTION

[0026] With reference to FIG. 1, a pulse modulator 1 includes twelve identical stages 2 stacked between a ground plate 3 and an end plate 4. One stage 5 is shown in plan view in FIG. 2 and has dimensions of 164 mm×164 mm with a depth of 15 mm. The distance between the ground plate 3 and end plate 4 is approximately 400 mm. If more or fewer stages are included the distance is greater or less than 400 mm. The stage 5 carries eight cells 6, each cell including a single solid state FET switch. The stage 5 includes a single turn primary winding and a single turn secondary winding on a magnetic core 7 for each cell. The secondary windings of all of the stages 2 are connected in series, as shown schematically in FIG. 3, to provide a twelve-stage inductive adder. The output voltage on the secondary winding 8 is the sum of all of the voltages appearing on the primary windings and is taken from the pulse modulator 1 via a coaxial output 9.

[0027] With reference to FIG. 4, a single cell 6 includes an input 10 to which the output of a capacitor charger is applied to a capacitor 11 of 100 nF via a diode 12.

[0028] The discharge of the capacitor 11 is controlled using solid state switch 13 which in this embodiment is a MOSFET 13.

[0029] In a power MOSFET, the theoretical carrier transit time from drain to source is on the order of 200 ps. The gate driver and the MOSFET parasitic inductance and capacitance determine the achievable switching speed.

[0030] With reference to FIG. 5, which a switching model of a MOSFET showing the most important parasitic components, assuming the trans-conductance of the MOSFET is large, the switch closure time, Tr, can be estimated as:

[00001]$T_r\approx \frac{C_m.Math.V.Math.R_g-L_s.Math.I}{V_g-V_{\mathrm{Miller}}}$

[0031] where V is the switched voltage, I is the switched current, L.sub.s is the source parasitic inductance, R.sub.g is the gate resistance, V.sub.g is the gate voltage, C.sub.m is the Miller capacitance, and V.sub.Miller is the Miller voltage. The Miller voltage is the voltage on the gate during switch transition and is greater than the threshold voltage.

[0032] Thus, by using a power switch with a separate gate drive connected to ground, the influence of the source inductance on the switching time can be minimised to obtain the fastest switching time possible from a device of this rating. The MOSFET 13 in this embodiment is an Infineon IPL60R199CP as shown in FIG. 6 and has a low parasitic inductance of 1.83 nH separate pin-outs for the gate drive ground and the source ground.

[0033] The MOSFET 13 is driven by a high-speed MOSFET gate driver 14 via a balun 15 which provides an isolated gate drive. The MOSEFET 13 has a separate gate drive 13a connected to ground. A Zener diode 16 is connected between the gate of the MOSFET 13 and ground. The balun 15 enables a much faster switch time to be achieved, as illustrated in FIG. 7, where the circuit without a balun is shown in FIG. 7(a) and with a balun in FIG. 7(b).

[0034] In one embodiment, the operating voltage/current is 30 kV/1200 A, and the impedance is 25 Ohms. The pulse rise time (10-90%) is 2 ns-5 ns, the pulse length is 15 ns-20 ns and the repetition rate is 1000 pulses per second with pulse jitter of 100 picoseconds (1σ) and a maximum pulse ripple of 5%. The pulse peak power is 30 MW.

[0035] In another pulse modulator, illustrated in FIG. 8, a dual FET switching cell 17 includes two circuits 18 and 19 similar to that shown in FIG. 4 and have outputs which are combined to switch a capacitor 20.

[0036] With reference to FIG. 9, another pulse modulator includes a Schottky diode 21 in series with FET 22 having a separate gate drive 22a. The diode 21 prevents conduction of the switch parasitic antiparallel diode which might otherwise result in the switch latching into conduction. A non-linear snubber network 23 dissipates reflected energy. These enhancements are not essential to a pulse modulator in accordance with the invention but may allow it to operate under more demanding conditions.

[0037] The present invention may be embodied in other specific forms without departing from its spirit or essential characteristics. The described embodiments are to be considered in all respects only as illustrative and not restrictive. The scope of the invention is, therefore, indicated by the appended claims rather than by the foregoing description. All changes that come within the meaning and range of equivalency of the claims are to be embraced within their scope.