STATIC RAM FOR DIFFERENTIAL POWER ANALYSIS RESISTANCE

Abstract

The present invention discloses a static RAM for defensive differential power consumption analysis, comprising a replica bit-line circuit, a decoder, an address latch circuit, a clock circuit, n-bit memory arrays, n-bit data selectors, n-bit input circuit and n-bit output circuits; the output circuits comprises a sensitivity amplifier and a data latch circuit; the 1st PMOS tube, the 2nd PMOS tube, the 3rd PMOS tube, the 4th PMOS tube, the 5th PMOS tube, the 6th PMOS tube, the 7th PMOS tube, the 1st NMOS tube, the 2nd NMOS tube, the 3rd NMOS tube, the 4th NMOS tube and the 5th NMOS tube constitute the sensitivity amplifier; two NOR gates, the 8th PMOS tube, the 9th PMOS tube, the 10th PMOS tube, the 11th PMOS tube, the 6th NMOS tube, the 7th NMOS tube, the 8th NMOS tube, the 9th NMOS tube and the 10th NMOS tube constitute the data latch circuit; the present invention is characterized in that energy consumption in each working cycle is basically identical, which is provided with higher capability in defense of differential power analysis.

Claims

1. A static RAM for Differential Power Analysis Resistance, comprising: a replica bit-line circuit; a decoder; an address data latch circuit; a clock circuit; n-bit memory arrays; n-bit data selectors; n-bit input circuits; and n-bit output circuits, wherein n-bit is an integral equal to or over 1, wherein the said decoder is connected to the said replica bit-line circuit, the said address data latch circuit, the said n-bit memory arrays and the said n-bit data selectors respectively, and the said clock circuit is connected to the said replica bit-line circuit, the said n-bit input circuits, the said n-bit output circuits respectively, wherein the jth input circuit is connected to the jth data selector; the said replica bit-line circuit is connected to the said n-bit output circuits, the said data selector j is connected to the said memory array j and the said output circuit j respectively, j=1, 2, . . . , n, wherein the said output circuit comprises a sensitivity amplifier and a data latch circuit, which is characterized in that the said sensitivity amplifier comprises a 1.sup.st, a 2.sup.nd, a 3.sup.rd, a 4.sup.th, a 5.sup.th, a 6.sup.th and a 7.sup.th PMOS tubes and a 1.sup.st, a 2.sup.nd, the 3.sup.rd, a 4.sup.th and a 5.sup.th NMOS tubes, wherein a source of the 1.sup.st PMOS tube, a source of the 4.sup.th PMOS tube and a source of the 5.sup.th PMOS tube are connected to the power supply respectively; a drain of the 1.sup.st PMOS tube and a source of the 2.sup.nd PMOS tube are connected to a source of the 3.sup.rd PMOS tube; a drain of the 2.sup.nd PMOS tube, a grid of the 3.sup.rd PMOS tube, a drain of the 4.sup.th PMOS tube, a drain of the 6.sup.th PMOS tube, a drain of the 1.sup.st NMOS tube and a grid of the 2.sup.nd NMOS tube are connected to a drain of the 4.sup.th NMOS tube respectively, and a common connection thereof is a 1.sup.st output terminal of the said sensitivity amplifier, wherein a grid of the 2.sup.nd PMOS tube, a drain of the 3.sup.rd PMOS tube, a drain of the 5.sup.th PMOS tube, a drain of the 7.sup.th PMOS tube, a grid of the 1.sup.st NMOS tube and a drain of the 2.sup.rd NMOS tube are connected to a drain of the 5.sup.th NMOS tube respectively, and a common connection thereof is a 2.sup.nd input terminal of the said sensitivity amplifier, wherein a grid of the 1.sup.st PMOS tube and a grid of the 4.sup.th NMOS tube are connected to a grid of the 5.sup.th NMOS tube, and a common connection thereof is a SADIS terminal of the said sensitivity amplifier, wherein the SADIS terminal of the said sensitivity amplifier is used to receive discharging signals from sensitivity amplifier, wherein a grid of the 4.sup.th PMOS tube is connected to a grid of the 5.sup.th PMOS tube, and a common connection thereof is a SAPRE terminal of the said sensitivity amplifier, the SAPRE terminal of the said sensitivity amplifier is used to receive charging signals from the sensitivity amplifier, wherein a grid of the 6.sup.th PMOS tube is connected to a grid of the 7.sup.th PMOS tube, and a common connection thereof is a SASEL terminal of the said sensitivity amplifier, the SASEL terminal of the said sensitivity amplifier is used to receive reading signals from the sensitivity amplifier, wherein a grid of the 3.sup.rd NMOS tube serves as a SAE terminal of the said sensitivity amplifier, the SAE terminal of the said sensitivity amplifier is used to receive enabling signals from the sensitivity amplifier, wherein a source of the 1.sup.st NMOS tube and a source of the 2.sup.nd NMOS tube are connected to the drain of the 3.sup.rd NMOS tube respectively, and a source of the 3.sup.rd NMOS tube, a source of the 4.sup.th NMOS tube and a source of the 5.sup.th NMOS tube are grounded respectively, wherein a source of the 6.sup.th PMOS tube serves as a 1.sup.st signal input terminal of the said sensitivity amplifier, and a source of the 7.sup.th PMOS tube serves as a 2.sup.nd signal input terminal of the said sensitivity amplifier, wherein the 1.sup.st signal input terminal of the said sensitivity amplifier serves as a BL terminal of the output circuit of the said static RAM, and the 2.sup.nd signal input terminal of the said sensitivity amplifier serves as a BLB terminal of the output circuit of the said static RAM, wherein the BL terminal and the BLB terminal of the output circuit of the said static RAM are used to connect the data selector to receive bit-line pairs, wherein the said data latch circuit comprises two NOR gates, a 8.sup.th PMOS tube, a 9.sup.th PMOS tube, a 10.sup.th PMOS tube, a 11.sup.th PMOS tube, a 6.sup.th NMOS tube, a 7.sup.th NMOS tube, a 8.sup.th NMOS tube, a 9.sup.th NMOS tube and a 10.sup.th NMOS tube, wherein the said two NOR gates comprise the 1.sup.st NOR gate and the 2.sup.nd NOR gate, and each of the said 1.sup.st and 2.sup.nd NOR gates comprises a 1.sup.st input terminal, a 2.sup.nd input terminal and an output terminal, wherein a source of the 9.sup.th PMOS tube and a grid of the 6.sup.th NMOS tube are connected to the power supply, the 1.sup.st input terminal of the 1.sup.st NOR gate serves as a 1.sup.st input terminal of the said data latch circuit, and the 1.sup.st input terminal of the said data latch circuit is connected to the 1.sup.st output terminal of the said sensitivity amplifier, wherein the 2.sup.nd input terminal of the 1.sup.st NOR gate, the output terminal of the 2.sup.nd NOR gate and a grid of the 10.sup.th PMOS tube are connected to a grid of the 10.sup.th NMOS tube, wherein the output terminal of the 1.sup.st NOR gate, the 1.sup.st input terminal of the 2.sup.nd NOR gate, a source of the 6.sup.th NMOS tube, a source of the 11.sup.th PMOS tube and a grid of the 8.sup.th PMOS tube are connected to a grid of the 9.sup.th NMOS tube, wherein the 2.sup.nd input terminal of the 2.sup.nd NOR gate serves as a 2.sup.nd input terminal of the said data latch circuit, and the 2.sup.nd input terminal of the said data latch circuit is connected to the 2.sup.nd input terminal of the said sensitivity amplifier, wherein a drain of the 9.sup.th PMOS tube is connected to a source of the 8.sup.th PMOS tube, wherein a grid of the 9.sup.th PMOS tube is connected to a grid of the 7.sup.th NMOS tube, and a common connection thereof is a OUTDIS terminal of the said data latch circuit, and the OUTDIS terminal of the said data latch circuit is used to receive discharging control signals from the output terminal, wherein a source of the 10.sup.th PMOS tube, a drain of the 10.sup.th PMOS tube, a drain of the 10.sup.th NMOS tube, a source of the 10.sup.th NMOS tube, a source of the 8.sup.th NMOS tube, a source of the 9.sup.th NMOS tube, a source of the 7.sup.th NMOS tube and a grid of the 11.sup.th PMOS tube are grounded, and a drain of the 6.sup.th NMOS tube and a drain of the 11.sup.th PMOS tube are connected to a grid of the 8.sup.th NMOS tube, wherein a drain of the 8.sup.th PMOS tube, a drain of the 8.sup.th NMOS tube and a drain of the 9.sup.th NMOS tube are connected to a drain of the 7.sup.th NMOS tube, and common connection thereof is an output terminal of the said data latch circuit, and the output terminal of the said data latch circuit serves as an output terminal of the output circuit of the said static RAM.

2. The static RAM for Differential Power Analysis Resistance according to claim 1, wherein the said input circuit comprises a 11.sup.th NMOS tube, a 12.sup.th NMOS tube, a 13.sup.th NMOS tube, a 14.sup.th NMOS tube, a 15.sup.th NMOS tube, a 16.sup.th NMOS tube, a 17.sup.th NMOS tube, a 18.sup.th NMOS tube, a 19 NMOS tube, a 20.sup.th NMOS tube, a 21.sup.st NMOS tube, a 12.sup.th PMOS tube, a 13.sup.th PMOS tube, a 14.sup.th PMOS tube, a 15.sup.th PMOS tube, a 16.sup.th PMOS tube, a 17.sup.th PMOS tube, a 18.sup.th PMOS tube, a 19.sup.th PMOS tube, a 20.sup.th PMOS tube, a 21.sup.st PMOS tube, a 22.sup.nd PMOS tube, a 23.sup.rd PMOS tube and a 24.sup.th PMOS tube, wherein a source of the 12.sup.th PMOS tube, a source of the 14.sup.th PMOS tube, a source of the 16.sup.th PMOS tube, a source of the 17.sup.th PMOD tube, a source of the 18.sup.th PMOS tube, a source of the 20.sup.th PMOS tube, a source of the 22.sup.nd PMOS tube, a source of the 23.sup.rd PMOS tube and a source of the 24.sup.th PMOS tube are connected to the power supply respectively; a drain of the 12.sup.th PMOS tube is connected to a source of the 13.sup.th PMOS tube, wherein a drain of the 13.sup.th PMOS tube, a drain of the 11.sup.th NMOS tube, a drain of the 15.sup.th PMOS tube and a drain of the 13.sup.th NMOS tube, a grid of the 16.sup.th PMOS tube are connected to a grid of the 15.sup.th NMOS tube, wherein a source of the 11.sup.th NMOS tube is connected to a drain of the 12.sup.th NMOS tube, wherein a source of the 12.sup.th NMOS tube, a source of the 14.sup.th NMOS tube, a source of the 15.sup.th NMOS tube, a source of the 19.sup.th NMOS tube and a source of the 21.sup.st NMOS tube are grounded respectively, wherein a drain of the 14.sup.th PMOS tube is connected to a source of the 15.sup.th PMOS tube, wherein a source of the 13.sup.th NMOS tube is connected to a drain of the 14.sup.th NMOS tube, wherein a grid of the 14.sup.th PMOS, a grid of the 14.sup.th NMOS tube, a drain of the 15.sup.th NMOS tube, a drain of the 16.sup.th PMOS tube, a grid of the 17.sup.th PMOS tube, a grid of 16.sup.th NMOS tube, a grid of 19.sup.th NMOS tube are connected to a grid of the 20.sup.th PMOS tube, wherein a drain of the 17.sup.th PMOS tube, a drain of the 16.sup.th NMOS tube, a grid of the 17.sup.th NMOS tube are connected to a grid of the 18.sup.th PMOS tube, wherein a drain of the 17.sup.th NMOS tube, a drain of the 18.sup.th PMOS tube and a source of the 18.sup.th NMOS tube are connected to the source of the 19.sup.th PMOS tube, wherein a drain of the 18.sup.th NMOS tube, a drain of the 19.sup.th PMOS tube are connected to a drain of the 22.sup.nd PMOS tube, and a common connection thereof is a Pt output terminal of the said input circuit, wherein a drain of the 19.sup.th NMOS tube, a drain of the 20.sup.th PMOS tube, a source of the 20.sup.th NMOS tube are connected to a source of the 21.sup.st PMOS tube, wherein a drain of the 20.sup.th NMOS tube, a drain of the 21.sup.st PMOS tube are connected to a drain of the 23.sup.rd PMOS tube, and a common connection thereof is a 2.sup.nd output terminal of the said input circuit, wherein a grid of the 12.sup.th PMOS tube, a grid of the 18.sup.th NMOS tube, a grid of the 20.sup.th NMOS tube, a grid of the 13.sup.th NMOS tube and a grid of the 21.sup.st NMOS tube are connected to a grid of the 24.sup.th PMOS tube, and a common connection thereof is a clock signal input terminal of the said input circuit, used to receive write-in signals output from the said clock circuit, wherein a grid of the 12.sup.th NMOS tube, a grid of the 15.sup.th PMOS tube, a drain of the 24.sup.th PMOS tube, a drain of the 21.sup.st NMOS tube, a grid of the 19.sup.th PMOS tube are connected to a grid of the 21.sup.st PMOS tube, and a common connection thereof is an inverted clock signal input terminal of the said input circuit, used to receive inverted signals among write-in signals output from the said clock module, wherein a grid of the 13.sup.th PMOS tube is connected to a grid of the 11.sup.th NMOS tube, and a common connection thereof is a signal input terminal of the said input circuit, used to receive external data, wherein a grid of the 22.sup.nd PMOS tube is connected to a grid of the 23.sup.rd PMOS tube, and a common node is a charging signal input terminal of the said input circuit, used to receive charging signals output from the said clock circuit.

Description

DESCRIPTION OF DRAWINGS

[0009] FIG. 1 is the structural block diagram for the present invention;

[0010] FIG. 2 is the structural block diagram for the memory array of the present invention;

[0011] FIG. 3 is the circuit diagram for the output circuit of the present invention;

[0012] FIG. 4 is the timing diagram for the output circuit of the present invention;

[0013] FIG. 5 is the energy consumption distribution diagram for the output circuit of the present invention;

[0014] FIG. 6 is the energy consumption distribution diagram for existing output circuit;

[0015] FIG. 7 is the diagram showing superposition of supply current produced by reading of 100 groups of data by the present invention;

[0016] FIG. 8 is the diagram showing superposition of supply voltage produced by reading of 100 groups of data by existing static RAM;

[0017] FIG. 9 is the input circuit of the static RAM in Embodiment 2.

DESCRIPTION OF EMBODIMENTS

[0018] The present invention is further described as follows in combination with drawings and embodiments:

[0019] Embodiment A: shown in FIGS. 1, 2 and 3, a static RAM for Differential Power Analysis Resistance 1000, comprising a replica bit-line circuit 1100, a decoder 1200, an address data latch circuit 1300, a clock circuit 1400, n-bit memory arrays 1510-1-1510-n, n-bit data selectors 1520-1-1520-n, n-bit input circuits 1530-1-1530-n and n-bit output circuits 1540-1 thru 1540-n, where n is an integral equal to or over 1. The said decoder 1200 is connected to the said replica bit-line circuit 1100, the said address data latch circuit 1300, the said n-bit memory arrays 1510-1-1510-n and the said n-bit data selectors 1520-1-1520-n, respectively. The said clock circuit 1400 is connected to the said replica bit-line circuit 1100, the said n-bit input circuits 1530-1-1530-n, the said n-bit output circuits 1540-1-1540-n, respectively. The said input circuit j is connected to the said data selector j; the said replica bit-line circuit is connected to the said n-bit output circuits 1540-1-1540-n. The said data selector j is connected to the said memory array j and the said output circuit j, respectively, where j=1, 2, . . . , n. With reference to FIG. 2, array of memory units 1500-1-1500-n are illustrated.

[0020] With reference to FIG. 3, the said output circuit 1540 comprises a sensitivity amplifier 1541 and a data latch circuit 1542. The said sensitivity amplifier 1541 comprises a 1.sup.st PMOS tube P1, a 2.sup.nd PMOS tube P2, a 3.sup.rd PMOS tube P3, a 4.sup.th PMOS tube P4, a 5.sup.th PMOS tube P5, a 6.sup.th PMOS tube P6, a 7.sup.th PMOS tube P7 and a 1.sup.st NMOS tube N1, a 2.sup.nd NMOS tube N2, a 3.sup.rd NMOS tube N3, a 4.sup.th NMOS tube N4 a 5.sup.th NMOS tube N5. In detail, a source of the 1.sup.st PMOS tube P1, a source of the 4.sup.th PMOS tube P4 and a source of the 5.sup.th PMOS tube P5 are connected to the power supply VDD, respectively. A drain of the 1.sup.st PMOS tube P1 and a source of the 2.sup.nd PMOS tube P2 are connected to the source of the 3.sup.rd PMOS tube P3. A drain of the 2.sup.nd PMOS tube P2, a grid of the 3.sup.rd PMOS tube P3, a drain of the 4.sup.th PMOS tube P4, a drain of the 6.sup.th PMOS tube P6, a drain of the 1.sup.st NMOS tube N1 and a grid of the 2.sup.nd NMOS tube N2 are connected to a drain of the 4.sup.th NMOS tube N4, respectively, and a common connection thereof is the 1.sup.st output terminal SAOUT of the said sensitivity amplifier 1541. A grid of the 2.sup.nd PMOS tube P2, a drain of the 3.sup.rd PMOS tube P3, a drain of the 5.sup.th PMOS tube P5, a drain of the 7.sup.th PMOS tube P7, a grid of the 1.sup.st NMOS tube N1 and a drain of the 2.sup.nd NMOS tube N2 are connected to a drain of the 5.sup.th NMOS tube N5 respectively, and a common connection thereof is the 2.sup.nd input terminal SAOUTB of the said sensitivity amplifier 1541. A grid of the 1.sup.st PMOS tube P1 and a grid of the 4.sup.th NMOS tube N4 are connected to a grid of the 5.sup.th NMOS tube N5, and a common connection thereof is a SADIS terminal of the said sensitivity amplifier 1541. The SADIS terminal of the said sensitivity amplifier 1541 is used to receive discharging signals from sensitivity amplifier 1541. A grid of the 4.sup.th PMOS tube P4 is connected to a grid of the 5.sup.th PMOS tube, and a common connection thereof is a SAPRE terminal of the said sensitivity amplifier 1541, and the SAPRE terminal of the said sensitivity amplifier 1541 is used to receive charging signals from the sensitivity amplifier 1541. A grid of the 6.sup.th PMOS tube P6 is connected to a grid of the 7.sup.th PMOS tube P7, and a common connection thereof is a SASEL terminal of the said sensitivity amplifier 1541. The SASEL terminal of the said sensitivity amplifier 1541 is used to receive reading signals from the sensitivity amplifier 1541. A grid of the 3.sup.rd NMOS tube N3 serves as a SAE terminal of the said sensitivity amplifier 1541. The SAE terminal of the said sensitivity amplifier 1541 is used to receive enabling signals from the sensitivity amplifier 1541. A source of the 1.sup.st NMOS tube N1 and a source of the 2.sup.nd NMOS tube N2 are connected to a drain of the 3.sup.rd NMOS tube N3 respectively. A source of the 3.sup.rd NMOS tube N3, a source of the 4.sup.th NMOS tube N4 and a source of the 5.sup.th NMOS tube N5 are grounded VSS, respectively. A source of the 6.sup.th PMOS tube P6 serves as a 1.sup.st signal input terminal of the said sensitivity amplifier 1541. A source of the 7.sup.th PMOS tube P7 serves as a 2.sup.nd signal input terminal of the said sensitivity amplifier 1541. The 1.sup.st signal input terminal of the said sensitivity amplifier 1541 serves as BL terminal of the output circuit of the said static RAM. The 2.sup.nd signal input terminal of the said sensitivity amplifier 1541 serves as BLB terminal of the output circuit of the said static RAM. The BL terminal and the BLB terminal of the output circuit of the said static RAM are used to connect the data selector to receive bit-line pairs.

[0021] The said data latch circuit 1542 comprises two NOR gates G1, G2, a 8.sup.th PMOS tube P8, a 9.sup.th PMOS tube P9, a 10.sup.th PMOS tube P10, a 11.sup.th PMOS tube P11, a 6.sup.th NMOS tube N6, a 7.sup.th NMOS tube N7, a 8.sup.th NMOS tube N8, a 9.sup.th NMOS tube N9 and a 10.sup.th NMOS tube N10. In detail, each of the said NOR gates is provided with the 1.sup.st input terminal, the 2.sup.nd input terminal and the output terminal. The said two NOR gates comprise the 1.sup.st NOR gate G1 and the 2.sup.nd NOR gate G2. A source of the 9.sup.th PMOS tube P9 and a grid of the 6.sup.th NMOS tube N6 are connected to the power supply. A 1.sup.st input terminal of the 1.sup.st NOR gate G1 serves as a 1.sup.st input terminal of the said data latch circuit. The 1.sup.st input terminal of the said data latch circuit 1542 is connected to the 1.sup.st output terminal of the said sensitivity amplifier 1541. A 2.sup.nd input terminal of the 1.sup.st NOR gate G1, an output terminal of the 2.sup.nd NOR gate G2 and a grid of the 10.sup.th PMOS tube P10 are connected to a grid of the 10.sup.th NMOS tube N10, and a common connection thereof is marked as node 2. An output terminal of the 1.sup.st NOR gate G1, a 1.sup.st input terminal of the 2.sup.nd NOR gate G2, a source of the 6.sup.th NMOS tube N6, a source of the 11.sup.th PMOS tube P11 and a grid of the 8.sup.th PMOS tube P8 are connected to a grid of the 9.sup.th NMOS tube N9, and a common connection thereof is marked as node 1. A 2.sup.nd input terminal of the 2.sup.nd NOR gate serves as a 2.sup.nd input terminal of the said data latch circuit 1542. The 2.sup.nd input terminal of the said data latch circuit 1542 is connected to the 2.sup.nd input terminal of the said sensitivity amplifier 1541. The drain of the 9.sup.th PMOS tube P9 is connected to the source of the 8.sup.th PMOS tube P8. The grid of the 9.sup.th PMOS tube P9 is connected to the grid of the 7.sup.th NMOS tube N7, and a common connection thereof is OUTDIS terminal of the said data latch circuit 1542. The OUTDIS terminal of the said data latch circuit 1542 is used to receive discharging control signals from the output terminal Q of the data latch circuit 1542. A source of the 10.sup.th PMOS tube P10, a drain of the 10.sup.th PMOS tube P10, a drain of the 10.sup.th NMOS tube N10, the source of the 10.sup.th NMOS tube N10, a source of the 8.sup.th NMOS tube N8, a source of the 9.sup.th NMOS tube N9, a source of the 7.sup.th NMOS tube N7 and a grid of the 11.sup.th PMOS tube P11 are grounded. A drain of the 6.sup.th NMOS tube N6 and a drain of the 11.sup.th PMOS tube P11 are connected to a grid of the 8.sup.th NMOS tube N8. A drain of the 8.sup.th PMOS tube P8, a drain of the 8.sup.th NMOS tube N8 and a drain of the 9.sup.th NMOS tube N9 are connected to a drain of the 7.sup.th NMOS tube N7, and a common connection thereof is the output terminal of the said data latch circuit 1542. The output terminal of the said data latch circuit 1542 serves as the output terminal Q of the output circuit of the said static RAM.

[0022] As shown in FIG. 9, the said input circuit comprises a 11.sup.th NMOS tube N11, a 12.sup.th NMOS tube N12, a 13.sup.th NMOS tube N13, a 14.sup.th NMOS tube N14, a 15.sup.th NMOS tube N15, a 16.sup.th NMOS tube N16, a 17.sup.th NMOS tube N17, a 18.sup.th NMOS tube N18, a 19.sup.th NMOS tube N19, a 20.sup.th NMOS tube N20, a 21.sup.st NMOS tube N21, a 12.sup.th PMOS tube P12, a 13.sup.th PMOS tube P13, a 14.sup.th PMOS tube P14, a 15.sup.th PMOS tube P15, a 16.sup.th PMOS tube P16, a 17.sup.th PMOS tube P17, a 18.sup.th PMOS tube P18, a 19.sup.th PMOS tube P19, a 20.sup.th PMOS tube P20, a 21.sup.st PMOS tube P21, a 22.sup.nd PMOS tube P22, a 23.sup.rd PMOS tube P23 and a 24.sup.th PMOS tube P24.

[0023] In detail, a source of the 12.sup.th PMOS tube P12, the 14.sup.th PMOS tube P14, the 16.sup.th PMOS tube P16, the 17.sup.th PMOD tube P17, the 18.sup.th PMOS tube P18, the 20.sup.th PMOS tube P20, the 22.sup.nd PMOS tube P22, the 23.sup.rd PMOS tube P23 and the 24.sup.th PMOS tube P24 is connected to the power supply respectively. A drain of the 12.sup.th PMOS tube P12 is connected to a source of the 13.sup.th PMOS tube P13. A drain of the 13.sup.th PMOS tube P13, a drain of the 11.sup.th NMOS tube N11, a drain of the 15.sup.th PMOS tube P15, a drain of the 13.sup.th NMOS tube N13 and a grid of the 16.sup.th PMOS tube P16 are connected to a grid of the 15.sup.th NMOS tube N15. A source of the 11.sup.th NMOS tube N11 is connected to a drain of the 12.sup.th NMOS tube N12. A source of the 12.sup.th NMOS tube N12, a source of the 14.sup.th NMOS tube N14, a source of the 15.sup.th NMOS tube N15, a source of the 19.sup.th NMOS tube N19 and a source of the 21.sup.st NMOS tube N21 are grounded respectively. A drain of the 14.sup.th PMOS tube P14 is connected to the source of the 15.sup.th PMOS tube P15. A source of the 13.sup.th NMOS tube N13 is connected to a drain of the 14.sup.th NMOS tube N14. A grid of the 14.sup.th PMOS tube P14 and a grid of the 14.sup.th NMOS tube N14, a drain of the 15.sup.th NMOS tube N15, a drain of the 16.sup.th PMOS tube P16, a grid of the 17.sup.th PMOS tube P17, a grid of the 16.sup.th NMOS tube N16 and a grid of the 19.sup.th NMOS tube N19 are connected to a grid of the 20.sup.th PMOS tube P20. A drain of the 17.sup.th PMOS tube P17, a drain of the 16.sup.th NMOS tube N16 and a grid of the 17.sup.th NMOS tube N17 are connected to a grid of the 18.sup.th PMOS tube P18. A drain of the 17.sup.th NMOS tube N17, a drain of the 18.sup.th PMOS tube P18 and a source of the 18.sup.th NMOS tube N18 are connected to a source of the 19.sup.th PMOS tube P19. A drain of the 18.sup.th NMOS tube N18 and a drain of the 19.sup.th PMOS tube P19 are connected to the drain of the 22.sup.nd PMOS tube P22, and a common connection thereof is the 1.sup.st output terminal of the said input circuit. A drain of the 19.sup.th NMOS tube N19, a drain of the 20.sup.th PMOS tube P20 and a source of the 20.sup.th NMOS tube N20 are connected to a source of the 21.sup.st PMOS tube P21. A drain of the 20.sup.th NMOS tube N20 and a drain of the 21.sup.st PMOS tube P21 are connected to the drain of the 23.sup.rd PMOS tube P23, and a common connection thereof is the 2.sup.nd output terminal of the said input circuit. A grid of the 12.sup.th PMOS tube P12, a grid of the 18.sup.th NMOS tube N18, a grid of the 20.sup.th NMOS tube N20, a grid of the 13.sup.th NMOS tube N13 and a grid of the 21.sup.th NMOS tube N21 are connected to a grid of the 24.sup.th PMOS tube P24, and a common connection thereof is a clock signal input terminal WCLK of the said input circuit, used to receive write-in signals output from the said clock circuit. A grid of the 12.sup.th NMOS tube N12, a grid of the 15.sup.th PMOS tube P15, a drain of the 24.sup.th PMOS tube P24, a drain of the 21.sup.st NMOS tube N21 and a grid of the 19.sup.th PMOS tube P19 are connected to a grid of the 21.sup.st PMOS tube P21, and a common connection thereof is the inverted clock signal input terminal WCLKB of the said input circuit, used to receive inverted signals among write-in signals output from the said clock module. A grid of the 13.sup.th PMOS tube P13 is connected to a grid of the 11.sup.th NMOS tube N11, and a common connection thereof is the signal input terminal In of the said input circuit, used to receive external data. A grid of the 22.sup.nd PMOS tube P22 is connected to a grid of the 23.sup.rd PMOS tube P23, and a common connection thereof is the charging signal input terminal PC of the said input circuit, used to receive charging signals output from the said clock circuit.

[0024] In this embodiment, the replica bit-line circuit 1100, the decoder 1200, the address latch circuit 1300, the clock circuit 1400, the memory array 1510-1-1510-n, the data selector 1520-1-1520-n and the input circuit 1540-1-1540-n are well-established products in the technical field. The SADIS, SAPRE, SASEL and SAE terminals of the sensitivity amplifier 1541 as well as OUTDIS terminal of the data latch circuit 1542 are connected to the clock circuit respectively. The terminal BL and BLB of the output circuit of the static RAM are connected to the data selector. Timing diagram for the output circuit of the static RAM of the present invention is as shown in FIG. 4. According to read data outputted from the output circuit in previous and current stages, four working states S.sub.00, S.sub.01, S.sub.10, S.sub.11 can be categorized, the working states S.sub.00 represents that logic 0 is read for the previous stage and logic 0 for the current stage; the working states S.sub.01 represents that logic 0 is read for the previous stage and logic 1 for the current stage; the working states S.sub.10 represents that logic 1 is read for the previous stage and logic 0 for the current stage; and the working states S.sub.11 represents that logic 1 is read for the previous stage and logic 1 for the current stage. As shown in FIG. 4, output terminal Q may subject to one-time charging before the evaluation stage. It is to be maintained or discharged according to the reading data at the evaluation stage. The node 1 and node 2 may charge and discharge one of nodes in each cycle. The 1.sup.st output terminal SAOUT and the 2.sup.nd output terminal SAOUTB of the sensitivity amplifier 1541 may experience one-time charging and discharging in each cycle to ensure balanced power consumption.

[0025] Energy consumption distribution diagram for the output circuit of the static RAM of the present invention is as shown in FIG. 5. The energy consumption distribution diagram for output circuit of existing static RAM is as shown in FIG. 6. According to the analysis of FIG. 6, the output circuit of the present invention has eliminated the difference between switching and short-circuit power consumption, which ensuring basically identical power consumption at each working state in each cycle. According to analysis of FIG. 6, output circuit of existing static RAM may produce obvious discrepancy to the power consumption at different working states. The output circuit of existing static RAM is requested to alter the data as stored in the data latch circuit 1542 to produce corresponding switching and short-circuit power consumption at working state S.sub.01 and S.sub.10. As a result of it, power consumption at working state S.sub.01 and S.sub.10 is obviously higher than that at working state S.sub.11 and S.sub.00. FIG. 7 is the diagram showing superposition of supply current produced by the static RAM for Differential Power Analysis Resistance when reading 100 groups of data. FIG. 8 is the diagram showing superposition of supply current produced by existing static RAM when reading 100 groups of data. According to analysis of FIGS. 7 and 8, existing static RAM has obvious current discrepancy at the evaluation stage, for example a circled area 810 shown in FIG. 8. On the contrary, the present invention has overcome defects associated with power consumption and data reading, which can ensure consistent power consumption and current in each reading cycle. As compared with prior art, the present invention has effectively improved the power equilibrium by 53%, which can effectively minimize differential power analysis attack.