READOUT CIRCUIT

Abstract

A readout circuit has a first transistor which have a first terminal, a second terminal, and a control terminal, a second transistor having a first terminal, a second terminal, and a control terminal, a first variable resistance having a first terminal connected to a first reference voltage line, and a second terminal connected to the first terminal of the first transistor, a first resistance having a first terminal connected to the first reference voltage line, and a second terminal connected to the first terminal of the second transistor, a second resistance having a first terminal connected to the second terminal of the first transistor, and a second terminal connected to a second reference voltage line, and a second variable resistance which has a first terminal connected to the second terminal of the second transistor, and a second terminal connected to the second reference voltage line.

Claims

1. A readout circuit comprising: a first transistor to comprise a first terminal, a second terminal, and a control terminal applied with a bias voltage; a second transistor to comprise a first terminal, a second terminal, and a control terminal applied with the bias voltage; a first variable resistor to comprise a first terminal connected to a first reference voltage line, and a second terminal connected to the first terminal of the first transistor; a first resistor to comprise a first terminal connected to the first reference voltage line, and a second terminal connected to the first terminal of the second transistor; a second resistor to comprise a first terminal connected to the second terminal of the first transistor, and a second terminal connected to a second reference voltage line; and a second variable resistor to comprise a first terminal connected to the second terminal of the second transistor, and a second terminal connected to the second reference voltage line.

2. The readout circuit of claim 1, wherein a resistance value of the first variable resistor in a no-signal state is equal to a resistance value of the first resistor.

3. The readout circuit of claim 1, wherein a resistance value of the second variable resistor in a no-signal state is equal to a resistance value of the second resistor.

4. The readout circuit of claim 1, wherein a change rate of a resistance value of the first variable resistor is equal to a change rate of a resistance value of the second variable resistor.

5. The readout circuit of claim 1, wherein the first resistor is a third variable resistor, and the second resistor is a fourth variable resistor.

6. The readout circuit of claim 5, wherein a change rate of a resistance value of the first variable resistor is reverse in sign to a change rate of a resistance value of the fourth variable resistor, and a change rate of a resistance value of the second variable resistor is reverse in sign to a change rate of a resistance value of the third variable resistor.

7. The readout circuit of claim 1, further comprising: a third transistor to be cascode-connected to the first transistor; and a fourth transistor to be cascode-connected to the second transistor.

8. The readout circuit of claim 1, further comprising a filter circuit to comprise a first input terminal connected to the first terminal of the second resistor, and a second input terminal connected to the first terminal of the second variable resistor.

9. The readout circuit of claim 8, further comprising an amplifier circuit to be connected in a stage following the filter circuit.

10. The readout circuit of claim 8, further comprising: a first route switch to be connected in a stage following the filter circuit; an amplifier circuit to be connected in a stage following the first route switch; and a second route switch to be connected in a stage following the amplifier circuit.

11. The readout circuit of claim 1, further comprising an amplifier circuit to comprise a first input terminal connected to the first terminal of the second resistor, and a second input terminal connected to the first terminal of the second variable resistor.

12. The readout circuit of claim 1, further comprising: a first route switch to comprise a first input terminal connected to the first terminal of the second resistor, and a second input terminal connected to the first terminal of the second variable resistor; an amplifier circuit to be connected in a stage following the first route switch; and a second route switch to be connected in a stage following the amplifier circuit.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0006] FIG. 1 is a diagram showing an example of a readout circuit according to a first embodiment.

[0007] FIG. 2 is a diagram showing an example of a conventional readout circuit.

[0008] FIG. 3 is a diagram showing an example of an amplifier circuit of FIG. 1,

[0009] FIG. 4 is a diagram showing another example of the amplifier circuit A of FIG. 1.

[0010] FIG. 5 is a diagram showing an example of a readout circuit according to a second embodiment.

[0011] FIG. 6 is a diagram showing an example of a readout circuit according to a third embodiment.

[0012] FIG. 7 is a diagram showing an example of a readout circuit according to a fourth embodiment.

[0013] FIG. 8 is a diagram showing an example of a filter circuit of FIG. 7.

[0014] FIG. 9 is a diagram showing an example of a readout circuit according to a fifth embodiment.

[0015] FIG. 10 is a diagram showing another example of the readout circuit according to the fifth embodiment.

DETAILED DESCRIPTION

[0016] According to one embodiment, a readout circuit has a first transistor to comprise a first terminal, a second terminal, and a control terminal applied with a bias voltage, a second transistor to comprise a first terminal, a second terminal, and a control terminal applied with the bias voltage, a first variable resistor to comprise a first terminal connected to a first reference voltage line, and a second terminal connected to the first terminal of the first transistor, a first resistor to comprise a first terminal connected to the first reference voltage line, and a second terminal connected to the first terminal of the second transistor, a second resistor to comprise a first terminal connected to the second terminal of the first transistor, and a second terminal connected to a second reference voltage line, and a second variable resistor to comprise a first terminal connected to the second terminal of the second transistor, and a second terminal connected to the second reference voltage line.

[0017] Hereinafter, embodiments of the present disclosure will be explained referring to the drawings.

FIRST EMBODIMENT

[0018] A readout circuit according to a first embodiment will be explained referring to FIGS. 1 to 4. The readout circuit according to the present embodiment reads a change in the resistance value of a variable resistance sensor. That is, the readout circuit outputs a detection signal depending on a change in the resistance value of the variable resistance sensor.

[0019] First, a configuration of the readout circuit will be explained. FIG. 1 is a diagram showing an example of a readout circuit according to the present embodiment. The readout circuit of FIG. 1 has a transistor M.sub.1, a transistor M.sub.2, a variable resistance VR.sub.1, a resistance R.sub.1, a resistance R.sub.2, a variable resistance VR.sub.2, an output terminal T.sub.1, an output terminal T.sub.2, and an amplifier circuit A.

[0020] The transistor M.sub.1 (first transistor) is an N-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor) (hereinafter referred to as “NMOS”) having a source terminal (first terminal), a drain terminal (second terminal), and a gate terminal (control terminal). The source terminal is connected to a second terminal of the variable resistance VR.sub.1. The drain terminal is connected to a first terminal of the resistance R.sub.2 and the output terminal T.sub.1. The gate terminal is applied with a predetermined bias voltage V.sub.b.

[0021] The transistor M.sub.2 (second transistor) is an NMOS having a source terminal, a drain terminal, and a gate terminal. The source terminal is connected to a second terminal of the resistance R.sub.1. The drain terminal is connected to a first terminal of the variable resistance VR.sub.2 and the output terminal T.sub.2. The gate terminal is applied with the predetermined bias voltage V.sub.b.

[0022] The variable resistance VR.sub.1 (first variable resistance) is a variable resistance of a variable resistance sensor. The variable resistance VR.sub.1 has a resistance value which changes depending on a change in a target of detection, such as light. The variable resistance VR.sub.1 has a first terminal and a second terminal. The first terminal is connected to a ground line (first reference voltage line). That is, the first terminal is grounded. The second terminal is connected to the source terminal of the transistor M.

[0023] The resistance R.sub.1 (first resistance) is a fixed resistance having a constant resistance value. The resistance R.sub.1 has a first terminal and a second terminal. The first terminal is connected to the ground line. That is, the first terminal is grounded. The second terminal is connected to the source terminal of the transistor M.sub.2.

[0024] The resistance R.sub.2 (second resistance) is a fixed resistance having a constant resistance value. The resistance R.sub.2 has a first terminal and a second terminal. The first terminal is connected to the drain terminal of the transistor M.sub.1 and the output terminal T.sub.1. The second terminal is connected to a power-supply line (second reference voltage line).

[0025] The variable resistance VR.sub.2 (second variable resistance) is a variable resistance of a variable resistance sensor. The variable resistance VR.sub.2 has a resistance value which changes depending on a change in a target of detection, such as light. The variable resistance VR.sub.2 has a first terminal and a second terminal. The first terminal is connected to the drain terminal of the transistor M.sub.2 and the output terminal T.sub.2. The second terminal is connected to the power-supply line.

[0026] The output terminal T.sub.1 is connected to the drain terminal of the transistor M.sub.1, the first terminal of the resistance R.sub.2, and a first input terminal T.sub.3 of the amplifier circuit A. The voltage of the output terminal T.sub.1 is inputted into the amplifier circuit A as a detection signal of the variable resistance VR.sub.1.

[0027] The output terminal T.sub.2 is connected to the drain terminal of the transistor M.sub.2, the first terminal of the variable resistance VR.sub.2, and a second input terminal T.sub.4 of the amplifier circuit A. The voltage of the output terminal T.sub.2 is inputted into the amplifier circuit A as a detection signal of the variable resistance VR.sub.2.

[0028] The amplifier circuit A is a voltage amplifier circuit which amplifies differentially inputted voltage and has a high input impedance. The amplifier circuit A has input terminals T.sub.3 and T.sub.4 and output terminals T.sub.5 and T.sub.6. The input terminal T.sub.3 is connected to the output terminal T.sub.1. The input terminal T.sub.4 is connected to the output terminal T.sub.2. The amplifier circuit A amplifies detection signals (voltage signals) differentially inputted from the input terminals T.sub.3 and T.sub.4, and differentially outputs the amplified detection signals. The configuration of the amplifier circuit A will be mentioned in detail later.

[0029] Next, the operation of the readout circuit of FIG. 1 will be explained.

[0030] The source terminal of the transistor M.sub.1 is connected to the ground line via the variable resistance VR.sub.1. Accordingly, the transistor M.sub.1 has a drain current I.sub.1 of I.sub.b1(1−ε.sub.1). I.sub.b1 represents a current value of the drain current in a no-signal state, which is i.e. bias current. ε.sub.1 represents a change rate of the resistance value of the variable resistance VR.sub.1.

[0031] Further, the input impedance of the amplifier circuit A is sufficiently larger than the resistance value of the resistance R.sub.2. Therefore, the output terminal T.sub.1 has a voltage V.sub.1 of V.sub.DD−R.sub.2I.sub.b1(1−ε.sub.1). V.sub.DD represents a power-supply voltage value. R.sub.2 represents a resistance value of the resistance R.sub.2.

[0032] Similarly, the source terminal of the transistor M.sub.2 is connected to the ground line via the resistance R.sub.1. Accordingly, the transistor M.sub.2 has a drain current 1.sub.2 which is equal to I.sub.b2. I.sub.b2 represents a bias current value.

[0033] Further, the input impedance of the amplifier circuit A is sufficiently larger than the resistance value of the variable resistance VR.sub.2. Therefore, the output terminal T.sub.2 has a voltage V.sub.2 of V.sub.DD−I.sub.b2VR.sub.2(1−ε.sub.2). VR.sub.2 represents a resistance value of the variable resistance VR.sub.2 in a no-signal state. ε.sub.2 represents a change rate of the resistance value of the variable resistance VR.sub.2.

[0034] Here, consider a case where a resistance value VR.sub.1 of the variable resistance VR.sub.1 is equal to a resistance value R.sub.1 of the resistance R.sub.1 (i.e. VR.sub.1=R.sub.1=r.sub.1) and a resistance value VR.sub.2 of the variable resistance VR.sub.2 is equal to a resistance value R.sub.2 of the resistance R.sub.2 (i.e. VR.sub.2=R.sub.2=r.sub.2).

[0035] In this case, the bias current value I.sub.b1 of the transistor M.sub.1 is equal to the bias current value I.sub.b2 of the transistor M.sub.2 (i.e. I.sub.b1=I.sub.b2=I.sub.b). Therefore, V.sub.1=V.sub.DD−r.sub.2I.sub.b(1−ε.sub.1), and V.sub.2=V.sub.DD−r.sub.2I.sub.b(1+ε.sub.2).

[0036] As will be understood from the above formulas, detection signals V.sub.1 and V.sub.2 are differentially outputted from the output terminals T.sub.1 and T.sub.2, respectively. That is, in the detection signals V.sub.1 and V.sub.2, changes in the power-supply voltage V.sub.DD, ground voltage, and bias voltage V.sub.b are canceled as a common mode phase.

[0037] Further, consider a case where characteristics of change in the resistance value of the variable resistance VR.sub.1 are the same as characteristics of change in the resistance value of the variable resistance VR.sub.2. At this time, the change rate ε.sub.1 of the resistance value of the variable resistance VR.sub.1 becomes equal to the change rate ε.sub.2 of the resistance value of the variable resistance VR.sub.2 (i.e. ε.sub.1=ε.sub.2=ε). Therefore, V.sub.1=V.sub.DD−r.sub.2I.sub.b(1−ε), and V.sub.2=V.sub.DD−r.sub.2I.sub.b(1+ε). That is, the detection signals V.sub.1 and V.sub.2 are differential signals each of which includes signal components depending on the change rate ε.

[0038] Here, the SNR of the readout circuit of FIG. 1 will be explained.

[0039] FIG. 2 is a diagram showing an example of a conventional readout circuit utilizing a Wheatstone bridge. The readout circuit of FIG. 2 can be obtained by short-circuiting the source terminal and drain terminal of the transistor M.sub.1 and short-circuiting the source terminal and drain terminal of the transistor M.sub.2 in the readout circuit of FIG. 1.

[0040] First, signal components included in the detection signals in the readout circuits of FIGS. 1 and 2 will be considered.

[0041] In the readout circuit of FIG. 2, when VR.sub.1=VR.sub.2=R.sub.1=R.sub.2=5 [kΩ], ε.sub.1=ε.sub.2=1[%], and each of the resistances (variable resistances VR.sub.1 and VR.sub.2 and resistances R.sub.1 and R.sub.2) has a voltage drop of 5 [V], V.sub.1=5.025 [V] and V.sub.2=4.975 [V]. That is, each of the detection signals V.sub.1 and V.sub.2 in the readout circuit of FIG. 2 includes signal components of 0.025 [V].

[0042] On the other hand, in the readout circuit of FIG. 1 under similar conditions, when each of the transistors M.sub.1 and M.sub.2 has a drain-source voltage of 1 [V], V.sub.1=6.05 [V] and V.sub.2=5.95 [V]. That is, each of the detection signals V.sub.1 and V.sub.2 in the readout circuit of FIG. 1 includes signal components of 0.05 [V].

[0043] The above shows that the signal components included in the detection signal in the readout circuit of FIG. 1 are twice as much as those included in the detection signal in the readout circuit of FIG. 2. This means that the conversion efficiency of the readout circuit of FIG. 1 is twice that of the readout circuit of FIG. 2.

[0044] Next, noise components included in the detection signals in the readout circuits of FIGS. 1 and 2 will be considered.

[0045] Noise components included in the detection signals in the readout circuit of FIG. 2 are determined by the output impedances of the output terminals T.sub.1 and T.sub.2, and are in proportion to (4 kTBR).sup.1/2. k represents a Boltzmann constant, T represents an absolute temperature, B represents a bandwidth, and R represents resistance components of output impedance.

[0046] Here, when defining that VR.sub.1=VR.sub.2=R.sub.1=R.sub.2=5 [kΩ], the output terminal T.sub.2 of the readout circuit of FIG. 2 has an output impedance of K{R.sub.1VR.sub.2/(R.sub.1+VR.sub.2)}.sup.1/2=1.58 K. K represents a proportional constant depending on k, T, and B. Therefore, noise components included in the detection signal V.sub.2 can be expressed as 1.58K′. K′ is a proportional constant depending on K. This can be similarly applied to the detection signal V.sub.1.

[0047] On the other hand, noise component Vn included in the detection signal of the readout circuit of FIG. 1 is decided by a sum of a component Vn.sub.1 proportional to (4 kTBR).sup.1/2 due to an output impedance at a drain terminal of the transistor M1 and a component Vn.sub.2 proportional to (4 kTB/R).sup.1/2 due to a current noise of a resistance connected to a source of the transistor M1. When assuming that VR.sub.1=VR.sub.2=R.sub.1=R.sub.2=5 [kΩ], the output terminal T.sub.2 of the readout circuit of FIG. 1 has an output impedance of KVR.sub.2.sup.1/2=2.24 K, because the drain terminal of the transistor M.sub.1 has an output impedance sufficiently larger than VR.sub.2. Furthermore, the current noise (K/R.sub.2).sup.1/2 of the resistance connected to the source passes from the source to the drain of the transistor M1 and is converted into a voltage by VR.sub.2, VR.sub.2K/(R.sub.2).sup.1/2=2.24 K. Therefore, noise components included in the detection signal V.sub.2 can be expressed as Vn=(Vn.sub.1.sup.2+Vn.sub.2.sup.2).sup.1/2=3.16 K′. This can be similarly applied to the detection signal V.sub.1.

[0048] In summary, signal components in the readout circuit of FIG. 1 are twice as much as those in the readout circuit of FIG. 2, and noise components in the readout circuit of FIG. 1 are 2 times as much as those in the readout circuit of FIG. 2. Therefore, the SNR of the readout circuit of FIG. 1 is equal to the SNR of the readout circuit of FIG. 2, but the signal level of the readout circuit of FIG. 1 is two times higher than the readout circuit of FIG. 2.

[0049] Note that noise components occurring in the transistors M.sub.1 and M.sub.2 are not treated in the above explanation, This is because the noise components occurring in the transistor M.sub.1 are made negligibly small by connecting the variable resistance VR.sub.1 between the source terminal of the transistor M.sub.1 and the ground line. The same can be applied to the noise components occurring in the transistor M.

[0050] Concretely, by connecting the variable resistance VR.sub.1, the transfer function of the noise components occurring in the transistor M.sub.1 can be expressed as 1/(1+g.sub.m1VR.sub.1). g.sub.m1 represents a transconductance of the transistor M.sub.1. Since g.sub.m1VR.sub.1 is sufficiently larger than 1, the noise components occurring in the transistor M.sub.1 are sufficiently less than the noise components included in the detection signal V.sub.1.

[0051] Similarly, by connecting the resistance R.sub.1, the transfer function of the noise components occurring in the transistor M.sub.2 can be expressed as 1/(1+g.sub.m2R.sub.1). g.sub.m2 represents a transconductance of the transistor M.sub.2. Since g.sub.m2R.sub.1 is sufficiently larger than 1, the noise components occurring in the transistor M.sub.2 are sufficiently less than the noise components included in the detection signal V.sub.2.

[0052] As explained above, the readout circuit according to the present embodiment has a higher SNR compared to the conventional readout circuit utilizing a Wheatstone bridge, That is, the present embodiment can realize a readout circuit having a high SNR.

[0053] Further, the readout circuit according to the present embodiment differentially outputs the detection signals, which makes it possible to easily connect a differential amplifier circuit in a following stage, This makes it possible to increase the output amplitude of the detection signals.

[0054] Furthermore, in the detection signals V.sub.1 and V.sub.2 of the readout circuit according to the present embodiment, changes in the power-supply voltage V.sub.DD, ground voltage, and bias voltage V.sub.b are canceled as a common phase. Therefore, the readout circuit according to the present embodiment has a high robustness with respect to the variation in the power-supply voltage V.sub.DD, ground voltage, and bias voltage V.sub.b.

[0055] Still further, the readout circuit according to the present embodiment outputs voltage signals as detection signals, which eliminates the need to connect a transimpedance amplifier in a following stage. Accordingly, the present embodiment can reduce the size of circuit area, which leads to the reduction in power consumption.

[0056] FIG. 3 is a diagram showing an example of the amplifier circuit A. The amplifier circuit A of FIG. 3 has operational amplifiers A.sub.1 and A.sub.2, input resistances R.sub.i1 and R.sub.i2, feedback resistances R.sub.f1 and R.sub.f2, the input terminals T.sub.3 and T.sub.4, and the output terminals T.sub.5 and T.sub.6.

[0057] The operational amplifier A.sub.1 has an inverting input terminal, a non-inverting input terminal, and an output terminal. The inverting input terminal is connected to a node N.sub.1. The non-inverting input terminal is connected to the input terminal T.sub.3. The output terminal is connected to the output terminal T.sub.5.

[0058] The operational amplifier A.sub.2 has an inverting input terminal, a non-inverting input terminal, and an output terminal. The inverting input terminal is connected to a node N.sub.2. The non-inverting input terminal is connected to the input terminal T.sub.4. The output terminal is connected to the output terminal T.sub.6.

[0059] The input resistance R.sub.i1 has a first terminal and a second terminal. The first terminal is connected to a first terminal of the input terminal R.sub.i2. The second terminal is connected to the node N.sub.1.

[0060] The input resistance R.sub.i2 has a first terminal and a second terminal. The first terminal is connected to the first terminal of the input terminal R.sub.i1. The second terminal is connected to the node N.sub.2.

[0061] The feedback resistance R.sub.f1 has a first terminal and a second terminal. The first terminal is connected to the node N.sub.1. The second terminal is connected to the output terminal T.sub.5.

[0062] The feedback resistance R.sub.f2 has a first terminal and a second terminal. The first terminal is connected to the node N.sub.2. The second terminal is connected to the output terminal T.sub.6.

[0063] The operational amplifier A.sub.1, input resistance R.sub.i1, and feedback resistance R.sub.f1 correspond to a non-inverting amplifier circuit. This non-inverting amplifier circuit has an amplification factor A.sub.1 of 1+R.sub.f1/R.sub.i1. Therefore, signal components of the detection signal V.sub.1 inputted from the input terminal T.sub.3 are amplified A.sub.1-fold and outputted from the output terminal T.sub.5. Note that a common phase of the detection signal V.sub.1 are amplified as the same value.

[0064] Similarly, the operational amplifier A.sub.2, input resistance R.sub.i2, and feedback resistance R.sub.f2 correspond to a non-inverting amplifier circuit. This non-inverting amplifier circuit has an amplification factor A.sub.2 of 1+R.sub.f2/R.sub.i2. Signal components of the detection signal V.sub.2 inputted from the input terminal T.sub.4 are amplified A.sub.2-fold and outputted from the output terminal T.sub.6. Note that in-phase components of the detection signal V.sub.2 are amplified as the same value.

[0065] In summary, the amplifier circuit A is differentially inputted with the detection signals V.sub.1 and V.sub.2 from the input terminals T.sub.3 and T.sub.4, amplifies the signal components by predetermined amplification factors, and differentially outputs the amplified detection signals from the output terminals T.sub.5 and T.sub.6.

[0066] With such a configuration, the amplifier circuit A can receive the detection signals from the readout circuit having a high output impedance without attenuation, and output them with a low output impedance.

[0067] FIG. 4 is a diagram showing another example of the amplifier circuit A. The amplifier circuit A of FIG. 4 has transistors M.sub.A1 and M.sub.A2, current sources I.sub.b1 to I.sub.b3, the input resistances R.sub.i1 and R.sub.i2, the feedback resistances R.sub.f1 and R.sub.f2, a fully-differential operational amplifier A.sub.3, the input terminals T.sub.3 and T.sub.4, and the output terminals T.sub.5 and T.sub.6.

[0068] The transistor M.sub.A1 is a P-channel MOSFET (hereinafter referred to as “PMOS”) having a source terminal, a drain terminal, and a gate terminal. The source terminal is connected to a node N.sub.3. The drain terminal is connected to a node N.sub.4. The gate terminal is connected to the input terminal T.sub.3. That is, the gate terminal of the transistor M.sub.A1 is applied with the detection signal V.sub.1.

[0069] The transistor M.sub.A2 is a PMOS having a source terminal, a drain terminal, and a gate terminal. The source terminal is connected to a node N.sub.5. The drain terminal is connected to a node N.sub.6. The gate terminal is connected to the input terminal T.sub.4. That is, the gate terminal of the transistor M.sub.A2 is applied with the detection signal V.sub.2.

[0070] The current source I.sub.b1 is connected between the power-supply line and a node N.sub.7 to supply a predetermined current to the transistors M.sub.A1 and M.sub.A2. The current supplied by the current source I.sub.b1 has a current value of 2I.sub.b.

[0071] The current source I.sub.b3 is connected between the node N.sub.4 and the ground line to supply a predetermined current to the transistor M.sub.A1. The current supplied by the current source I.sub.b2 has a current value of I.sub.b.

[0072] The current source I.sub.b3 is connected between the node N.sub.6 and the ground line to supply a predetermined current to the transistor M.sub.A2. The current supplied by the current source I.sub.b3 has a current value of I.sub.b.

[0073] The input resistance R.sub.i1 has a first terminal and a second terminal. The first terminal is connected to the node N.sub.3. The second terminal is connected to the node N.sub.7.

[0074] The input resistance R.sub.i2 has a first terminal and a second terminal. The first terminal is connected to the node N.sub.5. The second terminal is connected to the node N.sub.7.

[0075] The feedback resistance R.sub.f1 has a first terminal and a second terminal. The first terminal is connected to the node N.sub.3. The second terminal is connected to the output terminal T.sub.5.

[0076] The feedback resistance R.sub.f2 has a first terminal and a second terminal. The first terminal is connected to the node N.sub.5. The second terminal is connected to the output terminal T.sub.6.

[0077] The fully-differential operational amplifier A.sub.3 has an inverting input terminal, a non-inverting input terminal, a non-inverting output terminal, and an inverting output terminal. The inverting input terminal is connected to the node N.sub.6. The non-inverting input terminal is connected to the node N.sub.4. The non-inverting output terminal is connected to the output terminal T.sub.5. The inverting output terminal is connected to the output terminal T.sub.6.

[0078] The gate terminals of the transistors M.sub.A1 and M.sub.A2. of FIG. 4 correspond to the non-inverting input terminals of the operational amplifiers A.sub.1 and A.sub.2 of FIG. 3, respectively. Further, the source terminals of the transistors M.sub.A1 and M.sub.A2 of FIG. 4 correspond to the inverting input terminals of the operational amplifiers A.sub.1 and A.sub.2 of FIG. 3, respectively.

[0079] The amplifier circuit A can be realized with such a configuration. This makes it possible to further reduce the noise occurring in the amplifier circuit A, compared to the configuration of FIG. 3

[0080] Note that, in the above explanation, the amplifier circuit A is a differential output amplifier circuit, but it may be a single-ended output amplifier circuit. As such an amplifier circuit A, an instrumentation amplifier can be used. The instrumentation amplifier can be formed by connecting an operational amplifier in a stage following the circuit of FIG. 3, for example.

SECOND EMBODIMENT

[0081] A readout circuit according to a second embodiment will be explained referring to FIG. 5.

[0082] First, a configuration of the readout circuit according to the present embodiment will be explained. FIG. 5 is a diagram showing an example of a readout circuit according to the present embodiment. The readout circuit of FIG. 5 has a variable resistance VR.sub.3 instead of the resistance R.sub.1, and has a variable resistance VR.sub.4 instead of the resistance R.sub.2. The other components are similar to those of Hg. 1.

[0083] The variable resistance VR.sub.3 is a variable resistance of a variable resistance sensor. The variable resistance VR.sub.3 has a resistance value which changes depending on a change in a target of detection, such as light. The variable resistance VR.sub.3 has a first terminal and a second terminal. The first terminal is connected to the ground line. The second terminal is connected to the source terminal of the transistor M.sub.2. The variable resistance VR.sub.3 corresponds to a replacement for the resistance R.sub.1.

[0084] The variable resistance VR.sub.4 is a variable resistance of a variable resistance sensor. The variable resistance VR.sub.4 has a resistance value which changes depending on a change in a target of detection, such as light. The variable resistance VR.sub.4 has a first terminal and a second terminal. The first terminal is connected to the drain terminal of the transistor M.sub.1. The second terminal is connected to the power-supply line. The variable resistance VR.sub.4 corresponds to a replacement for the resistance R.sub.2.

[0085] Next, the operation of the readout circuit of FIG. 5 will be explained.

[0086] The source terminal of the transistor M.sub.1 is connected to the ground line via the variable resistance VR.sub.1. Accordingly, the transistor M.sub.1 has a drain current I.sub.1 of I.sub.b1(1−ε.sub.1). This is similar to the first embodiment.

[0087] Further, the input impedance of the amplifier circuit A is sufficiently larger than the resistance value of the variable resistance VR.sub.4. Therefore, the output terminal T.sub.1 has a voltage V.sub.1 of V.sub.DD−VR.sub.4(1+ε.sub.4)I.sub.b1(1−ε.sub.1). VR.sub.4 represents a resistance value of the variable resistance VR.sub.4 in a no-signal state. ε.sub.4 represents a change rate of the resistance value of the variable resistance VR.sub.4.

[0088] Similarly, the source terminal of the transistor M.sub.2 is connected to the ground line via the resistance VR.sub.3. Accordingly, the transistor M.sub.2 has a drain current I.sub.2 of I.sub.b2(1−ε.sub.3). ε.sub.3 represents a change rate of the resistance value of the variable resistance VR.sub.3.

[0089] Further, the input impedance of the amplifier circuit A is sufficiently larger than the resistance value of the variable resistance VR.sub.2. Therefore, the output terminal T.sub.2 has a voltage V.sub.2 of V.sub.DD−VR.sub.2(1+ε.sub.2)I.sub.b2(1−ε.sub.3). VR.sub.2 represents a resistance value of the variable resistance VR.sub.2 in a no-signal state. ε.sub.2 represents a change rate of the resistance value of the variable resistance VR.sub.2.

[0090] Here, consider a case where the resistance value VR.sub.1 of the variable resistance VR.sub.1 is equal to the resistance value R.sub.1 of the resistance R.sub.1 (Le. VR.sub.1=R.sub.1=r.sub.1), the resistance value VR.sub.2 of the variable resistance VR.sub.2 is equal to the resistance value R.sub.2 of the resistance R.sub.2 (i.e. VR.sub.2=R.sub.2=r.sub.2), and characteristics of change in the resistance value of the variable resistance VR.sub.1 are the same as characteristics of change in the resistance value of the variable resistance VR.sub.2 (i.e. ε.sub.1=ε.sub.2=ε).

[0091] In this case, the bias current value I.sub.b1 of the transistor M.sub.1 is equal to the bias current value I.sub.b2 of the transistor M.sub.2 (i.e. I.sub.b1=I.sub.b2=I.sub.b). Therefore, V.sub.1=V.sub.DD−r.sub.2(1+ε.sub.4)I.sub.b(1−ε), and V.sub.2=V.sub.DD−r.sub.2(1+ε)I.sub.b(1−ε.sub.3).

[0092] Further, consider a case where characteristics of change in the resistance value of the variable resistance VR.sub.3 are reverse in polarity to characteristics of change in the resistance value of the variable resistance VR.sub.2, and characteristics of change in the resistance value of the variable resistance VR.sub.4 are reverse in polarity to characteristics of change in the resistance value of the variable resistance VR.sub.1. At this time, the change rate ε.sub.3 of the resistance value of the variable resistance VR.sub.3 is reverse in sign to the change rate ε.sub.2 of the resistance value of the variable resistance VR.sub.2 (i.e. ε.sub.3=−ε.sub.2=−ε). Further, the change rate ε.sub.4 of the resistance value of the variable resistance VR.sub.4 is reverse in sign to the change rate ε.sub.1 of the resistance value of the variable resistance VR.sub.1 (i.e. ε.sub.4=−ε.sub.1=−ε). Therefore, V.sub.1=V.sub.DD−r.sub.2I.sub.b(1−ε).sub.2 and V.sub.2=V.sub.DD−r.sub.2I.sub.b(1+ε).sub.2. Further, when ε is minute, V.sub.1=V.sub.DD−r.sub.2I.sub.b(1−2ε) and V.sub.2=V.sub.DD−r.sub.2I.sub.b(1+2ε).

[0093] As explained above, in the present embodiment, the detection signals V.sub.1 and V.sub.2 are differential signals each of which includes twice the signal components of the first embodiment. Therefore, the present embodiment can further improve conversion efficiency and increase the SNR of the readout circuit compared to the first embodiment.

THIRD EMBODIMENT

[0094] A readout circuit according to a third embodiment will be explained referring to FIG. 6. FIG. 6 is a diagram showing an example of a readout circuit according to the present embodiment. In the readout circuit of FIG. 6, a transistor M.sub.3 is cascode-connected to the transistor M.sub.1, and a transistor M.sub.4 is cascode-connected to the transistor M.sub.2. Accordingly, in the present embodiment, the drain terminals of the transistors M.sub.1 and M.sub.2 are connected to source terminals of the transistors M.sub.3 and M.sub.4, respectively. The other components are similar to those of FIG. 1.

[0095] The transistor M.sub.3 (third transistor) is an NMOS having a source terminal, a drain terminal, and a gate terminal. The source terminal is connected to the drain terminal of the transistor M.sub.1. The drain terminal is connected to the first terminal of the resistance R.sub.2 and the output terminal T.sub.1. The gate terminal is applied with a predetermined bias voltage V.sub.b1. The transistor M.sub.3 is cascode-connected to the transistor M.sub.1.

[0096] The transistor M.sub.4 (fourth transistor) is an NMOS having a source terminal, a drain terminal, and a gate terminal. The source terminal is connected to the drain terminal of the transistor M.sub.2. The drain terminal is connected to the first terminal of the variable resistance VR.sub.2 and the output terminal T.sub.2. The gate terminal is applied with a predetermined bias voltage V.sub.b1. The transistor M.sub.4 is cascode-connected to the transistor M.sub.2.

[0097] Here, effect produced by the readout circuit according to the present embodiment will be explained.

[0098] Generally, a MOSFET in a saturation region has a drain current ID approximating a(V.sub.GS−V.sub.TH).sub.2(1+λV.sub.DS), where “a” represents a proportional coefficient determined by the structure of the transistor, V.sub.GS represents a gate-source voltage, V.sub.TH represents a threshold voltage, λ represents a channel modulation effect coefficient, and V.sub.DS represents a drain-source voltage. In the readout circuit of FIG. 1, drain-source voltages V.sub.DS of the transistors M.sub.1 and M.sub.2 change depending on changes in the resistance values of the variable resistances VR.sub.1 and VR.sub.2, Accordingly, as will be understood from the above expression, the drain currents I.sub.1 and I.sub.2 of the transistors M.sub.1 and M.sub.2 change depending on changes in the resistance values of the variable resistances VR.sub.1 and VR.sub.2. Consequently, harmonic signals depending on changes in the drain currents I.sub.1 and I.sub.2 may possibly occur in the output terminals T.sub.1 and T.sub.2 of the readout circuit of FIG. 1.

[0099] On the other hand, in the readout circuit according to the present embodiment, since the transistor M.sub.3 is cascade-connected to the transistor M.sub.1, variation in the drain-source voltage of the transistor M.sub.1 is restrained. Further, since the transistor M.sub.4 is cascade-connected to the transistor M.sub.2, variation in the drain-source voltage of the transistor M.sub.2 is restrained.

[0100] Therefore, the present embodiment can restrain the harmonic signals occurring due to the changes in the drain currents I.sub.1 and I.sub.2 of the transistors M.sub.1 and M.sub.2.

FOURTH EMBODIMENT

[0101] A readout circuit according to a fourth embodiment will be explained referring to FIGS. 7 and 8. FIG. 7 is a diagram showing an example of a readout circuit according to the present embodiment. The readout circuit of FIG. 7 further has a filter circuit F. In the present embodiment, the amplifier circuit A is connected in a stage following the filter circuit. The other components are similar to those of FIG. 1.

[0102] The filter circuit F is connected between the output terminals T.sub.1 and T.sub.2 and the input terminals T.sub.3 and T.sub.4. The filter circuit F passes a predetermined frequency band included in the detection signal V.sub.1 outputted from the output terminal T.sub.1, and inputs it into the amplifier circuit A through the input terminal T.sub.3. Further, the filter circuit F passes predetermined frequency components included in the detection signal V.sub.2 outputted from the output terminal T.sub.2, and inputs them into the amplifier circuit A through the input terminal T.sub.4. The filter circuit F is a lowpass filter, a highpass filter, or a band pass filter.

[0103] FIG. 8 is a diagram showing an example of the filter circuit F. The filter circuit F of FIG. 8 is a band pass filter functioning both as a lowpass filter and a highpass filter. The filter circuit F of FIG. 8 has input terminals T.sub.7 and T.sub.8, output terminals T.sub.9 and T.sub.10, capacitors C.sub.1 to C.sub.4, and resistances R.sub.3 and R.sub.4.

[0104] The input terminal T.sub.7 (first input terminal) is connected to the output terminal T.sub.1. The input terminal T.sub.8 (second input terminal) is connected to the output terminal T.sub.2. The output terminal T.sub.9 is connected to the input terminal T.sub.3. The output terminal T.sub.10 is connected to the input terminal T.sub.4.

[0105] The capacitor C.sub.1 has a first terminal and a second terminal, The first terminal is connected to a second terminal of the capacitor C.sub.2. The second terminal is connected to the input terminal T.sub.7. The capacitor C.sub.1 corresponds to a lowpass filter which passes low frequency components of the detection signal V.sub.1. The time constant of this lowpass filter is determined by the capacitance value of the capacitor C.sub.1 and the resistance value of the variable resistance VR.sub.1.

[0106] The capacitor C.sub.2 has a first terminal and a second terminal. The first terminal is connected to the input terminal T.sub.8. The second terminal is connected to the first terminal of the capacitor C.sub.1. The capacitor C.sub.2 corresponds to a lowpass filter which passes low frequency components of the detection signal V.sub.2. The time constant of this lowpass filter is determined by the capacitance value of the capacitor C.sub.2 and the resistance value of the resistance R.sub.1.

[0107] The capacitor C.sub.3 has a first terminal and a second terminal. The first terminal is connected to the input terminal T.sub.7. The second terminal is connected to the output terminal T.sub.9.

[0108] The capacitor C.sub.4 has a first terminal and a second terminal. The first terminal is connected to the input terminal T.sub.8. The second terminal is connected to the output terminal T.sub.10.

[0109] The resistance R.sub.3 has a first terminal and a second terminal. The first terminal is connected to a second terminal of the resistance R.sub.4 and applied with a predetermined voltage V.sub.C. The second terminal is connected to the output terminal T.sub.9.

[0110] The resistance R.sub.4 has a first terminal and a second terminal. The first terminal is connected to the output terminal T.sub.10. The second terminal is connected to the first terminal of the resistance R.sub.3 and applied with the predetermined voltage V.sub.C.

[0111] The capacitor C.sub.3 and resistance R.sub.3 correspond to a highpass filter which passes high frequency components of the detection signal V.sub.1. The time constant of this highpass filter is determined by the capacitance value of the capacitor C.sub.3 and the resistance value of the resistance R.sub.3.

[0112] Further, the capacitor C.sub.4 and resistance R.sub.4 correspond to a highpass filter which passes high frequency components of the detection signal V.sub.2. The time constant of this highpass filter is determined by the capacitance value of the capacitor C.sub.4 and the resistance value of the resistance R.sub.4.

[0113] A direct-current offset occurs between the detection signals V.sub.1 and V.sub.2 when there is an error between the resistance value of the variable resistance VR.sub.1 and the resistance value of the resistance R.sub.1 and when there is an error between the resistance value of the variable resistance VR.sub.2 and the resistance value of the resistance R.sub.2. This direct-current offset can be removed by connecting a highpass filter in a stage following the output terminals T.sub.1 and T.sub.2 as in the present embodiment. Consequently, passing the detection signals through the filter circuit F makes it possible to improve the SNR of the readout circuit.

[0114] Further, common-mode voltages of the filtered detection signals V.sub.1 and V.sub.2 outputted from the output terminals T.sub.9 and T.sub.10 become the voltage V.sub.C. That is, the common-mode voltages of the detection signals V.sub.1 and V.sub.2 can be arbitrarily set by the voltage V.sub.C. This makes it possible to make the detection signals V.sub.1 and V.sub.2 outputted from the output terminals T.sub.1 and T.sub.2 shift depending on the input voltage range of the amplifier circuit A.

FIFTH EMBODIMENT

[0115] A readout circuit according to a fifth embodiment will be explained referring to FIGS. 9 and 10. The readout circuit according to the present embodiment has a chopper circuit. FIG. 9 is a diagram showing an example of a readout circuit according to the present embodiment. The readout circuit of FIG. 9 further has a route switch S.sub.1, a route switch S.sub.2, and output terminals and T.sub.12. In the present embodiment, the amplifier circuit A is a differential output amplifier circuit. The other components are similar to those of FIG. 1,

[0116] The route switch S.sub.1 (first route switch) (hereinafter referred to as “switch S1”) is connected in a stage preceding the amplifier circuit A. Concretely, the switch S.sub.1 is connected between the output terminals T.sub.1 and T.sub.2 and the input terminals T.sub.3 and T.sub.4. The switch S.sub.1 switches a first route and a second route. The first route is a route for connecting the output terminal T.sub.1 and the input terminal T.sub.4 and connecting the output terminal T.sub.2 and the input terminal T.sub.3. The second route is a route for connecting the output terminal T.sub.1 and the input terminal T.sub.3 and connecting the output terminal T.sub.2 and the input terminal T.sub.4.

[0117] The route switch S.sub.2 (second route switch) (hereinafter referred to as “switch S2”) is connected in a stage following the amplifier circuit A. Concretely, the switch S.sub.2 is connected between the output terminals T.sub.5 and T.sub.6 and the output terminals T.sub.11 and T.sub.12. The switch S.sub.2 is a route switch for switching the first route and the second route. The first route is a route for connecting the output terminal T.sub.5 and the output terminal T.sub.12 and connecting the output terminal T.sub.6 and the output terminal T.sub.11. The second route is a route for connecting the output terminal T.sub.5 and the output terminal T.sub.11 and connecting the output terminal T.sub.6 and the output terminal T.sub.12.

[0118] The switches S.sub.1 and S.sub.2 correspond to a chopper circuit, and are synchronized with each other in the timing of switching the routes. Concretely, while the switch S.sub.1 forms the first route, the switch S.sub.2 also forms the first route. Further, while the switch S.sub.1 forms the second route, the switch S.sub.2 also forms the second route. The frequency at which the switches S.sub.1 and S.sub.2 switch the routes is called a switching frequency.

[0119] With such a configuration, the frequencies of the detection signals V.sub.1 and V.sub.2 can be shifted depending on the switching frequencies of the switches S.sub.1 and S.sub.2. This makes it possible to make the frequencies of the signal components of the detection signals V.sub.1 and V.sub.2 differ from the frequency of flicker noise occurring in the amplifier circuit A. That is, it is possible to prevent the flicker noise from being superimposed on the signal components of the detection signals V.sub.1 and V.sub.2. Connecting the filter circuit in a stage following the output terminals T.sub.11 and T.sub.12 and removing flicker noise from the detection signals V.sub.1 and V.sub.2 lead to the improvement of the SNR of the readout circuit.

[0120] FIG. 10 is a diagram showing another example of the readout circuit according to the present embodiment. The readout circuit of FIG. 10 has the filter circuit F explained in the fourth embodiment and the switch S.sub.1 is connected in a stage following thereto. The other components are similar to those of FIG. 9. With such a configuration, direct-current offset and flicker noise can be removed from the detection signals V.sub.1 and V.sub.2. Consequently, the SNR of the readout circuit can be further improved.

[0121] Note that the readout circuit explained as an example in each of the above embodiments is formed using MOSFETs. However, the readout circuit according to each embodiment can be formed using bipolar transistors. In this case, NMOS, PMOS, source terminal, drain terminal, and gate terminal in the above explanation should be replaced with NPN-type bipolar transistor, PNP-type bipolar transistor, emitter terminal, collector terminal, and base terminal, respectively.

[0122] While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the disclosures. Indeed, the novel methods and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the disclosures. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the disclosures.