CONVERTER CIRCUIT AND OPERATING METHOD THEREOF

Abstract

A converter circuit regulating power transfer from a power source to a load includes a first switching circuit arranged to be connected across an output of the power source, and including a plurality of switches. A second switching circuit including a plurality of switches is arranged to be connected across an input of the load. An inductive component electrically connects the first switching circuit with the second switching circuit. A controller is operably connected with the plurality of switches in both the first and second switching circuits, and receives a control signal for controlling switching of the plurality of switches in both the first and second switching circuit; generates gating signals to be provided to the plurality of switches in both the first and second switching circuit based on the control signal; and provide the gating signals to the plurality of switches in both the first and second switching circuit.

Claims

1. A converter circuit arranged to regulate power transfer from a power source to a load, comprising: a first switching circuit arranged to be connected across an output of the power source, the first switching circuit comprises a plurality of switches; a second switching circuit arranged to be connected across an input of the load, the second switching circuit comprises a plurality of switches; an inductive component electrically connecting the first switching circuit with the second switching circuit; and a controller operably connected with the plurality of switches in the first switching circuit and the plurality of switches in the second switching circuit, the controller being arranged to: receive a control signal for controlling switching of the plurality of switches in the first switching circuit and the plurality of switches in the second switching circuit; generate gating signals to be provided to the plurality of switches in the first switching circuit and the plurality of switches in the second switching circuit based on the control signal; and provide the gating signals to the plurality of switches in the first switching circuit and the plurality of switches in the second switching circuit so as to regulate power transfer from the power source to the load.

2. A converter circuit in accordance with claim 1, wherein the plurality of switches of the first switching circuit comprises a first pair of switches connected in series such that the first pair of switches is arranged to be connected across the output of the power source.

3. A converter circuit in accordance with claim 2, wherein the first switching circuit further comprises a pair of capacitors connected in series, and the pair of capacitors is connected in parallel with the first pair of switches such that the pair of capacitors is arranged to be connected across the output of the power source.

4. A converter circuit in accordance with claim 2, wherein the plurality of switches of the second switching circuit comprises a third pair of switches connected in parallel such that each of the third pair of switches is arranged to be connected across the input of the load.

5. A converter circuit in accordance with claim 4, wherein each of the third pair of switches is connected with a respective diode in series to form a switch-diode pair, thereby forming two switch-diode pairs arranged to be connected in parallel across the input of the load.

6. A converter circuit in accordance with claim 1, wherein the inductive component is a transformer with a primary winding connected with the first switching circuit and a secondary winding connected with the second switching circuit.

7. A converter circuit in accordance with claim 6, further comprising: a resonance circuit connected between the first switching circuit and the inductive component.

8. A converter circuit in accordance with claim 7, wherein the resonance circuit comprises: an inductor and capacitor pair connected in series between the first switching circuit and the inductive component.

9. A converter circuit in accordance with claim 8, wherein a resonance frequency of the inductor and capacitor pair is substantially identical to a switching frequency of one or more of the plurality of switches in the first switching circuit and the plurality of switches in the second switching circuit.

10. A converter circuit in accordance with claim 8, wherein the resonance circuit further comprises: a further inductor or a further capacitor connected in parallel across an output of the first switching circuit.

11. A converter circuit in accordance with claim 4, wherein the controller is arranged to control the first pair of switches and the third pair of switches to have substantially identical switching period.

12. A converter circuit in accordance with claim 11, wherein the controller is further arranged to perform one or more of the following: switch on and off the first pair of switches complementarily such that each of the first pair of switches has a duty cycle of about 50% with a dead time therebetween; switch on and off the third pair of switches complementarily such that each of the third pair of switches has a duty cycle of about 50% with a dead time therebetween; and control a duration from a switch-on time of one of the first pair of switches to switch-on time of one of the third pair of switches based on the control signal, wherein the duration is controlled to be between 0 and half the switching period.

13. A converter circuit in accordance with claim 12, wherein the plurality of switches of the first switching circuit further comprises a second pair of switches connected in series, the second pair of switches is connected in parallel with the first pair of switches; and the controller is further arranged to control the first pair of switches, the second pair of switches and the third pair of switches to have substantially identical switching period.

14. A converter circuit in accordance with claim 13, wherein the controller is further arranged to: switch on and off the second pair of switches complementarily such that each of the second pair of switches has a duty cycle of about 50% with a dead time therebetween; switch on and off one of the second pair of switches and one of the first pair of switches synchronously; and switch on and off another one of the second pair of switches and another one of the first pair of switches synchronously.

15. A converter circuit in accordance with claim 1, further comprising: an input capacitor arranged to be connected across the power source, between the power source and the first switching circuit; and an output capacitor arranged to be connected across the second switching circuit, between the second switching circuit and the load.

16. A converter circuit in accordance with claim 1, wherein the plurality of switches in the first switching circuit and the plurality of switches in the second switching circuit are controllable power semiconductor switches.

17. A method for operating a converter circuit arranged to regulate power transfer from a power source to a load, comprising the steps of: receiving a control signal for controlling switching of a plurality of switches in a first switching circuit and a plurality of switches in a second switching circuit of the converter circuit, wherein the first switching circuit is arranged to be connected across an output of the power source, the second switching circuit is arranged to be connected across an input of the load, and the first and second switching circuits are electrically connected through an inductive component; generating gating signals to be provided to the plurality of switches in the first switching circuit and the plurality of switches in the second switching circuit based on the control signal; and providing the gating signals to the plurality of switches in the first switching circuit and the plurality of switches in the second switching circuit so as to regulate power transfer from the power source to the load.

18. A method in accordance with claim 17, wherein the plurality of switches of the first switching circuit comprises a first pair of switches connected in series such that the first pair of switches is arranged to be connected across the output of the power source; and the plurality of switches of the second switching circuit comprises a third pair of switches connected in parallel such that each of the third pair of switches is arranged to be connected across the input of the load; and the method further comprises one or more of the following steps: controlling the first pair of switches and the third pair of switches to have substantially identical switching period; switching on and off the first pair of switches complementarily such that each of the first pair of switches has a duty cycle of about 50% with a dead time therebetween; switching on and off the third pair of switches complementarily such that each of the third pair of switches has a duty cycle of about 50% with a dead time therebetween; and controlling a duration from a switch-on time of one of the first pair of switches to switch-on time of one of the third pair of switches based on the control signal, wherein the duration is controlled to be between 0 and half the switching period.

19. A method in accordance with claim 18, wherein the plurality of switches of the first switching circuit further comprises a second pair of switches connected in series, the second pair of switches is connected in parallel with the first pair of switches; and the method further comprises one or more of the following steps: controlling the first pair of switches, the second pair of switches and the third pair of switches to have substantially identical switching period; switching on and off the second pair of switches complementarily such that each of the second pair of switches has a duty cycle of about 50% with a dead time therebetween; switching on and off one of the second pair of switches and one of the first pair of switches synchronously; and switching on and off another one of the second pair of switches and another one of the first pair of switches synchronously.

20. A controller for a converter circuit arranged to regulate power transfer from a power source to a load, wherein the controller is arranged to: receive a control signal for controlling switching of a plurality of switches in a first switching circuit and a plurality of switches in a second switching circuit of the converter circuit, wherein the first switching circuit is arranged to be connected across an output of the power source, the second switching circuit is arranged to be connected across an input of the load, and the first and second switching circuits are electrically connected through an inductive component; generate gating signals to be provided to the plurality of switches in the first switching circuit and the plurality of switches in the second switching circuit based on the control signal; and provide the gating signals to the plurality of switches in the first switching circuit and the plurality of switches in the second switching circuit so as to regulate power transfer from the power source to the load.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Embodiments of the present invention will now be described, by way of example, with reference to the accompanying drawings in which:

[0033] FIG. 1 is a simplified circuit diagram of a converter circuit in accordance with one embodiment of the present invention;

[0034] FIG. 2A is a circuit diagram of the first switching circuit in the converter circuit of FIG. 1 in accordance with one embodiment of the present invention;

[0035] FIG. 2B is a circuit diagram of the first switching circuit in the converter circuit of FIG. 1 in accordance with another embodiment of the present invention;

[0036] FIG. 2C is a circuit diagram of the first switching circuit in the converter circuit of FIG. 1 in accordance with yet another embodiment of the present invention;

[0037] FIG. 3A is a circuit diagram of a resonance circuit in the converter circuit of FIG. 1 in accordance with one embodiment of the present invention;

[0038] FIG. 3B is a circuit diagram of a resonance circuit in the converter circuit of FIG. 1 in accordance with another embodiment of the present invention;

[0039] FIG. 3C is a circuit diagram of a resonance circuit in the converter circuit of FIG. 1 in accordance with yet another embodiment of the present invention; and

[0040] FIG. 4 is a graph showing waveforms of the operation of the switches in the converter circuit of FIG. 1, as well as the respective voltage and current waveforms obtained in the converter circuit of FIG. 1 using the first switching circuit of FIGS. 2A to 2C.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

[0041] Referring to FIGS. 1-2C, there is provided a converter circuit 100 arranged to regulate power transfer from a power source to a load, comprising: a first switching circuit 102 arranged to be connected across an output of the power source V.sub.1, the first switching circuit 102 comprises a plurality of switches; a second switching circuit 104 arranged to be connected across an input of the load R.sub.L, the second switching circuit 104 comprises a plurality of switches; an inductive component TR connected between the first switching circuit 102 and the second switching circuit 104; and a controller 106 operably connected with the plurality of switches in the first switching circuit 102 and the plurality of switches in the second switching circuit 104, the controller 106 being arranged to: receive a control signal for controlling switching of the plurality of switches in the first switching circuit 102 and the plurality of switches in the second switching circuit 104; generate gating signals to be provided to the plurality of switches in the first switching circuit 102 and the plurality of switches in the second switching circuit 104 based on the control signal; and provide the gating signals to the plurality of switches in the first switching circuit 102 and the plurality of switches in the second switching circuit 104 so as to regulate power transfer from the power source V.sub.1 to the load R.sub.L. Preferably, the converter circuit 100 also includes a resonance circuit 108 connected between the first switching circuit 102 and the inductive component TR.

[0042] FIG. 1 shows a simplified circuit diagram of a converter circuit 100 in accordance with one embodiment of the present invention. In the present invention, the power source V.sub.1 is preferably a voltage source and in particular a DC voltage source. The converter circuit 100 is preferably a DC/DC converter circuit arranged to regulate power transfer from a DC power source V.sub.1 to a load R.sub.L. In some other embodiments, however, the power source may be other AC or DC current/voltage sources, and the converter circuit 100 may be operable to regulate power transfer from these power sources to the load, or to regulate power transfer between two of these power sources.

[0043] As shown in FIG. 1, the converter circuit 100 includes a first switching circuit 102 arranged to be connected across an output of the voltage source V.sub.1. The first switching circuit 102 is preferably connected across the voltage source V.sub.1 at nodes T1P and T1N. Optionally, an input capacitor C.sub.in that acts as a high frequency filter is also connected across the voltage source V.sub.1 at nodes T1P and T1N, between the voltage source V.sub.1 and the first switching circuit 102. Different embodiments of the first switching circuit 102 in the converter circuit 100 of present invention are shown in FIGS. 2A to 2C, and are described below.

[0044] FIG. 2A shows a first switching circuit 102A in accordance with one embodiment of the present invention. The first switching circuit 102A in FIG. 2A is a bridge circuit with a first pair of switches S.sub.1u,S.sub.1d connected in series between nodes T1P and T1N, and a second pair of switches S.sub.2u, S.sub.2d connected in series between nodes T1P and T1N. The first pair of switches S.sub.1u, S.sub.1d and the second pair of switches S.sub.2u, S.sub.2d is connected in parallel. In the present embodiment, the switches S.sub.1u, S.sub.1d, S.sub.2u, S.sub.2d are MOSFET switches each with a respective body/bypass diode d.sub.1u, d.sub.1d, d.sub.2, d.sub.2d connected in an antiparallel manner. Node A defined between the first pair of switches S.sub.1u, S.sub.1d, and node B defined between the second pair of switches S.sub.2u, S.sub.2d are preferably connected with the resonance circuit 108 or the inductive component TR (in case where the circuit 100 lacks a resonance circuit 108). In the present embodiment, all of the switches S.sub.1u, S.sub.1d, S.sub.2u, S.sub.2d are operably connected with the controller 106 so as to be controlled by the controller 106.

[0045] FIG. 2B shows a first switching circuit 102B in accordance with another embodiment of the present invention. The first switching circuit 102B in this embodiment is a bridge circuit with the first pair of switches S.sub.1u, S.sub.1d connected in series between nodes T1P and T1N, and a pair of capacitors C.sub.2u, C.sub.2d connected in series between nodes T1P and T1N. The first pair of switches S.sub.1u, S.sub.1d and the pair of capacitors C.sub.2u, C.sub.2d is connected in parallel. The switches S.sub.1u, S.sub.1d, are preferably MOSFET switches each with a respective body/bypass diode d.sub.1u, d.sub.1d connected in an antiparallel manner. Node A defined between the first pair of switches S.sub.1u, S.sub.1d, and node B defined between the pair of capacitors C.sub.2u, C.sub.2d are preferably connected with the resonance circuit 108 or the inductive component TR (in case where the circuit 100 lacks a resonance circuit 108). In the present embodiment, all of the switches S.sub.1u, S.sub.1d are operably connected with the controller 106 so as to be controlled by the controller 106. Preferably, the capacitances of the capacitors C.sub.2u, C.sub.2d are large enough to maintain the voltages across them almost constant.

[0046] FIG. 2C shows yet another embodiment of the first switching circuit 102C. In this embodiment, the first switching circuit 102C is a half-bridge circuit with only the first pair of switches S.sub.1u, S.sub.1d connected in series between nodes T1P and T1N. The switches S.sub.1u, S.sub.1d are preferably MOSFET switches each with a respective body/bypass diode d.sub.1u, d.sub.1d connected in an antiparallel manner. Node A defined between the first pair of switches S.sub.1u, S.sub.1d, and node B defined to be the same as node T1N are preferably connected with the resonance circuit 108 or the inductive component TR (in case where the circuit 100 lacks a resonance circuit 108). In the present embodiment, all of the switches S.sub.1u, S.sub.1d are operably connected with the controller 106 so as to be controlled by the controller 106.

[0047] The switches S.sub.1u, S.sub.1d, S.sub.2u, S.sub.2d used in the embodiments of the switching circuit 102A-102C illustrated in FIGS. 2A-2C are all MOSFET switches. However, in other embodiments, the switches S.sub.1u, S.sub.1d, S.sub.2u, S.sub.2d may be any power semiconductor switches, transistors, or other switching components that can be controlled by one or more controllers. Examples of these transistors include bipolar junction transistors (BJT), junction gate field-effect transistors GFET), metal-oxide-semiconductor field-effect transistors (MOSFET), and hetero-structure field-effect transistors (HFET)/high-electron-mobility transistors (HEMT) that can be of any type (e.g., PNP, NPN) or channel (e.g., p-channel, n-channel), and can operate at different operation modes (e.g., depletion mode, enhancement mode). The switches in the first switching circuit are preferably of the same type. On the other hand, all the above embodiments of the first switching circuits 102A-102C include the first pair of switches S.sub.1u, S.sub.1d, that are essential in some embodiments of the present invention. The second pair of switches S.sub.2u, S.sub.2d is some embodiments, is optional, and may be omitted. In one embodiment, the first switching circuit 102 may include a second pair of switches S.sub.2u, S.sub.2d that are idle. In some other embodiments, the first switching circuit 102 may include other active or passive circuit components (e.g., diodes, capacitors, inductors, etc.) in addition to the first pair of switches S.sub.1u, S.sub.1d.

[0048] Referring back to FIG. 1, the converter circuit 100 also in some embodiments may include a resonance circuit 108 connected between the first switching circuit 102 (across nodes A and B) and the inductive component TR (across nodes TRP1 and TRP2). Different embodiments of the resonance circuit 108 are shown in FIGS. 3A to 3C, and can be used tougher with any embodiments of the first switching circuit 102, such that those illustrated in FIGS. 2A to 2C. In the embodiment of FIG. 3A, the resonance circuit 108A includes an inductor L.sub.r and capacitor C.sub.r pair connected in series between the first switching circuit 102 and the inductive component TR, between nodes A and TRP1. In the embodiment of FIG. 3B, the resonance circuit 108B includes the inductor L.sub.r and capacitor C.sub.r pair, and a further inductor L.sub.p connected in parallel across an output of the first switching circuit, e.g., across nodes TRP1 and TRP2, downstream of the capacitor C.sub.r. In the embodiment of FIG. 3C, the resonance circuit 108C includes the inductor L.sub.r and capacitor C.sub.r pair, and a further capacitor C.sub.p connected in parallel across an output of the first switching circuit 102, e.g., across nodes TRP1 and TRP2, downstream of the capacitor C.sub.r. In the present invention, the resonance frequency f.sub.r of the inductor L.sub.r and capacitor C.sub.r pair is preferably substantially identical to a switching frequency (i.e., reciprocal of the switching period T.sub.p) of the plurality of switches S.sub.1u, S.sub.1d, S.sub.2u, S.sub.2d, S.sub.3d, S.sub.4d in the first switching circuit 102 and the second switching circuit 104. In one example, the resonance frequency f.sub.r is larger than but close to the switching frequency. The use of the further inductor L.sub.p or the further capacitor C.sub.p in some embodiments can improve the switching transient of the active switches S.sub.1u, S.sub.1d, S.sub.2u, S.sub.2d, S.sub.3d, S.sub.4d.The inductance of the further inductor L.sub.p and the capacitance of the further capacitor C.sub.p would not substantially affect the power being transferred from the voltage source V.sub.1 to the load R.sub.L.

[0049] In a preferred embodiment of the present invention, the inductive component TR is a transformer with a primary winding and a secondary winding. The transformer is arranged to provide galvanic isolation between the first switching circuit 102 and second switching circuit 104. The primary winding is preferably connected with the resonance circuit 108 through nodes TRP1 and TRP2, or with the first switching circuit 102 (in embodiments where the circuit 100 lacks a resonance circuit 108) through nodes A and B. The secondary winding is preferably connected with the second switching circuit 104 through nodes M and N. In the present embodiment, the transformer ratio of the transformer can be freely chosen to meet the requirements of different input-output voltage ratios. In another embodiment, the inductive component may be an inductor connected in series between the resonance circuit 108 (or the first switching circuit 102 in embodiments where the circuit 100 lacks a resonance circuit 108) and the second switching circuit 104.

[0050] The converter circuit 100 in the present invention further includes a second switching circuit 104 arranged to be connected across an input of the load R.sub.L, between the inductive component TR and the load R.sub.L. The second switching circuit 104 is preferably connected across the load R.sub.L at nodes T2P and T2N. The second switching circuit 104 preferably includes a third pair of switches S.sub.3d, S.sub.4d connected in parallel with each other.

[0051] In one embodiment, each of the third pair of switches S.sub.3d, S.sub.4d is connected in series with a respective diode d.sub.3, d.sub.4 to form a switch-diode pair. Each of the switch-diode pair is arranged to be connected across the input of the load R.sub.L, at nodes T2P and T2N. The switches S.sub.3d, S.sub.4d are preferably MOSFET switches each with a respective body/bypass diode d.sub.3d, d.sub.4d connected in an antiparallel manner. In other examples, the switches S.sub.3d, S.sub.4d may be any power semiconductor switches, transistors, or other switching components that can be controlled by one or more controllers 106. Examples of these transistors include bipolar junction transistors (BJT), junction gate field-effect transistors (JFET), metal-oxide-semiconductor field-effect transistors (MOSFET), and hetero-structure field-effect transistors (HFET)/high-electron-mobility transistors (HEMT) that can be of any type (e.g., PNP, NPN) or channel (e.g., p-channel, n-channel), and can operate at different operation modes (e.g., depletion mode, enhancement mode).. Node M defined between the switch S.sub.3d and diode d.sub.3 and node N defined between the switch S.sub.4d and diode d.sub.4 are preferably connected with each other through the inductive component TR, e.g., the secondary windings of the transformer. In the present embodiment, all of the switches S.sub.3d, S.sub.4d are operably connected with the controller 106 so as to be controlled by the controller 106. Optionally, an output capacitor C.sub.out that acts as a high frequency filter is connected across the load R.sub.L at nodes T2P and T2N, between the second switching circuit 104 and the load R.sub.L.

[0052] The converter circuit 100 in the present invention also includes a controller 106 operably connected with the switches S.sub.1u, S.sub.1d, S.sub.2u, S.sub.2d of the first switching circuit 102 and the switches S.sub.3d, S.sub.4d of the second switching circuit 104 to control their operation. In the present invention, the controller 106 may include one or more processors (e.g., MCU, CPU, or other integrated circuit chip with processor core, volatile and/or non-volatile memory, and programmable input/output peripherals). Preferably, the controller 106 also has input or detection means arranged to receive a control signal for controlling operation of the switches S.sub.1u, S.sub.1d, S.sub.2u, S.sub.2d, S.sub.3d, S.sub.4d. In other embodiments, the controller may be an information handling system (with one or more processors, memory modules, input/output devices, disk drives, communication modules, etc.), integrated or distributed, with one or more hardware and/or software components.

[0053] In a preferred embodiment of the present invention, the controller 106 is arranged to receive a control signal for controlling switching of the switches S.sub.1u, S.sub.1d (and S.sub.2u, S.sub.2d if present) of the first switching circuit 102 and the switches S.sub.3d, S.sub.4d of the second switching circuit 104. The controller 106 is also arranged to generate and provide gating signals to the plurality of the switches S.sub.1u, S.sub.1d (and S.sub.2u, S.sub.2d if present) of the first switching circuit 102 and the switches S.sub.3d, S.sub.4d of the second switching circuit 104 based on the control signal so as to regulate power transfer from the voltage source V.sub.1 to the load R.sub.L.

[0054] Preferably, the controller 106 is arranged to control the first pair of switches S.sub.1u, S.sub.1d and the third pair of switches S.sub.3d, S.sub.4d to have substantially identical switching period T. In the embodiment where the first switching circuit 102 includes and uses a second pair of switches S.sub.2u, S.sub.2d, the controller 106 may control the first pair of switches S.sub.1u, S.sub.1d, the second pair of switches S.sub.2u, S.sub.2d, and the third pair of switches S.sub.3d, S.sub.4d to have substantially identical switching period T. The controller 106 preferably controls all the switches S.sub.1u, S.sub.1d, S.sub.2u, S.sub.2d, S.sub.3d, S.sub.4d in the first switching circuit 102 and the second switching circuit 104 to have the same switching period T.sub.p, even though the switches may or may not be switched-on at the same time. In the present embodiment, a switching period T.sub.p may be defined from a switch-on time of switch S.sub.1u to the next switch-on time of the same switch S.sub.1u.

[0055] In the present embodiment, the controller 106 is arranged to switch on and off the first pair of switches S.sub.1u, S.sub.1d complementarily such that each of the first pair of switches has a duty cycle of about 50% with a dead time therebetween. In other words, the controller 106 is arranged to switch-on one of the first pair of switches and switch-off another one of the first pair of switches at substantially the same time. The controller 106 may further switch on and off the third pair of switches S.sub.3d, S.sub.4d complementarily such that each of the third pair of switches has a duty cycle of about 50% with a dead time therebetween. In other words, the controller 106 is arranged to switch-on one of the third pair of switches and switch-off another one of the third pair of switches at substantially the same time. In a preferred embodiment, the controller 106 is further arranged to control a duration T.sub.d from a switch-on time of one of the first pair of switches S.sub.1u to switch-on time of one of the third pair of switches S.sub.3d based on the control signal. The duration T.sub.d is preferably positive and is controlled to be between 0 and half the switching period T. Preferably, the duration T.sub.d is the only variable parameter in the circuit 100 for controlling the amount of power flowing from the voltage source V.sub.1 to the load R.sub.L.

[0056] In embodiments where the converter circuit 100 includes and uses a second pair of switches S.sub.2u, S.sub.2d, the controller 106 may switch on and off the second pair of switches complementarily such that each of the second pair of switches has a duty cycle of about 50% with a dead time therebetween. In other words, the controller 106 is arranged to switch-on one of the second pair of switches and switch-off another one of the second pair of switch at substantially the same time. Preferably, the controller 106 also switches on and off one of the second pair of switches S.sub.2d and one of the first pair of switches S.sub.1u synchronously, and switches on and off another one of the second pair of switches S.sub.2u and another one of the first pair of switches S.sub.1d synchronously. That is, the controller 106 switches-on one of the second pair of switches and switches-on one of the first pair of switch at substantially the same time; and switches-off the one of the second pair of switches and switches-off the one of the first pair of switch at substantially the same time.

[0057] FIG. 4 shows the waveforms of the operation of the switches S.sub.1u, S.sub.1d, S.sub.2u, S.sub.2d, S.sub.3d, S.sub.4d in the converter circuit of FIG. 1, as well as the respective steady state voltage and current waveforms obtained from the converter circuit 100 of FIG. 1 incorporating the first switching circuit of FIGS. 2A to 2C. As shown in FIG. 4, all switches S.sub.1u, S.sub.1d, (and S.sub.2u, S.sub.2d if present), S.sub.3d, S.sub.4d have the same switching period T.sub.p, defined as a duration between successive switch-on times of the first switch S1u. Also, each of the first pair of switches S.sub.1u, S.sub.1d, the second pair of switches S.sub.2u, S.sub.2d (if present), and the third pair of switches S.sub.3d, S.sub.4d are switched on and off complementarily. In embodiments where the first switching circuit 102 includes the second pair of switches S.sub.1u, S.sub.2d, one of the first pair of switches S.sub.1u and one of the second pair of switches S.sub.2d are switched on and off synchronously; and the other of the first pair of switches S.sub.1d and the other of the second pair of switches S.sub.2u are switched on and off synchronously. As shown in FIG. 4, the duration T.sub.d between a switch-on time of the first switch s.sub.1u and a switch-on time of the third switch s.sub.3d is positive, between 0 and T.sub.p/2.

[0058] FIG. 4 shows three voltage waveforms obtained across nodes A and B for converter circuits 100 with different embodiments of the first switching circuits 102A-102C. For the converter circuit 100 with the first switching circuit 102A of FIG. 2A, the voltage waveform is an AC square wave having a peak-to-peak amplitude 2V.sub.1 (varies between +V.sub.1 and −V.sub.1). For the converter circuit 100 with the first switching circuit 102B of FIG. 2B, the voltage waveform is an AC square wave having a peak-to-peak amplitude V.sub.1 (varies between +V.sub.1/2 and −V.sub.1/2). For the converter circuit 100 with the first switching circuit 102C of FIG. 2C, the voltage waveform is a DC square wave having a peak-to-peak amplitude V.sub.1 (varies between +V.sub.1 and 0). The waveform of the current i.sub.p in each of these embodiments is substantially sinusoidal.

[0059] Embodiments of the converter circuit and its operation method are particularly advantageous and adapted for applications with high voltage and low current, e.g., applications of switching-mode power supply, battery charger in a power range of several hundred watts to a few kilo-watts. Equipped with a high-frequency isolated transformer TR, embodiments of the converter circuit in the present invention can provide galvanic isolation between the input (e.g., power source) and the output (e.g. load), which increases safety and voltage-matching ability. Embodiments of the resonant circuits in the present invention can improve the switching transient. Also, in the present invention, all switches S.sub.1u, S.sub.1d, S.sub.2u, S.sub.2d, S.sub.3d, S.sub.4d can be turned on with zero voltage and can be turned off softly. All independent diodes d.sub.3, d.sub.4 can also be turned on and turned off with zero current. In embodiments of the present invention, the switching loss resulting from high-frequency switching behaviour in the converter circuit 100 is almost zero. All switches and diodes can work with nearly zero switching loss for a wide range of load. In addition, the power control methods in embodiments of the present invention are simple and can be readily adjusted. Other advantages of the present invention in terms of structure, function, cost, manufacture cost and ease, operation effectiveness, operation efficiency, etc., can be inferred by the person skilled in the art upon reading the description of the invention.

[0060] Although not required, the embodiments described with reference to the Figures can be implemented as an application programming interface (API) or as a series of libraries for use by a developer or can be included within another software application, such as a terminal or personal computer operating system or a portable computing device operating system. Generally, as program modules include routines, programs, objects, components and data files assisting in the performance of particular functions, the skilled person will understand that the functionality of the software application may be distributed across a number of routines, objects or components to achieve the same functionality desired herein.

[0061] It will also be appreciated that where the methods and systems of the present invention are either wholly implemented by computing system or partly implemented by computing systems then any appropriate computing system architecture may be utilised. This will include stand-alone computers, network computers and dedicated hardware devices. Where the terms “computing system” and “computing device” are used, these terms are intended to cover any appropriate arrangement of computer hardware capable of implementing the function described.

[0062] It will be appreciated by persons skilled in the art that numerous variations and/or modifications may be made to the invention as shown in the specific embodiments without departing from the spirit or scope of the invention as broadly described. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive.

[0063] Any reference to prior art contained herein is not to be taken as an admission that the information is common general knowledge, unless otherwise indicated.