Differential input circuit and driving circuit

Abstract

A differential input circuit and a driving circuit including the same are provided. The differential input circuit transforms an analog voltage signal corresponding to a sensing line on an OLED panel to a pair of differential input signals being output to a gain amplifier. The differential input circuit includes a sampling circuit and a scaling circuit. The sampling circuit receives the analog voltage signal and a reference voltage through a first scaling path and a second scaling path, respectively. The scaling circuit includes a first scaling path and a second scaling path. The first scaling path and the second scaling path collectively generate the pair of differential input signals, based on a first shift voltage, a first scaled voltage, a second shift voltage, and a second scaled voltage. The first shift voltage is less than the second shift voltage.

Claims

1. A differential input circuit, for transforming an analog voltage signal corresponding to a sensing line on an OLED panel to a pair of differential input signals being output to a gain amplifier, wherein the differential input circuit comprises: a sampling circuit, configured to receive the analog voltage signal and a reference voltage, comprising: a first sampling path, configured to selectively sample the analog voltage signal to generate a first sampling voltage between a first sensing terminal and a first reference terminal according to the analog voltage signal and the reference voltage; and a second sampling path, configured to selectively sample the analog voltage signal to generate a second sampling voltage between a second reference terminal and a second sensing terminal according to the reference voltage and the analog voltage signal; and a scaling circuit, comprising: a first scaling path, electrically connected to the first sensing terminal and the first reference terminal, configured to receive the first sampling voltage and a first shift voltage, down scale the first sampling voltage to a first scaled voltage, and generate one of the pair of differential input signals according to the first shift voltage and the first scaled voltage; and a second scaling path, electrically connected to the second sensing terminal and the second reference terminal, configured to receive the second sampling voltage and a second shift voltage, down scale the second sampling voltage to a second scaled voltage, and generate the other one of the pair of differential input signals according to the second shift voltage and the second scaled voltage, wherein the first and the second shift voltages are direct current voltages and the first shift voltage is less than the second shift voltage.

2. The differential input circuit according to claim 1, wherein the first scaling path receives the first shift voltage at a first shift terminal, and the second scaling path receives the second shift voltage at a second shift terminal, wherein a range of the pair of differential input signals is less than or equivalent to difference between the first and the second shift voltages.

3. The differential input circuit according to claim 1, wherein magnitudes of the first sampling voltage and the second sampling voltage are equivalent and polarities of the first sampling voltage and the second sampling voltage are opposite.

4. The differential input circuit according to claim 1, wherein the first sampling path comprises: a first sampling switch, electrically connected to a first receiving terminal and the first sensing terminal, configured to transmit the analog voltage signal to the first sensing terminal according to a sample enable signal; a first reference switch, electrically connected to a second receiving terminal and the first reference terminal, configured to transmit the reference voltage to the first reference terminal according to the sample enable signal; and a first sampling capacitor, electrically connected to the first sensing terminal and the first reference terminal, configured to be charged and generate the first sampling voltage when the first sampling switch and the first reference switch are switched on.

5. The differential input circuit according to claim 4, wherein the first scaling path comprises: a first scaling switch, electrically connected to the first sensing terminal and a first scaling terminal, configured to conduct the first sensing terminal and the first scaling terminal according to a scaling enable signal; a first shift switch, electrically connected to the first reference terminal and a first shift terminal, configured to conduct the first reference terminal and the first shift terminal according to the scaling enable signal; and a first charge sharing capacitor, electrically connected to the first scaling terminal and the first shift terminal, configured to receive the first shift voltage through the first shift terminal, share charges stored in the first sampling capacitor when the first scaling switch and the first shift switch are turned on and accordingly down scale the first sampling voltage to the first scaled voltage, wherein the one of the pair of differential input signals is generated at the first scaling terminal.

6. The differential input circuit according to claim 5, wherein a first scaling ratio between the first scaled voltage and the first sampling voltage is determined based on capacitances of the first sampling capacitor and the first charge sharing capacitor.

7. The differential input circuit according to claim 4, wherein the second sampling path comprises: a second sampling switch, electrically connected to the first receiving terminal and the second sensing terminal, configured to transmit the analog voltage signal to the second sensing terminal according to the sample enable signal; a second reference switch, electrically connected to the second receiving terminal and the second reference terminal, configured to transmit the reference voltage to the second reference terminal according to the sample enable signal; and a second sampling capacitor, electrically connected to the second reference terminal and the second sensing terminal, configured to be charged and generate the second sampling voltage when the second sampling switch and the second reference switch are switched on.

8. The differential input circuit according to claim 7, wherein the second scaling path comprises: a second scaling switch, electrically connected to the second reference terminal and a second scaling terminal, configured to conduct the second reference terminal and the second scaling terminal according to a scaling enable signal; a second shift switch, electrically connected to the second sensing terminal and a second shift terminal, configured to conduct the second sensing terminal and the second shift terminal according to the scaling enable signal; and a second charge sharing capacitor, electrically connected to the second scaling terminal and the second shift terminal, configured to receive the second shift voltage through the second shift terminal, share charges stored in the second sampling capacitor when the second scaling switch and the second shift switch are turned on and accordingly down scale the second sampling voltage to the second scaled voltage, wherein the other one of the pair of differential input signals is generated at the second scaling terminal.

9. The differential input circuit according to claim 8, wherein a second scaling ratio between the second scaled voltage and the second sampling voltage is determined based on capacitances of the second sampling capacitor and the second charge sharing capacitor.

10. A driving circuit of a display device, comprising: a differential input circuit, for transforming an analog voltage signal corresponding to a sensing line on an OLED panel to a pair of differential input signals, wherein the differential input circuit comprises: a sampling circuit, configured to receive the analog voltage signal and a reference voltage, comprising: a first sampling path, configured to selectively sample the analog voltage signal to generate a first sampling voltage between a first sensing terminal and a first reference terminal according to the analog voltage signal and the reference voltage; and a second sampling path, configured to selectively sample the analog voltage signal to generate a second sampling voltage between a second reference terminal and a second sensing terminal according to the reference voltage and the analog voltage signal; and a scaling circuit, comprising: a first scaling path, electrically connected to the first sensing terminal and the first reference terminal, configured to receive the first sampling voltage and a first shift voltage, down scale the first sampling voltage to a first scaled voltage, and generate one of the pair of differential input signals according to the first shift voltage and the first scaled voltage; and a second scaling path, electrically connected to the second sensing terminal and the second reference terminal, configured to receive the second sampling voltage and a second shift voltage, down scale the second sampling voltage to a second scaled voltage, and generate the other one of the pair of differential input signals according to the second shift voltage and the second scaled voltage, wherein the first and the second shift voltages are direct current voltages and the first shift voltage is less than the second shift voltage; and a gain amplifier, electrically connected to the differential input circuit, comprising a first input terminal, a second input terminal, a first output terminal and a second output terminal, configured to receive the pair of differential input signals through the first and the second input terminals and generate a pair of differential output signals at the first and the second output terminals.

11. The driving circuit according to claim 10, wherein the first scaling path receives the first shift voltage at a first shift terminal, and the second scaling path receives the second shift voltage at a second shift terminal, wherein a range of the pair of differential input signals is less than or equivalent to difference between the first and the second shift voltages.

12. The driving circuit according to claim 10, wherein magnitudes of the first sampling voltage and the second sampling voltage are equivalent, and polarities of the first sampling voltage and the second sampling voltage are opposite.

13. The driving circuit according to claim 10, wherein the first sampling path comprises: a first sampling switch, electrically connected to a first receiving terminal and the first sensing terminal, configured to transmit the analog voltage signal to the first sensing terminal according to a sample enable signal; a first reference switch, electrically connected to a second receiving terminal and the first reference terminal, configured to transmit the reference voltage to the first reference terminal according to the sample enable signal; and a first sampling capacitor, electrically connected to the first sensing terminal and the first reference terminal, configured to be charged and generate the first sampling voltage when the first sampling switch and the first reference switch are switched on.

14. The driving circuit according to claim 13, wherein the first scaling path comprises: a first scaling switch, electrically connected to the first sensing terminal and a first scaling terminal, configured to conduct the first sensing terminal and the first scaling terminal according to a scaling enable signal; a first shift switch, electrically connected to the first reference terminal and a first shift terminal, configured to conduct the first reference terminal and the first shift terminal according to the scaling enable signal; and a first charge sharing capacitor, electrically connected to the first scaling terminal and the first shift terminal, configured to receive the first shift voltage through the first shift terminal, share charges stored in the first sampling capacitor when the first scaling switch and the first shift switch are turned on and accordingly down scale the first sampling voltage to the first scaled voltage, wherein the one of the pair of differential input signals is generated at the first scaling terminal.

15. The driving circuit according to claim 13, wherein the second sampling path comprises: a second sampling switch, electrically connected to the first receiving terminal and the second sensing terminal, configured to transmit the analog voltage signal to the second sensing terminal according to the sample enable signal; a second reference switch, electrically connected to the second receiving terminal and the second reference terminal, configured to transmit the reference voltage to the second reference terminal according to the sample enable signal; and a second sampling capacitor, electrically connected to the second reference terminal and the second sensing terminal, configured to be charged and generate the second sampling voltage when the second sampling switch and the second reference switch are switched on.

16. The driving circuit according to claim 15, wherein the second scaling path comprises: a second scaling switch, electrically connected to the second reference terminal and a second scaling terminal, configured to conduct the second reference terminal and the second scaling terminal according to a scaling enable signal; a second shift switch, electrically connected to the second sensing terminal and a second shift terminal, configured to conduct the second sensing terminal and the second shift terminal according to the scaling enable signal; and a second charge sharing capacitor, electrically connected to the second scaling terminal and the second shift terminal, configured to receive the second shift voltage through the second shift terminal, share charges stored in the second sampling capacitor when the second scaling switch and the second shift switch are turned on and accordingly down scale the second sampling voltage to the second scaled voltage, wherein the other one of the pair of differential input signals is generated at the second scaling terminal.

17. The driving circuit according to claim 10, further comprising: a multiplexer selection circuit, electrically connected to the differential input circuit and the gain amplifier, configured to conduct the pair of differential input signals to the first and the second input terminals of the gain amplifier according to a channel selection signal.

18. The driving circuit according to claim 17, wherein the multiplexer selection circuit further comprises: a first selection switch, electrically connected to the first scaling terminal and the gain amplifier, configured to conduct the one of the pair of differential input signals to the first input terminal of the gain amplifier; and a second selection switch, electrically connected to the second scaling terminal and the gain amplifier, configured to conduct the other one of the pair of differential input signals to the second input terminal of the gain amplifier.

19. The driving circuit according to claim 10, wherein the gain amplifier comprises: an input stage circuit, electrically connected to the first and the second selection switches, configured to receive a common voltage or the pair of differential input signals; a loading stage circuit, electrically connected to the input stage circuit, configured to generate the pair of differential output signals according to the common voltage or the pair of differential input signals.

20. The driving circuit according to claim 19, wherein the input stage circuit receives the common voltage when the channel selection signal represents the gain amplifier operates in a common mode; and the input stage circuit receives the pair of differential input signals when the channel selection signal represents the gain amplifier operates in an amplification mode.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 (prior art) is a schematic diagram illustrating the operation of an OLED pixel circuit.

(2) FIG. 2 is a schematic diagram illustrating components related to sensing the OLED and/or TFT degradation information of the pixel circuits in an OLED display device.

(3) FIG. 3A is a schematic diagram illustrating a driving circuit according to the embodiment of the present disclosure.

(4) FIG. 3B is a waveform diagram illustrating changes of the signals shown in FIG. 3A.

(5) FIG. 4 is a schematic diagram illustrating a differential input circuit according to the embodiment of the present disclosure.

(6) FIG. 5 and FIG. 6 are schematic diagrams respectively illustrating the differential input circuit operating in a sampling phase and in a hold phase (voltage scaling phase) according to the embodiment of the present disclosure.

(7) FIG. 7 is a schematic diagram illustrating the gain amplifier operates in the amplification mode. FIG. 7 is corresponding to the sixth duration T6 shown in FIG. 3B.

(8) FIG. 8 is a schematic diagram illustrating an example of the implementation of the differential input circuit according to the embodiment of the present disclosure.

(9) FIG. 9 is a schematic diagram illustrating the characteristic of the differential input circuit according to the embodiment of present disclosure.

(10) FIG. 10 is a schematic diagram illustrating the conversion characteristic of the ADC.

DETAILED DESCRIPTION OF THE INVENTION

(11) FIG. 2 is a schematic diagram illustrating components related to sensing the OLED and/or TFT degradation information of the OLED pixel circuits in an OLED display device. The OLED display device 20 includes a display panel 27, a source driver 23, a timing controller 21, and a gate driver 25. Both the timing controller 21 and the display panel 27 are electrically connected to the source driver 23 and the gate driver 25.

(12) The display panel 27 display images with basic display elements 271 (pixels), and each of the basic display elements 271 includes an R-pixel circuit 271a, a G-pixel circuit 271b, and a B-pixel circuit 271c.

(13) The source driver 23 may include one or multiple driving circuits 231, 233, and each of the driving circuits 231, 233 further includes an ADC 231a, 233a, a multiplexer (hereinafter, MUX) 231b, 233b, a gain amplifier 231c, 233c, and multiple differential input circuits 2311, 2313, 2315, 2331, 2333, 2335. As the components and interconnections in the driving circuits 231, 233 are similar, only the driving circuit 231 is illustrated. Each driving circuit may be implemented as a semiconductor chip.

(14) The differential input circuit 2311 receives a first-channel (ch1) analog voltage signal through the sensing line SL.sub.1. The differential input circuit 2313 receives a second-channel (ch2) analog voltage signal V.sub.th(ch2) through the sensing line SL.sub.2. The differential input circuit 2315 receives a third-channel (ch3) analog voltage signal V.sub.th(ch3) through the sensing line SL.sub.3. It is noted that FIG. 2 is an exemplary diagram, and the sensing lines SL.sub.1˜SL.sub.3 and the pixel columns are not necessary to be in a one-on-one relationship. Based on the analog voltage signals respectively received from the sensing lines SL.sub.1˜SL.sub.3, the OLED/TFT degradation information may be acquired.

(15) According to the embodiment of the present disclosure, the number of driving circuits 231, 233 included in the source driver 23 is not limited. As shown in FIG. 2, the driving circuits 231, 233 may include multiplexers 231b, 231c, so that it is possible to equip one ADC in every driving circuit 231, 233.

(16) After receiving the analog voltage signals from the sensing lines SL.sub.1˜SL.sub.3, the differential input circuits 2311, 2313, 2315 samples, and scales down the analog voltage signals. Then, the ADCs 231a, 233a transform the scaled analog voltage signals into digitals signal representing ADC codes. The digital signals are further transmitted to the timing controller 21.

(17) As the digital signals originated from the analog voltage signals carrying the OLED and/or TFT degradation information of the OLED pixel circuits, the ADC codes can reflect the degradation statuses of the OLED/TFT of the OLED pixel circuits.

(18) According to the embodiment of the present disclosure, the multiplexer 231b receives selection signals EN.sub.sel from the timing controller 21. Basically, the selection signals EN.sub.sel are separately corresponding to the differential input circuits 2311, 2313, 2315, and the differential input circuits 2311, 2313, 2315. With the selection signals EN.sub.sel, the ADC 231a rotativity generates the digital signals corresponding to the differential input circuits 2311, 2313, 2315. In consequence, the timing controller 21 is capable of compensating the OLED and/or TFT degradation of the OLED panel.

(19) FIG. 3A is a schematic diagram illustrating a driving circuit according to the embodiment of the present disclosure. The driving circuit 30 includes a voltage sensing module 31, a selection module 32, a gain amplifier 33, an ADC 35, and a multiplexer 27. Depending on the number of channels to be supported by the driving circuit 30, the number of differential input circuits 311, 313 in the voltage sensing module 31 may vary. That is, a plurality of differential input circuits 311, 313 generate their outputs to the gain amplifier 33 in a time-multiplexing manner.

(20) For illustration purposes, the driving circuit 30 in FIG. 3A is assumed to support two channels. Thus, the voltage sensing module 31 includes two differential input circuits 311, 313, and the selection module 32 includes two selection circuits 321, 323. The differential input circuit 311 and the selection circuit 321 are respectively corresponding to a first channel (ch1), and the differential input circuit 313 and the selection circuit 323 are respectively corresponding to a second channel (ch2).

(21) According to the embodiment of the present disclosure, some signals are channel specific, but others are not. For example, a reference voltage V.sub.ref, a first shift voltage V.sub.shft1, a second shift voltage V.sub.shft2, a sampling enable signal EN.sub.sam, and a scaling enable signal EN.sub.scl are signals being transmitted to both the differential input circuits 311, 313. On the other hand, the analog voltage signals V.sub.th(ch1), V.sub.th(ch2) and the channel selection signals EN.sub.sel(ch1), EN.sub.sel(ch2) are channel specific. In the following context, the signals specific to individual channels are marked in brackets if necessary.

(22) The differential input circuit 311 includes a sampling circuit 311a and a scaling circuit 311b. Similarly, the differential input circuit 313 includes a sampling circuit 313a and a scaling circuit 313b. The signals and operations of the differential input circuit 313 are similar to those of the differential input circuit 311. Thus, only one differential input circuit is illustrated as an example in the following figures (FIGS. 4-8).

(23) The sampling circuits 311a, 313a are respectively electrically connected to the scaling circuits 311b, 313b. Both the sampling circuits 311a, 313a are controlled by the sampling enable signal EN.sub.sam and the reference voltage V.sub.ref. Both the scaling circuits 311b, 313b are controlled by the scaling enable signal EN.sub.scl, the first shift voltage V.sub.shft1, and the second shift voltage V.sub.shft2.

(24) The sampling enable signal EN.sub.sam, and the scaling enable signal EN.sub.scl are pulse signals issued by the timing controller (not illustrated). The generation and timing of the sampling enable signal EN.sub.sam, and the scaling enable signal EN.sub.scl are related and briefly illustrated in FIG. 3B. In short, the sampling enable signal EN.sub.sam, and the scaling enable signal EN.sub.scl are alternatively generated, and the pulse of the sampling enable signal EN.sub.sam is prior to the pulse of the scaling enable signal EN.sub.scl.

(25) The scaling circuits 311b, 313b are respectively electrically connected to the selection circuits 321, 323. The selection circuit 321 transmits the pair of differential input signals corresponding to the first channel (V.sub.in+(ch1), V.sub.in−(ch1)) to the gain amplifier 33, and the selection circuit 321 transmits the pair of differential input signals corresponding to the second channel (V.sub.in+(ch2), V.sub.in−(ch2)) to the gain amplifier 33. The multiplexer 37 generates and transmits two channel selection signals EN.sub.sel(ch1), EN.sub.sel(ch2) to the selection circuits 321, 323, respectively. Basically, the channel selection signals EN.sub.sel(ch1), EN.sub.sel(ch2) are utilized to select which of the selection circuits 321, 323 can transmit their output signals to the gain amplifier 33.

(26) The gain amplifier 33 may operate in a common mode (M.sub.cmn) or in an amplification mode (M.sub.amp). The timing controller controls the gain amplifier 33 to operate in the common mode (M.sub.cmn) with a common mode signal EN.sub.cmn, and in the amplification mode (M.sub.amp) with an amplification mode signal EN.sub.amp.

(27) When the gain amplifier 33 operates in the common mode (M.sub.cmn), none of the selection circuits 321, 323 transmits the differential input signals (V.sub.in+(ch1), V.sub.in−(ch1)), (V.sub.in+(ch1), (V.sub.in−(ch2)) to the gain amplifier 33.

(28) When the gain amplifier 33 operates in the amplification mode (M.sub.amp), one of the selection circuits 321, 323 transmits the pair of differential input signals (V.sub.in+(ch1), V.sub.in−(ch1)), (V.sub.in+(ch2), V.sub.in−(ch2)) to the gain amplifier 33, the gain amplifier 33 generates and transmits the pair of differential output signals (V.sub.out+, V.sub.out−) to the ADC 35, and the ADC 35 converts the differential output signals (V.sub.out+, V.sub.out−) to the digital signal. The input range of the ADC 35 is relatively lower than the voltage range of the analog voltage signal being sensed. The practical values of the input range and the output range of the ADC 35 are not limited.

(29) FIG. 3B is a waveform diagram illustrating changes of the signals shown in FIG. 3A. The vertical axis represents different signals, and the horizontal axes represent time. The voltage levels of these signals shown here are examples and not limited in practical application.

(30) The first waveform represents the sampling enable signal EN.sub.sam, and the second waveform represents the scaling enable signal EN.sub.scl. The third and the fourth waveforms represent channel selection signals (EN.sub.sel(ch1), EN.sub.sel(ch2)) to be respectively transmitted to the selection circuits 321, 323. The fifth waveform is a common mode signal EN.sub.cmn, and the sixth waveform is an amplification mode signal EN.sub.amp.

(31) The sampling enable signal EN.sub.sam significantly transits from a low voltage level to a high voltage level at time point t1, and transits from the high voltage level to the low voltage level at time point t3. The duration when the sampling enable signal EN.sub.sam is at the high voltage level is represented as a first duration T1. The sampling circuits 311a, 313a are enabled by the sampling enable signal EN.sub.sam during the first duration T1.

(32) The scaling enable signal EN.sub.scl significantly transits from a low voltage level to a high voltage level at time point t4, and transits from the high voltage level to the low voltage level at time point t5. The duration when the scaling enable signal EN.sub.scl is at the high voltage level is represented as a second duration T2. The end time point of the first duration T1 is the same as or before the start time point of the second duration T2. The short duration between the first duration T1 and the second duration T2 can be defined to prevent signal confliction.

(33) The sampling circuits 311a, 313a respectively sample the analog voltage signals V.sub.th(ch1), V.sub.th(ch2)) during the first duration T1. During the second duration T2, the scaling circuit 311b generates a pair of differential input signals (V.sub.in+(ch1), V.sub.in−(ch1)), and the scaling circuit 313b generates another pair of differential input signals (V.sub.in+(ch2), V.sub.in−(ch2)).

(34) The sampling circuits 311a, 313a simultaneously receive the sampling enable signal EN.sub.sam, and the scaling circuits 311b, 313b simultaneously receive the scaling enable signal EN.sub.scl. Alternatively speaking, operations of the sampling circuits 311a, 313a are synchronized, and operations of the scaling circuits 311b, 313b are synchronized. That is, the pair of differential input signals (V.sub.in+(ch1), V.sub.in−(ch1)), and another pair of differential input signals (V.sub.in+(ch2), V.sub.in−(ch2))) are generated at the same time.

(35) The channel selection signal EN.sub.sel(ch1) specific to the first channel (ch1) transits from the low voltage level to the high voltage level at time point t6, and transits from the high voltage level to the low voltage level at time point t7. The duration when the channel selection signal EN.sub.sel(ch1) specific to the first channel (ch1) is at the high voltage level is represented as a third duration T3. The end time point of the second duration T2 is the same as or before the start time point of the third duration T3. The short duration between the second duration T2 and the third duration T3 can be defined to prevent signal confliction.

(36) The channel selection signal EN.sub.sel(ch2) specific to the second channel (ch2) transits from the low voltage level to the high voltage level at time point t8, and transits from the high voltage level to the low voltage level at time point t9. The duration when the channel selection signal EN.sub.sel(ch2) specific to the second channel (ch2) is at the high voltage level is represented as a fourth duration T4. The end time point of the third duration T3 is the same as or before the start time point of the fourth duration T4. The short duration between the third duration T3 and the fourth duration T4 can be defined to prevent signal confliction.

(37) In FIG. 3B, the common mode signal EN.sub.cmn is assumed to transit from the low voltage level to the high voltage level at time point t2, and transits from the high voltage level to the low voltage level at time point t5. The duration when the common mode signal EN.sub.cmn is at the high voltage level is represented as a fifth duration T5.

(38) According to the embodiment of the present disclosure, the gain amplifier 33 must acquire a common mode voltage V.sub.cmn before the selection module 32 receives the channel selection signals EN.sub.sel(ch1), EN.sub.sel(ch2). For example, the start time point of the fifth duration T5 can be between time point t1 and t4, and the end time point of the fifth duration T5 can be before or the same as the time point t6.

(39) The amplification mode signal EN.sub.amp transits from the low voltage level to the high voltage level at time point t6, and transits from the high voltage level to the low voltage level at time point t10. The duration when the amplification mode signal EN.sub.amp is at the high voltage level is represented as a sixth duration T6. The end time point of the fifth duration T5 is the same as or before the start time point of the sixth duration T6. The short duration between the fifth duration T5 and the sixth duration T6 can be defined to prevent signal confliction.

(40) Based on the waveforms shown in FIG. 3B, the differential input circuits 311, 313 transform the analog voltage signals corresponding to sensing lines to pairs of differential input signals (V.sub.in+(ch1), V.sub.in−(ch1)), (V.sub.in+(ch2), V.sub.in−(ch2)) of the gain amplifier 33. Details of the design and operation of the differential input circuit according to the embodiment of the present disclosure are illustrated below. For the sake of illustration, only one differential input circuit is illustrated as an example.

(41) FIG. 4 is a schematic diagram illustrating a differential input circuit according to the embodiment of the present disclosure. The differential input circuit 41 includes a sampling circuit 411 and a scaling circuit 413. The sampling circuit 411 further includes a first sampling path 411a and a second sampling path 411b, and the scaling circuit 413 further includes a first scaling path 413a and a second scaling path 413b. The first scaling path 413a is electrically connected to the first sampling path 411a and the selection circuit 43. The second scaling path 413b is electrically connected to the second sampling path 411b and the selection circuit 43.

(42) The sampling circuit 411 receives the analog voltage signal V.sub.th and a reference voltage V.sub.ref. The first sampling circuit 411a selectively generates a first sampling voltage ΔV.sub.c1 according to the analog voltage signal V.sub.th and the reference voltage V.sub.ref, that is, ΔV.sub.c1=V.sub.th−V.sub.ref. The second sampling path 411b selectively generates a second sampling voltage ΔV.sub.c2 according to the reference voltage V.sub.ref and the analog voltage signal V.sub.th.

(43) The first scaling path 413a receives the first sampling voltage ΔV.sub.c1 and a first shift voltage V.sub.shft1, down scales the first sampling voltage ΔV.sub.c1 to a first scaled voltage ΔV.sub.cs1 with a first scaling ratio r.sub.s1, and generates one of the pair of differential input signals (for example, a non-inverting differential input signal V.sub.in+) according to the first shift voltage V.sub.shft1 and the first scaled voltage ΔV.sub.cs1. That is, ΔV.sub.cs1=ΔV.sub.c1*r.sub.s1, and V.sub.in+=V.sub.shft1+ΔV.sub.c1*r.sub.s1=V.sub.shft1+ΔV.sub.cs1.

(44) The second scaling path 413b receives the second sampling voltage ΔV.sub.c2 and a second shift voltage V.sub.shft1, down scales the second sampling voltage ΔV.sub.c2 to a second scaled voltage ΔV.sub.cs2 with a second scaling ratio r.sub.s2, and generates the other one of the pair of differential input signals (for example, an inverting differential input signal V.sub.in−) according to the second shift voltage V.sub.shft2 and the second scaled voltage ΔV.sub.cs2. That is, ΔV.sub.cs2=ΔV.sub.c2*r.sub.s2, and V.sub.in−=V.sub.shft2+ΔV.sub.c2*r.sub.s2=V.sub.shft2+ΔV.sub.cs2.

(45) According to the embodiment of the present disclosure, the first and the second shift voltages V.sub.shft1, V.sub.shft2 are direct current (hereinafter, DC) voltages, and the first shift voltage V.sub.shft1 is less than the second shift voltage V.sub.shft2 (V.sub.shft1<V.sub.shft2). Moreover, a range of the pair of differential input signals (V.sub.in+, V.sub.in−) is less than or equivalent to the difference between the first and the second shift voltages V.sub.shft1, V.sub.shft2. That is, |V.sub.in+−V.sub.in−|≤|V.sub.shft1−V.sub.shft2|. According to the embodiment of the present disclosure, the first shift voltage V.sub.shft1 and the second shift voltage V.sub.shft2 may have the same absolute values and inversed polarities that are relative to a reference point. For example, the first shift voltage V.sub.shft1 is −0.5V, and the second shift voltage V.sub.shft2 is +0.5V, relative to a reference point 0V; or, the first shift voltage V.sub.shft1 is +1V and the second shift voltage V.sub.shft2 is +2V, relative to a reference point +0.5V.

(46) The selection circuit 43 includes a first selection switch SW.sub.sel1 and a second selection switch SW.sub.2. The selection circuit 43 is electrically connected to the gain amplifier 45. When the channel selection signal EN.sub.sel corresponding to the differential input circuit 41 is at the high voltage level, the first selection switch SW.sub.sel1 and the second selection switch SW.sub.sel2 are switched on so that the first selection switch SW.sub.sel1 conducts the non-inverting differential input signal V.sub.in+ to the gain amplifier 45 and the second selection switch SW.sub.sel2 conducts the inverting differential input signal V.sub.in− to the gain amplifier 45.

(47) FIG. 5 and FIG. 6 are schematic diagrams respectively illustrating the differential input circuit operating in a sampling phase and in a hold phase (voltage scaling phase) according to the embodiment of the present disclosure. FIG. 5 is corresponding to the condition that the sampling enable signal EN.sub.sam is at the high voltage level (for example, the first duration T1 shown in FIG. 3B). FIG. 6 is corresponding to the condition that the sampling enable signal EN.sub.sam transits to the low voltage level and the scaling enable signal EN.sub.scl is at the high voltage level (for example, the second duration T2 shown in FIG. 3B).

(48) The internal components of the first sampling path 411a and the first scaling path 413a, and those of the second sampling path 411b and the second scaling path 413b are symmetric.

(49) The first sampling path 411a and the first scaling path 413a jointly generate the non-inverting differential input signal V.sub.in+ based on the analog voltage signal V.sub.th, the reference voltage V.sub.ref and the first shift voltage V.sub.shft1, accompanied with control of the sampling enable signal EN.sub.sam, and the scaling enable signal EN.sub.scl.

(50) The first sampling path 411a includes a first sampling switch sw.sub.s1, a first reference switch sw.sub.ref1 and a first sampling capacitor C.sub.s1. The first sampling switch sw.sub.s1 is electrically connected to a first receiving terminal N.sub.rv1 and a first sensing terminal N.sub.sen1. The first reference switch sw.sub.ref1 is electrically connected to a second receiving terminal N.sub.rv2 and a first reference terminal N.sub.ref1. The first sampling capacitor C.sub.s1 is electrically connected to the first sensing terminal N.sub.sen1, and the first reference terminal N.sub.ref1. When the sample enable signal EN.sub.sam is at the high voltage level, the first sampling switch sw.sub.s1 transmits/conducts the analog voltage signal to the first sensing terminal N.sub.sen1 and the first reference switch sw.sub.ref1 transmits/conducts the reference voltage V.sub.ref to the first reference terminal N.sub.ref1 such that the first sampling capacitor C.sub.s1 are charged, and the first sampling voltage ΔV.sub.c1 is generated between the first sensing terminal N.sub.sen1 and the first reference terminal N.sub.ref1.

(51) The first scaling path 413a includes a first scaling switch sw.sub.scl1, a first shift switch sw.sub.shft1, and a first charge sharing capacitor C.sub.cs1. The first scaling switch sw.sub.scl1 is electrically connected to the first sensing terminal N.sub.sen1 and a first scaling terminal N.sub.scl1. The first shift switch sw.sub.shft1 is electrically connected to the first reference terminal N.sub.ref and a first shift terminal N.sub.sft1. The first charge sharing capacitor C.sub.cs1 is electrically connected to the first scaling terminal N.sub.scl1 and the first shift terminal N.sub.sft1.

(52) When the scaling enable signal EN.sub.scl is at the high voltage level, the first scaling switch sw.sub.scl1 conducts the first sensing terminal N.sub.sen1 to the first scaling terminal N.sub.scl1, and the first shift switch sw.sub.shft1 conducts the first reference terminal N.sub.ref1 to the first shift terminal N.sub.sft1. Meanwhile, the first charge sharing capacitor C.sub.cs1 receives the first shift voltage V.sub.shft1 through the first shift terminal N.sub.sft1, and charges stored in the first sampling capacitor C.sub.s1 are shared by the first sampling capacitor C.sub.s1 and the first charge sharing capacitor C.sub.cs1.

(53) The second sampling path 411b and the second scaling path 413b jointly generate the inverting differential input signal V.sub.in− based on the analog voltage signal V.sub.th, the reference voltage V.sub.ref and the second shift voltage V.sub.shft2, accompanied with control of the sampling enable signal EN.sub.sam and the scaling enable signal EN.sub.scl. Since the implementation of the second sampling path 411b and the second scaling path 413b are similar to those of the first sampling path 411a and the first scaling path 413a, details of which are not redundantly described.

(54) The first sampling switch sw.sub.s1 and the first reference switch sw.sub.r, are switched on when the sampling enable signal EN.sub.sam is at the high voltage level. Meanwhile, the first sampling capacitor C.sub.s1 is charged, and the first sampling voltage ΔV.sub.c1 is generated between the first sensing terminal N.sub.sen1 and the first reference terminal N.sub.ref1. When the scaling enable signal EN.sub.scl is at the high voltage level, charges being accumulated in the first sampling capacitor C.sub.s1 in the sensing phase is jointly shared by two capacitors, that is, the first sampling capacitor C.sub.s1 and the first charge sharing capacitor C.sub.cs1. In consequence, the voltage between the first scaling terminal N.sub.scl1 and the first shift terminal N.sub.sft1 decreases and becomes less than the first sampling voltage ΔV.sub.c1. The voltage between the first scaling terminal N.sub.scl1 and the first shift terminal N.sub.sft1 after being scaled down is defined as a first scaled voltage ΔV.sub.cs1.

(55) Similarly, the second sampling switch sw.sub.s2 and the second reference switch sw.sub.ref2 are switched on when the sampling enable signal EN.sub.sam is at the high voltage level. Meanwhile, the second sampling capacitor C.sub.s2 is charged, and the second sampling voltage ΔV.sub.c2 is generated between the second reference terminal N.sub.ref2 and the second sensing terminal N.sub.sen2. When the scaling enable signal EN.sub.scl is at the high voltage level, charges being accumulated in the second sampling capacitor C.sub.s2 in the sensing phase is jointly shared by two capacitors, that is, the first sampling capacitor C.sub.s1 and the first charge sharing capacitor C.sub.cs1. In consequence, the voltage between the second scaling terminal N.sub.scl2 and the second shift terminal N.sub.sft2 decreases and becomes less than the second sampling voltage ΔV.sub.c2. The voltage between the second scaling terminal N.sub.scl2 and the second shift terminal N.sub.sft2 after being scaled down is defined as a second scaled voltage ΔV.sub.cs2.

(56) According to the embodiment of the present disclosure, the reference voltage V.sub.ref, the first shift voltage V.sub.shft1 and the second shift voltage V.sub.shft2 are direct current voltages. The first shift voltage V.sub.shft1 is lower than the second shift voltage V.sub.shft2 (V.sub.shft1<V.sub.shft2). The difference between the first and the second shift voltages (ΔV.sub.shft) can be represented as ΔV.sub.shft=V.sub.shft2−V.sub.shft1. Ranges of the pairs of the differential input signals (V.sub.in+(ch1), V.sub.in−(ch1)), (V.sub.in+(ch2), V.sub.in−(ch2)) are less than or equivalent to the difference between the first and the second shift voltages (ΔV.sub.shft).

(57) As shown in FIG. 5, the gain amplifier 45 can include an input stage circuit 451, a loading stage circuit 453, an interconnection path, a first conduction path 45a, and a second conduction path 45b. The first conduction path 45a is electrically connected to the first input terminal N.sub.in1 and the first output terminal N.sub.out−, and the second conduction path 45b is electrically connected to the second input terminal N.sub.in2 and the second output terminal N.sub.out+.

(58) The input stage circuit 451 is electrically connected to the selection circuit 43, from which the differential input signals V.sub.in+, V.sub.in− are received. The loading stage circuit 453 is electrically connected to the input stage circuit 452, the first output terminal N.sub.out−, and the second output terminal N.sub.out+. The interconnection path includes switches sw.sub.amp5, sw.sub.amp6, the first conduction path 45a includes switches sw.sub.amp1, sw.sub.amp2, sw.sub.amp7, and an amplification capacitor C.sub.amp1, and the second conduction path 45b includes switches sw.sub.amp3, sw.sub.amp4, sw.sub.amp8, and another amplification capacitor C.sub.amp2.

(59) When the gain amplifier 45 operates in the common mode (M.sub.cmn), switches sw.sub.amp1, sw.sub.amp2, sw.sub.amp3, sw.sub.amp4, swamps, sw.sub.amp6 are switched on, and switches sw.sub.amp7, sw.sub.amp8 are switched off. Through switches sw.sub.amp1, sw.sub.amp2, the first conduction paths 45a receive the common mode voltage V.sub.cmn. Through switches sw.sub.amp3, sw.sub.amp4, the second conduction paths 45b receive the common mode voltage V.sub.cmn.

(60) When the gain amplifier 45 operates in the amplification mode (M.sub.amp), the first conduction path 45a generates an inverting differential output signal V.sub.out− based on the common mode voltage V.sub.cmn and the pair of differential input signals (V.sub.in+, V.sub.in−), and the second conduction path 45b generates the non-inverting differential output signal V.sub.out+ based on the same.

(61) As for the gain amplifier 45, FIG. 6 is corresponding to the condition that the gain amplifier 45 is in the common mode (M.sub.cmn) (for example, the fifth duration T5 shown in FIG. 3B).

(62) Since the first scaling switch sw.sub.scl1 and the first shift switch sw.sub.shft1 are turned on by the scaling enable signal EN.sub.scl, the first charge sharing capacitor C.sub.cs1 shares charges stored in the first sampling capacitor C.sub.s1. In consequence, the first sampling voltage ΔV.sub.c1 is down scaled to the first scaled voltage ΔV.sub.cs1, and the non-inverting differential input signal V.sub.in+ is generated at the first scaling terminal N.sub.scl1. The generation of the non-inverting differential input signal V.sub.in+ can be represented as equation (1).

(63) $\begin{array}{cc}{V}_{\mathrm{in}+}=V_{\mathrm{shift}1}+\Delta {V_{c1}}^{*}{r}_{s1}=V_{\mathrm{shift}1}+\Delta V_{\mathrm{cs}1}=V_{\mathrm{shift}1}+\Delta {V_{c1}}^{*}{C}_{s1}/\left(C_{s1}+C_{\mathrm{cs}1}\right)& \mathrm{equation}\left(1\right)\end{array}$

(64) Since the second scaling switch sw.sub.scl2 and the second shift switch sw.sub.shft2 are turned on by the scaling enable signal EN.sub.scl, the second charge sharing capacitor C.sub.cs2 shares charges stored in the second sampling capacitor C.sub.s2. In consequence, the second sampling voltage ΔV.sub.c2 is down scaled to the second scaled voltage ΔV.sub.cs2, and the inverting differential input signal V.sub.in− is generated at the second scaling terminal N.sub.scl2. Generation of the inverting differential input signal V.sub.in− can be represented as equation (2).

(65) $\begin{array}{cc}{V}_{\mathrm{in}\text{-}}=V_{\mathrm{shift}2}+\Delta V_{\mathrm{cs}2}=V_{\mathrm{shift}2}+\Delta {V_{c2}}^{*}{C}_{s2}/\left(C_{s2}+C_{\mathrm{cs}2}\right)& \mathrm{equation}\left(2\right)\end{array}$

(66) The first sampling capacitor C.sub.s1 receives the analog voltage signal V.sub.th and the reference voltage V.sub.ref with its anode and cathode, respectively. The second sampling capacitor C.sub.s2 receives the analog voltage signal V.sub.th and the reference voltage V.sub.ref with its cathode and anode, respectively. Based on the assumption that C.sub.s1=C.sub.s2, magnitudes of the first sampling voltage ΔV.sub.c1 and the second sampling voltage ΔV.sub.c1 are equivalent but polarities of the first sampling voltage ΔV.sub.c1 and the second sampling voltage ΔV.sub.c2 are opposite.

(67) The first scaling ratio r.sub.s1 between the first scaled voltage ΔV.sub.cs1 and the first sampling voltage ΔV.sub.c1 thus can be determined based on capacitances of the first sampling capacitor C.sub.s1 and the first charge sharing capacitor C.sub.cs1. For example, in a case that Cs1=C and Ccs1=2*C, ΔV.sub.cs1=⅓*ΔV.sub.c1. Similarly, the second scaling ratio r.sub.s2 between the second scaled voltage ΔV.sub.cs2 and the second sampling voltage ΔV.sub.c2 can be determined based on capacitances of the second sampling capacitor C.sub.s2 and the second charge sharing capacitor C.sub.cs2.

(68) According to the embodiment of the present disclosure, capacitances of the first sampling capacitor C.sub.s1 and the second sampling capacitor C.sub.s2 are equivalent, and capacitances of the first charge sharing capacitor C.sub.cs1 and the second charge sharing capacitor C.sub.cs2 are equivalent. Therefore, the first scaling ratio r.sub.s1 is equivalent to the second scaling ratio r.sub.s2.

(69) Based on these equivalences (C.sub.s1=C.sub.s2, C.sub.cs1=C.sub.cs2, and ΔV.sub.c2=−ΔV.sub.c1), equation (2) can be re-written as equation (3).

(70) $\begin{array}{cc}{V}_{\mathrm{in}\text{-}}=V_{\mathrm{shift}2}+\Delta V_{\mathrm{cs}2}=V_{\mathrm{shift}2}+\Delta {V_{c2}}^{*}{C}_{s2}/\left(C_{s2}+C_{\mathrm{cs}2}\right)=V_{\mathrm{shift}2}\text{-}\Delta {V_{c1}}^{*}{C}_{s1}/\left(C_{s1}+C_{\mathrm{cs}1}\right)& \mathrm{equation}\left(3\right)\end{array}$

(71) FIG. 7 is a schematic diagram illustrating the gain amplifier operates in the amplification mode (M.sub.amp). FIG. 7 is corresponding to the sixth duration T6 shown in FIG. 3B.

(72) When the gain amplifier 45 operates in the amplification mode (M.sub.amp), switches sw.sub.amp1, sw.sub.amp2, sw.sub.amp3, sw.sub.amp4, sw.sub.amp5, swamps are switched off, and switches sw.sub.amp7, sw.sub.amp8 are switched on. Through amplification capacitor C.sub.amp1 and switch sw.sub.amp7, the first conduction path 45a feedbacks the inverting differential output signal V.sub.out− from the first output terminal N.sub.out− to the first differential input terminal N.sub.in1. Through amplification capacitor C.sub.amp2 and switch sw.sub.amp8, the second conduction path 45b feedbacks the non-inverting differential output signal V.sub.out+ from the second output terminal N.sub.out+ to the second differential input terminal N.sub.in2. In FIG. 7, the first conduction path 45a generates the inverting differential output signal V.sub.out− based on the common mode voltage V.sub.cmn and the differential input signals (V.sub.in+, V.sub.in−), and the second conduction path 45b generates the non-inverting differential output signal V.sub.out+ based on the same.

(73) FIG. 8 is a schematic diagram illustrating an example of the implementation of the differential input circuit according to the embodiment of the present disclosure. As shown in FIG. 8, the first sampling switch sw.sub.s1, the second sampling switch sw.sub.s2, the first reference switch sw.sub.ref1, the second reference switch sw.sub.ref2, the first selection switch sw.sub.scl1, and the second selection switch sw.sub.sel2 can be implemented by transmission gates; and the first scaling switch sw.sub.scl1, the second scaling switch sw.sub.shft2, the first shift switch sw.sub.shft1, and the second shift switch sw.sub.shft2 can be implemented by NMOS transistors. The implementation shown in FIG. 8 is an example, and the implementation in practical applications may vary.

(74) FIG. 9 is a schematic diagram illustrating the characteristic of the differential input circuit according to the embodiment of present disclosure. The horizontal axis represents the input voltage (V.sub.th−V.sub.ref) of the differential input circuit 41, and the vertical axis represents the differential output signals of the differential input circuit 41, that is, the differential input signal of the gain amplifier 45. In FIG. 9, line L1 represents the non-inverting differential input signal V.sub.in+, and line L2 represents the inverting differential output signal V.sub.in−.

(75) FIG. 10 is a schematic diagram illustrating the conversion curve of the input voltage (V.sub.th−V.sub.ref) of the differential input circuit to the code output by the ADC. The vertical axis represents the input voltage (V.sub.th−V.sub.ref) of the differential input circuit. The horizontal axis represents the ADC code. In FIG. 10, the maximum of the input voltage of the differential input circuit, (V.sub.th−V.sub.ref).sub.MAX, is corresponding to the largest ADC code, wherein the resolution of the ADC code is 10 bits as an example. Therefore, the smallest ADC code is assumed to be “0”, and the largest ADC code is assumed to be “1023”. In FIG. 10, line L3 represents the non-inverting differential input signal V.sub.in+, and line L4 represents the inverting differential output signal V.sub.in−.

(76) Under the assumption that the ADC operates in a range of 1V (voltage between the gain amplifier output, that is, |Vout+−Vout−|, is equivalent to 1V (|Vout+−Vout−|=1V), and the gain of the gain amplifier is equivalent to 1, the first shift voltage V.sub.sft1 can be designed as V.sub.shft1=−0.5, and the second shift voltage V.sub.shft2 can be designed as V.sub.shft2=+0.5V in order to satisfy with the relationship that V.sub.shft2−V.sub.shft1=1V.

(77) In addition, under the same assumption that the down scaling ratio is assumed to be equivalent to ⅓, the input voltage (V.sub.th−V.sub.ref) of the differential input circuit must be less than or equivalent to 3V to ensure that the down-scaled voltage (V.sub.in+−V.sub.in−) is maintained to be less than or equivalent to 1V. That is, the non-inverting differential input signal V.sub.in+ and the inverting differential input signal V.sub.in− must be satisfied with the following relationship: |V.sub.in+−V.sub.in−|≤|V.sub.shft1−V.sub.shft2|.

(78) The scenario that the analog voltage signal V.sub.th is equivalent to the minimum value and equivalent to the reference voltage Vref (for example, Vref=0V, Vth=0V) is discussed. Under such circumstance, the non-inverting differential input signal V.sub.in+ is equivalent to the first shift voltage V.sub.shft1 (V.sub.in+=−0.5+0*(⅓)=−0.5V=V.sub.shft1), according to equation (2). Moreover, according to equation (3), the inverting differential input signal V.sub.in− is equivalent to the second shift voltage V.sub.shft2 (V.sub.in−=+0.5+0*(⅓)=+0.5V=V.sub.shft2).

(79) The scenario that the analog voltage signal Vth is equivalent to 3V and the reference voltage Vref is equivalent to 0V (Vth=3V and Vref=0V) is discussed. Under such circumstance, the non-inverting differential input signal V.sub.in+ is equivalent to the second shift voltage V.sub.shft (V.sub.in+=−0.5V+3*(⅓)V=+0.5V), according to equation (2). Moreover, according to equation (3), the inverting differential input signal V.sub.in− is equivalent to the first shift voltage V.sub.shft1 (V.sub.in−=−0.5V+(−3)*(⅓)=−0.5V=V.sub.shft1).

(80) When the input voltage of the differential input circuit 41 (V.sub.th−V.sub.ref) is equivalent to zero, the analog voltage signal V.sub.th is equivalent to the reference voltage V.sub.ref, and the first sampling voltage ΔV.sub.c1 is equivalent to zero. According to equation (1), the non-inverting differential input signal V.sub.in+ can be obtained, that is, V.sub.in+=V.sub.shft1+(0)*C.sub.s1/(C.sub.s1+C.sub.cs1)=V.sub.shft1. Similarly, according to equation (3), the inverting differential input signal V.sub.in− can be obtained, that is, V.sub.in−=V.sub.shft2−(0)*C.sub.s1/(C.sub.s1+C.sub.cs1)=V.sub.shft2. Therefore, the non-inverting differential input signal V.sub.in+ is equivalent to the first shift voltage V.sub.shft1, and the inverting differential input signal V.sub.in− is equivalent to the second shift voltage V.sub.shft2.

(81) Based on the above illustrations, meanings of the lines L3, L4 in FIG. 10 are illustrated. When the input voltage of the differential input circuit 41, (V.sub.th−V.sub.ref) is equivalent to the minimum value (V.sub.th−V.sub.ref).sub.min, the differential output (V.sub.out+−V.sub.out−) of the gain amplifier is equivalent to the minimum value, and the corresponding ADC code is the smallest (ADC code=0). On the other hand, when the input voltage of the differential input circuit, (V.sub.th−V.sub.ref) is equivalent to the maximum value (V.sub.th−V.sub.ref).sub.max, the differential output (V.sub.out+−V.sub.out−) of the gain amplifier 45 is equivalent to the maximum value, and the corresponding ADC code is the largest (ADC code=1023).

(82) According to the embodiment of the present disclosure, the differential input circuit receives the analog voltage signal V.sub.th in a single-ended manner but provides a pair of fully differential signals to the gain amplifier. Consequentially, the gain amplifier is not necessary to transform a single-ended input to a differential output. Alternatively speaking, the signal quality of the driving circuit can be improved when the differential input circuit is capable of providing the fully differential signals to the gain amplifier.

(83) Although the illustrations above are based on the OLED display panel, the application of the present disclosure is not limited. Therefore, if there is a need for other display devices having the analog voltage signal to be scaled down, the embodiment of the present disclosure can be modified and applied.

(84) While the invention has been described by way of example and in terms of the preferred embodiment(s), it is to be understood that the invention is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements and procedures, and the scope of the appended claims therefore should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures.