Electrical device and method for manufacturing same

Abstract

A method for manufacturing an electrical device is disclosed. In an embodiment, the method includes providing a first layer of a first conductivity type, providing an intrinsic layer onto the first layer, providing one or more trenches into the intrinsic layer, filling the one or more trenches with a material of a second conductivity type opposite to the first conductivity type, and providing a second layer of a second conductivity type onto the intrinsic layer.

Claims

1. A method for manufacturing an electrical device, the method comprising: providing a first layer of a first conductivity type; providing an intrinsic layer onto the first layer; providing one or more deep trenches into the intrinsic layer such that the intrinsic layer has a reduced thickness at at least one portion; filling the one or more deep trenches with a material of a second conductivity type opposite to the first conductivity type; and providing a second layer of the second conductivity type onto the intrinsic layer, wherein an area of the at least one portion is less than 30% of an active area in which the first and second layers face each other, wherein the at least one portion is formed by one or more indenters having the second conductivity type, wherein the one or more indenters are electrically connected to the second layer and extend into the intrinsic layer, and wherein the one or more indenters are arranged in the deep trenches so as to form a pin-junction between the one or more indenters and the first layer with the intrinsic layer in-between.

2. The method for manufacturing according to claim 1, wherein providing the one or more deep trenches and filling the one or more deep trenches are performed after providing the second layer such that the filled deep trenches extend through the second layer into the intrinsic layer.

3. The method for manufacturing according to claim 1, wherein filling the one or more deep trenches is performed by epitaxy of polysilicon.

4. The method for manufacturing according to claim 3, further comprising etching the polysilicon.

5. The method for manufacturing according to claim 1, wherein filling the one or more deep trenches and providing the second layer are performed simultaneously.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Embodiments of the present invention are described in the following with respect to the figures, among which:

(2) FIG. 1 exemplarily shows a cross-sectional view of an electrical device comprising an intrinsic layer having a partially reduced thickness according to an embodiment;

(3) FIG. 2a exemplarily shows a cross-sectional view of an electrical device comprising an indenter for partially reducing a thickness of an intrinsic layer according to an embodiment;

(4) FIG. 2b exemplarily shows a top view of an electrical device comprising a plurality of indenters according to an embodiment;

(5) FIGS. 3a to 3b exemplarily show cross-sectional views of electrical devices comprising indenters according to further embodiments;

(6) FIG. 4 exemplarily illustrates a method for manufacturing an electrical device comprising an intrinsic layer having a partially reduced thickness according to an embodiment; and

(7) FIGS. 5a to 5b show two exemplary diagrams resulting from a device simulation of a TVS diode and a pin diode according to embodiments for illustrating turn on time improvements.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

(8) Different embodiments of the teachings disclosed herein will subsequently be discussed referring to FIG. 1 to FIG. 5. In the drawings, identical reference numerals are provided to objects having identical or similar functions so that objects referred to by identical reference numerals within the different embodiments are interchangeable and the description thereof is mutually applicable.

(9) FIG. 1 shows an electrical device 10 comprising a first layer 12 and a second layer 14, wherein an intrinsic layer 16 is arranged between the first and the second layer 12 and 14. The first layer 12 is of a first conductivity type, for example, an n+ doped layer, wherein the second layer 14 is of a second conductivity type opposite to the first conductivity type, for example, a p+ doped layer. The two layers 12 and 14 are arranged such that same face each other and form an active area with a pn-junction in between. Between the facing (parallel) layers 12 and 14 the intrinsic layer 16 is arranged, which may have a low doping concentration, e.g., n—(i.e., approx. 1e13 cm.sup.−3). In general, an intrinsic layer 16 has such a low doping that the layer is depleted of all free carriers even if no bias is applied. The intrinsic layer 16 which may be an epi layer has a reduced thickness w.sub.n2 (e.g., 2 to 10 μm) at at least one portion compared to a thickness w.sub.n1 (e.g., 5 to 20 μm) of the intrinsic layer 16. It should be noted that this area 18 of the at least one portion is less than 50%, or less than 30% or even less than 10% of the active area in which the layers 12 and 14 are overlapping.

(10) Due to the intrinsic layer 16 (depleted zone) in between a so-called PIN diode 10 is formed. Such a PIN diode 10 may be used in forward mode operation as a bypass diode for ESD (electrostatic discharge) protection, especially for circuits having just one polarity. The PIN diode 10 has preferably a small capacity depending on the thickness w.sub.n1 of the intrinsic layer 16. A reduced capacity may be achieved by an increase of the thickness w.sub.n1 (base width w.sub.n1). However, due to the increase of the entire thickness w.sub.n1 the time for switching between the blocking state into the conducting state is also increased. This time is called turn on time t and is defined by the formula
t=w.sub.n1.sup.2/2μ,
where μ is the mobility of the minority carriers within the base and the intrinsic layer 16, respectively. This increased turn on time t in combination with the small capacity may lead to an overshoot voltage which is built up during the turn on time t. Background thereon is that electrical charges of an applied current surge, which cannot be discharged while the diode 10 is in the blocking state, are charged into the diode 10 and build up the overshoot voltage due to the small the capacity. Therefore, it is the goal to reduce the turn on time t in order to avoid the overshoot voltage while maintaining the small capacity of the device 10. So, embodiments of the invention are based on the principle that the thickness w.sub.n2 of the intrinsic layer 16 is just partially reduced, namely in the area 18. Background thereof is that the capacitance depends primarily on the area, wherein the turn on time t depends primarily on the base width w.sub.n2. Therefore, the base width w.sub.n2 is just reduced in the limited area 18. In other words, the area 18 having the reduced thickness w.sub.n2 forms a further diode connected in parallel to the PIN diode 10, wherein the further diode has a reduced turn on time t. Due to the limited area 18, e.g., 5% of the active area, the turn on time t may significantly be reduced, while the capacitance is changed only a little bit.

(11) In this embodiment, the area 18 of the portion having the reduced thickness w.sub.n2 may be realized by a trench which extends, for example, 4 μm or 6 μm, into the intrinsic layer 16 and is filled by the material of the second layer 14. The trench and thus a portion of the second layer 14 extend typically more than 30% or 50% of the thickness w.sub.n1 of the intrinsic layer 16 into the intrinsic layer 16.

(12) FIG. 2a shows an electrical device 20 which substantially corresponds to the electrical device 10, wherein the area 18 having the reduced thickness w.sub.n2 is formed by an indenter 22. The indenter 22 extends from the second layer 14 into the intrinsic layer 16 up to a depth of 50% or 80% of the thickness w.sub.n1. The indenter 22 comprises a material which is of the same conductivity type of the second layer 14, for example, a p or p+ doped polysilicon, and is connected to the second layer 14. Here, the indenter 22 is provided after providing the second layer 14 (upper layer) such that same extends through the thin upper layer 14 (thickness preferentially smaller compared to the thickness of the intrinsic layer 16, e.g., less than 1 μm) into the intrinsic layer 16.

(13) As explained above, the indenter 22 has the purpose to reduce partially the thickness w.sub.n2 of the intrinsic layer 16 in order to speed up the turn on time t.

(14) According to another embodiment, the electrical device 20 may comprise an optional metallization layer 24 arranged on the upper layer 14 for electrically contacting the layer 14 (anode contact). The lower layer 12 may be electrically contacted via the substrate (cathode contact) which comprises the lower layer 12. So, the lower layer 12 may be arranged on the substrate or may be formed by the substrate which is, for example, doped. It should be noted that according to a further embodiment, in which reverse conductivity types are provided (substrate p doped and upper layer 14 n doped) the substrate forms the anode contact and the upper layer 14 the cathode contact.

(15) FIG. 2b shows a top view of an electrical device 21 which is substantially equal to the electrical device 20 of FIG. 2a, but further comprises a plurality of indenters 22. The indenters 22 are arranged in the same active area and embedded into the upper layer 14 and into the intrinsic layer (not shown).

(16) Thus, a plurality of diodes, which are connected in parallel to the proper electrical device 21 and to the diode 21, respectively, is formed by the plurality of indenters 22. According to further embodiments, the square-shaped indenters 22 which may have a size of 2×2 μm.sup.2 may be laterally evenly distributed over the active area such that the entire area of the plurality of indenters 22 is less than 50% or 10% of the active area. Therefore, a distance between two adjacent indenters 22 is typically larger than three times or five times a diameter or a side length of the respective indenter 22.

(17) FIGS. 3a and 3b show a further electrical device 30. The electrical device 30 comprises the lower layer 12, e.g., a p doped layer, arranged on a substrate 32, e.g., an n+ doped substrate. Further, the electrical device 30 comprises the upper layer 14, e.g., an n+ doped layer, and the intrinsic layer 16 between the lower and upper layer 12 and 14. As in the embodiment of FIG. 2a, the indenter 22 extends from the upper layer 14 into the intrinsic layer 16 in order to partially reduce the thickness of the intrinsic layer 16. Optionally, the electrical device 30 may comprise the metallization layer 24 for electrically connecting the upper layer 14.

(18) In this embodiment, the electrical device 30 may be used as a transistor wherein the substrate 32 forms the collector, the upper layer 14 the emitter, and the lower layer 12 together with the intrinsic layer 16 the base. Consequently, the base width w.sub.b1 is defined by the distance between the collector 32 (pn-junction) and the emitter 14. In the same way as the embodiment of FIG. 2, the turn on time t of the electrical device 30 is reduced by locally reducing the base width w.sub.b2 compared to the base width w.sub.b1 (wherein the reduced base width w.sub.b2 complies with the distance between the collector 32 and the indenter 22). Consequently, a capacity surge may be avoided. Expressed in other words, the indenter 22 forms a parallel transistor (connected in parallel to the transistor 30) which has a reduced turn on time t which is in quadratic portion to the reduced base width w.sub.b2. According to another embodiment, the electrical circuit 30 may comprise a plurality of indenters 22, as shown with respect to FIG. 2b.

(19) In case the base is left floated, the shown device 30 forms a diode, namely a so-called transient voltage suppressor (TVS) diode which has the purpose to protect electronic circuits against damaging high voltages. The transient voltage suppressor diode 10, also referred to as Zener or Avalanche diode, is typically connected to the circuit so that it is reverse biased, e.g., via the n-type side (cf. layer 12). Here, the transient voltage suppressor diode 10 is non-conducting if the voltage is below the avalanche breakdown voltage, e.g., 30 V or 70 V. If the voltage exceeds beyond this avalanche breakdown voltage, e.g., in case of a high voltage surge, the diode goes from the blocking state into the avalanche state and begins to conduct the overshoot current, for example, to ground. The avalanche breakdown takes place at the junction between the substrate 32 and the lower layer 12. As explained above the turn on time t (switching from the blocking state to the avalanche state) is reduced due to the provided indenters 22.

(20) FIG. 4 illustrates the method for manufacturing an electrical device comprising an indenter 22, wherein just the steps for reducing the thickness w.sub.b1 of the intrinsic layer 16 and for providing the indenter 22 are illustrated.

(21) So, the shown steps are performed after providing the lower (first) layer (not shown) and the intrinsic layer 16 onto the first layer. It should be noted that the intrinsic layer 16 is provided such that same has a constant thickness, for example, by using epitaxy. In order to partially reduce the thickness w.sub.b1 of the intrinsic layer 16, same is etched in the area 18, e.g., by trench or deep trench etching (see step 1). The trench may, for example, have a depth of 4 μm or up to 16 μm or a depth which is smaller (at least, e.g., 2%, 5%, 10% or 30%) when compared to the thickness w.sub.b1 of the intrinsic layer 16.

(22) The next step is filling the trench with a material, e.g., a p doped polysilicon, of same doping type as the upper layer. This step may be performed by polysilicon depositing (cf. step 2). Due to the polysilicon depositing the surface of the intrinsic layer 16 is covered with polysilicon, too. This polysilicon may form the upper (second) layer 14 directly. According to another embodiment, the polysilicon on the surface may be removed (see step 3), e.g., by reactive ion etching (RIE), so that another second layer, e.g., with a different doping concentration, may be provided. Thus, the non-removed material in the trench (see area 18) forms the indenter 22 embedded in the intrinsic layer 16. After these three steps 1, 2 and 3, the second layer 14 may be provided such that same has the conductivity type of the indenter 22 (if applicable with different doping concentration) and such that same is electrically connected to the indenter 22.

(23) It should be noted that the three illustrated steps of providing the trench (step 1), filling the trench with doped material (step 2), and removing the doped material from the surface (step 3) may, alternatively, be performed after providing the upper (second) layer 14 such that the indenter 20 extends through the upper layer 14.

(24) In FIGS. 5a and 5b the results of two device simulations, namely the simulation of a TVS diode (avalanche mode operation) and of a PIN diode (forward mode operation), are illustrated. Such simulations are used to demonstrate the performance improvement by an arrangement according the present invention. This evaluation method is based on a simulated transmission line pulse which is applied to the respective device within a 50 Ω system. The result of each simulation is shown by a diagram of a voltage of the respective diode resulting from the transmission line pulse plotted over the time.

(25) FIG. 5a shows the result for a 4000 μm.sup.2 (TVS-) diode in avalanche mode operation to which a transmission line pulse 38a, e.g., a 20 ampere pulse, has been applied. This transmission line pulse 38a increases the current up 0.5 ns and forms a plateau (20 A) after that point of time. During this increase of the current a so-called overshoot voltage is built up due to the parasitic capacitance of the diode up to the point of time when the avalanche breakdown is completed setting on. The overshoot voltage for a conventional diode is marked by the reference numeral 40a, wherein the overshoot voltage for the improved diode comprising the indenter is marked by the reference numeral 40′a. As illustrated by the graph 40a for the conventional diode a maximum overshoot voltage of, e.g., 70V is built up before the diode goes into avalanche. Here, the avalanche breakdown begins at approximately 0.3 ns and is completed approximately after 0.6 ns (cf. 40a). The graph 40′a of the improved diode shows that nearly none overshoot voltage is built up due to the reduced turn on time t. That is, the improved diode conducts the current before the transmission line pulse has been set on completely.

(26) FIG. 5b illustrates the result of the performance simulation of a PIN diode in the forward mode operation to which a 20 ampere transmission line pulse 38b has been applied. Similarly to the results illustrated in FIG. 5a the overshoot voltage 40b of a conventional PIN diode (e.g., 30 V) is avoided by using the improved version having a partially reduced base width w.sub.n2 (cf. 40b) due to its reduced turn on time t.

(27) Referring to FIG. 1 and FIG. 2a, it should be noted that the conductivity types of the layers 12 and 14 may be selected such that a NIP-diode is formed, i.e., that the layer 12 comprises a p+ dopant instead of an n+ dopant and the layer 14 comprises an n+ dopant instead of a p+ dopant. Analogously, the conductivity types used for the layers of the electrical circuit 30 may vary such that the substrate 32 may comprise a p+ dopant (instead of an n+ dopant), the lower layer 12 may comprise an n+ dopant (instead of a p+ dopant), and the upper layer 14 as well as the indenter 22 may comprise a p+ dopant (instead of an n+ dopant). According to an alternative embodiment, the applied doping concentration of the singular materials (e.g., for the first or second layer 12 and 14) may vary such that a lower (−) or higher (++) doping concentration may be used.

(28) Referring to FIG. 1 it should be noted that the area 18 having the reduced thickness w.sub.n2 is not necessarily embedded in the intrinsic layer 16. That is, the area 18 reduced regarding its thickness w.sub.n2 may be arranged adjacent to an area of the intrinsic layer 16 having a non-reduced thickness w.sub.n1. Expressed in other words, the intrinsic layer 18 is provides such that same forms a step.

(29) Referring to FIGS. 2b and 2c it should be noted that the size and the shape of the indenter 22 may, alternatively, be different so that the indenter 22 may have a round or elongated shape with diameter in the range between 1 μm and 10 or 20 μm.

(30) Referring to FIGS. 3a and 3b, it should be noted that the shown vertical transistor 30 may comprise further layers like a buried layer which is a low-resistance layer embedded in a high-resistance substrate 32.

(31) Although the layer arrangement of FIGS. 3a and 3b is explained in the context of a transistor, it should be noted that the layer arrangement may also be used as a transient voltage suppressor diode, wherein the substrate 32 forms the cathode and the upper layer 14 forms the anode. In case of NPN layer arrangement the substrate 32 forms the anode and the upper layer 14 the cathode.

(32) In general, it should be noted that the embodiments described above are merely illustrative for the principle of the present invention. These principles may be applied to further electrical devices, for example to an insulated gate bipolar transistor (IGBT) or to another semiconductor device. Therefore, it is understood that modifications and variations of the arrangement and the details described herein will be apparent to others skilled in the art.

(33) Therefore, it is the intent to be limited only by the scope of the appending patent claims and not by the specific details presented by way of description and explanation of the embodiments herein.