Image display apparatus with conversion analog signal generator

Abstract

An image display apparatus includes a conversion analog signal generator. A histogram value output section outputs histogram value data of image data of pixels of a line. An accumulator accumulates the histogram value data. The cumulative sums represent the number of analog switches turned off among a plurality of analog switches. A ramp signal data generator generates ramp signal data having a non-linear slope variably-controlled in accordance with the cumulative sum so as to reduce voltage fluctuation of the ramp signal due to load variation caused depending on the number of analog switches turned off. A DA converter converts the ramp signal data to an analog ramp signal and supplies the analog ramp signal to the plurality of analog switches.

Claims

1. An image display apparatus, comprising: a pixel section including a plurality of pixels arranged at intersections of a plurality of data lines and a plurality of gate lines; a vertical direction driver configured to sequentially supply a pixel selection signal to the plurality of gate lines and sequentially select each pixel of the pixel section on the basis of pixels of each line; a plurality of analog switches connected to the plurality of data lines one to one; a holding section configured to hold image data of pixels of a line of a display digital video signal; a conversion analog signal generator configured to generate a ramp signal composed of a sawtooth wave, to commonly supply the generated ramp signal to the plurality of analog switches, and to supply image data of the pixels of the line to the holding section in synchronization with the ramp signal, the ramp signal changing in level with time at such a slope that the level of the ramp signal starts with one of black and white levels at the beginning of each horizontal scanning period and reaches the other level right before the end of the horizontal scanning period and the slope is variably-controlled in accordance with the number of analog switches turned off among the plurality of analog switches to be non-linear; and a controller configured to simultaneously turn the plurality of analog switches on at the beginning of each horizontal scanning period to supply the ramp signal to the plurality of data lines through the plurality of analog switches, to compare on a pixel-by-pixel basis, the image data of the pixels of the line held by the holding section with a first counter value sequentially changing from one of minimum and maximum gray levels to the other in each horizontal scanning period, to turn off only the analog switches provided corresponding to the pixels having pixel data matching the first counter value until the beginning of the next horizontal scanning period, and through the data lines connected to the analog switches turned off, to cause the pixels to sample and hold the potential of the ramp signal just before the analog switches are turned off, wherein the conversion analog signal generator comprises: a histogram value output section configured to detect histogram values of respective gray levels included by image data of the pixels of the line and outputs histogram value data at each horizontal scanning period; an accumulator configured to accumulate the histogram value data to calculate a cumulative sum representing the number of analog switches turned off among the plurality of analog switches; a ramp signal data generator configured to generate ramp signal data having a non-linear slope variably-controlled in accordance with the cumulative sum so as to reduce voltage fluctuation of the ramp signal due to load variation caused and depending on the number of analog switches turned off; a DA converter configured to convert the ramp signal data to the ramp signal as an analog signal and supply the ramp signal to the plurality of analog switches; and a delay section configured to delay the image data of the pixels of the one line and supply the delayed image data to the holding section in synchronization with the ramp signal outputted from the DA converter.

2. The image display apparatus according claim 1, wherein the ramp signal data generator comprises: a counter configured to be reset by the horizontal scanning signal of the display digital video signal, count pulses of a clock with a predetermined frequency, and generate a second counter value synchronized with the first counter value; and a data generator configured to receive the second counter value generated by the counter and the cumulative sum calculated by the accumulator as an address and output the ramp signal data.

3. The image display apparatus according claim 2, wherein the ramp signal data outputted by the data generator is ramp signal data having a non-linear slope characteristic enabling degamma for the display digital video signal.

4. The image display apparatus according claim 1, wherein the ramp signal data generator comprises: a counter configured to be reset by the horizontal scanning signal of the display digital video signal, count pulses of a clock with a predetermined frequency, and generate a second counter value synchronized with the first counter value; a load variation correction data generator configured to generate load variation correction data to correct the load variation expressed by Z.sub.1/{(n−s)Z.sub.0+Z.sub.1} where n is the total number of the plurality of analog switches, s is the number of analog switches turned of at a predetermined timing among the plurality of analog switches (0<=s<=n), Z.sub.0 is output impedance of a buffer of the DA converter, and Z.sub.1 is input impedance of each of the plurality of analog switches; and a multiplier configured to multiply the second counter value generated by the counter by the load variation correction data generated by the load variation correction data generator and outputs the result of multiplication as the ramp signal data.

5. The image display apparatus according claim 1, wherein the ramp signal data generator comprises: a counter configured to be reset by the horizontal scanning signal of the display digital video signal, count pulses of a clock with a predetermined frequency, and generate a second counter value synchronized with the first counter value; a load variation correction data generator configured to generate load variation correction data to correct the load variation rate expressed by Z.sub.1/{(n−s)Z.sub.0+Z.sub.1} where n is the total number of the plurality of analog switches, s is the number of analog switches turned of at a predetermined timing among the plurality of analog switches (0<=s<=n), Z.sub.0 is output impedance of a buffer of the DA converter, and Z.sub.1 is input impedance of each of the plurality of analog switches; a data generator configured to receive the second counter value generated by the counter as an address and generate in accordance with the address, correction data for executing degamma for the display digital video signal or correcting the voltage-transmittance characteristic of liquid crystal elements included by the pixels; and a multiplier configured to multiply the correction data generated by the data generator by the load variation correction data and outputs the result of multiplication as the ramp signal data.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1A is a block diagram illustrating an image display apparatus according to at least one embodiment.

(2) FIG. 1B is a configuration diagram of an example of a pixel.

(3) FIG. 2 is a timing diagram for explaining a schematic operation of the image display apparatus according to the embodiment.

(4) FIG. 3 is a block diagram illustrating a concrete configuration example of a conversion analog signal generator illustrated in FIG. 1A.

(5) FIG. 4 is a timing diagram for explaining a schematic operation of the conversion analog signal generator illustrated in FIG. 3.

(6) FIG. 5 is a timing diagram for explaining operations of a histogram memory and an accumulator illustrated in FIG. 3.

(7) FIG. 6 is a table illustrating gray levels, histogram values, and cumulative sums for an image data input period for odd-numbered lines.

(8) FIG. 7 is a diagram illustrating an example of the relationship between load variation rate and the number of off analog switches.

(9) FIG. 8 is a diagram illustrating an example of the relationship between load variation correction data and the number of off analog switches.

(10) FIG. 9 is a diagram illustrating an example of display images of the image display apparatus according to the embodiment.

(11) FIG. 10A is a diagram illustrating the load variation rate of image 1C of the display image illustrated in FIG. 9.

(12) FIG. 10B is a diagram illustrating the load variation rate of image 2C of the display image illustrated in FIG. 9.

(13) FIG. 10C is a diagram illustrating the load variation rate of image 3C of the display image illustrated in FIG. 9.

(14) FIG. 11A is a diagram illustrating ramp signal data in displaying image 1C of the display image illustrated in FIG. 9.

(15) FIG. 11B is a diagram illustrating ramp signal data in displaying image 2C of the display image illustrated in FIG. 9.

(16) FIG. 11C is a diagram illustrating ramp signal data in displaying image 3C of the display image illustrated in FIG. 9.

(17) FIG. 12 is a block diagram illustrating the first configuration example of the ramp signal data generator illustrated in FIG. 3.

(18) FIG. 13 is a block diagram illustrating the second configuration example of the ramp signal data generator illustrated in FIG. 3.

(19) FIG. 14 is a block diagram illustrating the third configuration example of the ramp signal data generator illustrated in FIG. 3.

(20) FIG. 15A is a diagram illustrating an example of an original image to be displayed on a conventional image display apparatus.

(21) FIG. 15B is a diagram illustrating a display image displayed on the conventional image display apparatus based on the original image illustrated in FIG. 15A.

(22) FIG. 16 is a diagram illustrating an example of the equivalent circuit of an output section of the conversion analog signal generator and an analog switch.

(23) FIG. 17 is a diagram illustrating an example of the relationship between the number of off analog switches and input voltage of analog switches in the conventional image display apparatus.

DETAILED DESCRIPTION

(24) A description is given of an embodiment with reference to the drawings. FIG. 1A is a block diagram illustrating an image display apparatus according to the embodiment, and FIG. 1B is a configuration diagram illustrating an example of a pixel.

(25) An image display apparatus 100 according to the embodiment is a liquid crystal display apparatus used in a reflective liquid crystal projector or the like.

(26) The image display apparatus 100 includes a conversion analog signal generator 101, a driving pulse generator 102, a shift resistor circuit 103, a one-line latch circuit 104, a gray-level counter 105, comparators 106.sub.1 to 106.sub.n, analog switches 107.sub.1 to 107.sub.n, a pixel section 108, and a vertical driving circuit 109.

(27) The conversion analog signal generator 101 receives a digital video signal ID to be displayed, a vertical synchronization signal VD, a horizontal synchronization signal HD, and a clock CLK.

(28) The conversion analog signal generator 101 performs predetermined processing described below to generate a display digital video signal SVD and a ramp signal VREF which are in synchronization.

(29) The display digital video signal SVD is supplied to the shift resistor circuit 103, and the ramp signal VREF is supplied through a ramp signal line Ls to input terminals of the analog switches 107.sub.1 to 107.sub.n.

(30) The ramp signal VREF is a sawtooth wave which gradually changes in level in the same period as one horizontal scanning period so as to start with one of either black or white levels and reach the other level just before the end of the horizontal scanning period.

(31) The driving pulse generator 102 receives the vertical synchronization signal VD, horizontal synchronization signal HD, and clock CLK. The driving pulse generator 102 generates a driving signal synchronized with the display digital video signal SVD and ramp signal VREF and supplies the generated driving signal to the vertical driving circuit 109.

(32) The shift resistor circuit 103 sequentially shifts the supplied display digital video signal SVD on a pixel-by-pixel basis. The one-line latch circuit 104 temporarily holds the digital video signal (hereinafter, also referred to as pixel data) outputted in parallel from the shift resistor circuit 103, on a line-by-line basis.

(33) The shift resistor circuit 103 and one-line latch circuit 104 constitute a holding section to hold image data of pixels of a line in the display digital video signal SVD.

(34) The gray-level counter 105 counts pulses of the clock CK with a predetermined frequency synchronized with the synchronization signal of the digital video signal ID and outputs counter value QD (referential gray-level data) which changes from the minimum to the maximum gray-level to be displayed and comes to the same value again in a one-line period.

(35) The n comparators 106.sub.1 to 106.sub.n are provided corresponding to the n pixels arrayed in the horizontal direction of the pixel section 108. The n comparators 106.sub.1 to 106.sub.n compare the counter value QD of the gray-level counter 105 with respective n pieces of pixel data of each line from the one-line latch circuit 104 and output a matching pulse when the counter value QD matches the pixel data.

(36) The analog switches 107.sub.1 to 107.sub.n are provided corresponding to the comparators 106.sub.1 to 106.sub.n and n pixels arrayed in the horizontal direction of the pixel section 108, respectively. At every horizontal scanning period, the analog switches 107.sub.1 to 107.sub.n are controlled and turned on simultaneously at the beginning of the horizontal scanning period, and each analog switch 107.sub.1 to 107.sub.n supplies the ramp signal VREF through corresponding data line D.sub.1 to D.sub.n to m pixels arrayed in the vertical direction in the pixel section 108.

(37) The pixel section 108 is composed of pixels arrayed in a two-dimensional matrix (n pixels in the horizontal direction of the screen by m pixels in the vertical direction: m rows by n columns).

(38) In the pixel section 108, m pixels of each column (in the vertical direction) are connected to one of the n data lines D.sub.1 to D.sub.n, and n pixels arrayed in each row (in the horizontal direction) are coupled to one of the m gate lines G.sub.1 to G.sub.m.

(39) That is, the pixel section 108 is composed of n×m pixels provided at intersections of the n data lines D.sub.1 to D.sub.n and the m gate lines G.sub.1 to G.sub.m.

(40) Each pixel can be a pixel 110 configured as illustrated in FIG. 1B, for example. In FIG. 1B, the pixel 110 includes a pixel selection transistor Q, a signal holding capacitance Cs, and a liquid crystal element 111, which are provided at the intersection of a data line D and a gate line G.

(41) The data line D is any one of the data lines D.sub.1 to D.sub.n of FIG. 1A, and the gate line G is any one of the gate lines G.sub.1 to G.sub.n.

(42) In the pixel selection transistor Q, the gate is connected to the gate line G, the drain is connected to the data line D, and the source is connected to an ungrounded terminal of the signal holding capacitance Cs and a pixel driving electrode PE of the liquid crystal element 111.

(43) The pixel 110 is selected when the pixel selection transistor Q is turned on by a pixel selection signal (a gate signal) inputted through the gate line G. The pixel 110 receives the ramp signal through the data line D connected to the corresponding one of the analog switches 107.sub.1 to 107.sub.n.

(44) The pixel 110 is configured so that the ramp signal (or a DA-converted analog video signal) sampled when the analog switch is turned off is written and held in the signal holding capacitance Cs through the pixel selection transistor Q and is then applied to the pixel driving electrode PE of the liquid crystal element 111.

(45) The liquid crystal element 111 as an example of the display elements has a structure in which a liquid crystal layer LCM is sandwiched between the pixel driving electrode PE and a common electrode (a transparent electrode) CE facing each other. To the common electrode CE, common voltage Vcom is applied.

(46) The pixel driving electrode PE is driven with voltage corresponding to analog video signal voltage (the sampled ramp signal voltage herein) to control the light transmittance of the liquid crystal layer LCM. The liquid crystal element 111 thus displays video.

(47) The vertical driving circuit 109 constitutes a vertical direction driver and receives the driving signal. The vertical driving circuit 109 supplies the pixel selection signal sequentially to the m gate lines, one gate line (G1 to Gm) per horizontal scanning period (1H), which is synchronized with the horizontal synchronization signal HD, to repeatedly select n pixels arrayed in the same row of the pixel section 108 at the same time. The vertical driving circuit 109 thereby selects all the pixels in one frame period.

(48) Next, a description is given of the schematic operation of the image display apparatus 100 illustrated in FIG. 1A with reference to the timing diagram of FIG. 2.

(49) The conversion analog signal generator 101 generates the display digital video signal SVD illustrated in (b) of FIG. 2 and ramp signal VREF illustrated in (i) of FIG. 2. The display digital video signal SVD includes pixel data composed of plural bits synthesized in chronological order and is synchronized with the horizontal synchronization signal HD illustrated in (a) of FIG. 2. The ramp signal VREF has the same period as the horizontal scanning period.

(50) The shift resistor circuit 103 sequentially shifts and loads the inputted display digital video signal SVD line by line based on shift clock SCLK illustrated in (c) of FIG. 2.

(51) When the shift resistor circuit 103 finishes loading part of the display digital video signal SVD corresponding to a line, the one-line latch circuit 104 temporarily holds n pieces of pixel data of the line which are outputted from the shift resistor circuit 103 in parallel as schematically illustrated in (d) of FIG. 2. After holding the pixel data, the one-line latch circuit 104 supplies the same to the first data input terminals of the comparators 106.sub.1 to 106.sub.n.

(52) The gray level counter 105 counts the pulses of the clock CK illustrated in (e) of FIG. 2 and outputs the counter value QD in synchronization with each horizontal scanning period. The counter value QD represents plural gray levels sequentially varied from the minimum to the maximum value as illustrated in (f) of FIG. 2. The gray level counter 105 commonly supplies the counter value QD to second data input terminals of the comparators 106.sub.1 to 106.sub.n.

(53) The comparators 106.sub.1 to 106.sub.n independently compare the pixel data supplied to the first data input terminals on a pixel-by-pixel basis with the counter value QD commonly supplied to the second data input terminals. When the pixel data matches the counter value QD, the comparator 106.sub.1 to 106.sub.n outputs a matching pulse.

(54) The comparator 106.sub.1 to 106.sub.n supplies a matching pulse to the corresponding one of the analog switches 107.sub.1 to 107.sub.n to turn off the same.

(55) The gray level counter 105 and comparators 106.sub.1 to 106.sub.n constitute an analog switch controller.

(56) The analog switches 107.sub.1 to 107.sub.n receive switch start pulses illustrated in (g) of FIG. 2 and are turned on simultaneously at the beginning of every horizontal scanning period.

(57) The switch start pulses, clock CK, shift clock SCLK, ramp signal VREF are all synchronized with the horizontal synchronization signal HD.

(58) Some of the analog switches 107.sub.1 to 107.sub.n are then turned off upon the matching pulses outputted from the comparators 106.sub.1 to 106.sub.n provided corresponding thereto.

(59) (h) of FIG. 2 illustrates timings when a certain one of the analog switches 107.sub.1 to 107.sub.n is opened and closed. The high level thereof schematically represents on periods while the low level schematically represents off periods.

(60) (h) of FIG. 2 illustrates that the analog switch receives a matching pulse and is turned off upon a change from the high level to the low level.

(61) As for the analog switch with the opening and closing timings illustrated in (h) of FIG. 2, the analog switch is turned off when the gray level of a pixel which is at a certain line in the pixel column corresponding to the analog switch of interest is equal to a counter value QD of j and is turned off at the next line when the gray level of the pixel is equal to a counter value QD of k.

(62) The potentials of the data lines connected to the analog switches 107.sub.1 to 107.sub.n gradually increase with the inputted ramp signal VREF while the analog switches 107.sub.1 to 107.sub.n are on.

(63) Once each analog switch is turned off, the analog switch remains turned off until the beginning of the next horizontal scanning period. Accordingly, the potential of the ramp signal VREF (indicated by white circles in (i) of FIG. 2) just before the analog switch is turned off is sampled and held in the corresponding data line.

(64) The sampled and held potential is held by the signal holding capacitance Cs of a pixel which is selected by the gate lines G.sub.1 to G.sub.m among the m pixels arrayed in the vertical direction in the pixel section 108 and connected via the data line of interest.

(65) The voltage of the ramp signal VREF held at this time corresponds to the pixel value (the gray level) of the pixel of interest in the digital video signal. That is, the pixel data of the inputted display digital video signal SVD is converted to the analog video signal, which is then stored in the signal holding capacitance Cs of the pixel of interest.

(66) As described above, in each pixel, the voltage of the ramp signal VREF just before the corresponding one of the analog switches 107.sub.1 to 107.sub.n is turned off, is held by the signal holding capacitance Cs of the pixel until the next frame to drive the liquid crystal element of the pixel.

(67) In the image display apparatus 100, the time when the analog switches 107.sub.1 to 107.sub.n are turned off, that is, the time when the voltage of the ramp signal is sampled and held, depends on the picture design of the video signal to be displayed. The analog switches 107.sub.1 and 107.sub.n are all turned off at the same time in some cases, or are turned off at different times in other cases.

(68) The order that the analog switches 107.sub.1 to 107.sub.n are turned off is also not fixed. When the level of the inputted ramp signal VREF gradually changes from the black level (corresponding to 0% light transmittance of the liquid crystal layer) to the white level (corresponding to 100% light transmittance of the liquid crystal layer), the analog switches are turned off in ascending order of gray levels to be displayed by the pixels connected to the respective analog switches. The order of turning off the analog switches depends on each picture.

(69) The image display apparatus 100 has features including good linearity due to the operation of the DA conversion using the ramp signal. The image display apparatus 100 includes the conversion analog signal generator 101 in order to reduce tonality degradation (waveform interference) due to voltage fluctuation of the ramp signal, which is caused by a load variation of the ramp signal data generator that dynamically changes on the basis of lines in the digital video signal for the display.

(70) Next, a description is given of the configuration and operation of the conversion analog signal generator 101 in detail.

(71) FIG. 3 is a block diagram illustrating a specific configuration example of the conversion analog signal generator 101, and FIG. 4 is a timing diagram for explaining the schematic operation of the conversion analog signal generator 101 illustrated in FIG. 3. For convenience, the time axis of (a) to (d) of FIG. 4 is different from that of (e) to (r).

(72) As illustrated in FIG. 3, the conversion analog signal generator 101 receives the digital video signal ID to be displayed, the vertical synchronization signal VD, the horizontal synchronization signal HD, and the clock CLK.

(73) The conversion analog signal generator 101 includes an odd-numbered line ramp signal data generator 201A, an even-numbered line ramp signal data generator 201B, a one-bit line counter 202, an address counter 203, a NOT circuit 204, an image data selector 211, a histogram value selector 212, a ramp signal data generator 213, and a DA converter 214.

(74) The conversion analog signal generator 101 generates and outputs the display digital video signal SVD and ramp signal VREF.

(75) The odd-numbered line ramp signal data generator 201A includes an odd-numbered one-line data memory 205a (hereinafter, referred to as a data memory 205a), an odd-numbered line histogram memory 206a (hereinafter, referred to as a histogram memory 206a), an AND circuit 207a, an adder 208a, a switch 209a, and an odd-numbered line accumulator 210a.

(76) The histogram memory 206a is a histogram value output section configured to detect histogram values of respective gray levels of the image data of pixels in each odd-numbered line every horizontal scanning period and outputs histogram value data.

(77) The even-numbered line ramp signal data generator 201B has the same configuration as that of the odd-numbered line ramp signal data generator 201A.

(78) The even-numbered line ramp signal data generator 201B includes an even-numbered one-line data memory 205b (hereinafter, referred to as a data memory 205b), an even-numbered line histogram memory 206b (hereinafter, referred to as a histogram memory 206b), an AND circuit 207b, an adder 208b, a switch 209b, and an even-numbered line accumulator 210b.

(79) The histogram memory 206b is a histogram value output section configured to detect histogram values of respective gray levels of the image data of pixels in each even-numbered line every horizontal scanning period and outputs histogram value data.

(80) The data memories 205a and 205b and histogram memories 206a and 206b are dual port memories which independently enable reading and writing.

(81) The processing is separately performed for odd-numbered lines and even-numbered lines because a one line period is required to generate a histogram. The histogram is not fixed during this period.

(82) Specifically, while the histogram values are generated in one of the odd-numbered and even-numbered line processes, the histogram values are read in another process. These processes are alternated line by line.

(83) The data memories 205a and 205b are used to accommodate the time delay corresponding to one line which is produced at the histogram generation.

(84) The one-bit line counter 202 is supplied with the vertical synchronization signal VD illustrated in (b) of FIG. 4 and the horizontal synchronization signal HD illustrated in (c) and (g) of FIG. 4. The one-bit line counter 202 generates a determination signal LINE indicating whether the image data ID of the input digital video signal illustrated in (a) and (e) of FIG. 4 is odd-numbered line image data ID(1), ID(3), . . . or even-numbered line image data ID(2), ID(4), . . . .

(85) As illustrated in (d) and (h) of FIG. 4, the determination signal LINE is 1 when the image data is image data for odd-numbered lines, and is 0 when the image data is image data for even-numbered lines.

(86) The one-bit line counter 202 supplies the determination signal LINE as a write enable signal to write enable terminals WE of the data memory 205a and histogram memory 206a.

(87) The NOT circuit 204 reverses the polarity of the determination signal LINE, and supplies the obtained signal as a write enable signal to the write enable terminals WE of the data memory 205b and histogram memory 206b.

(88) The AND circuit 207a supplies the AND of the determination signal LINE and the horizontal synchronization signal HD to clear terminals CLR of the histogram memory 206a and the odd-numbered line accumulator 210a as a clear signal.

(89) The AND circuit 207b supplies the AND of the horizontal synchronization signal HD and the signal obtained by reversing the polarity of the determination signal LINE through the NOT circuit 204 to clear terminals CLR of the histogram memory 206b and the even-numbered line accumulator 210b as a clear signal.

(90) The address counter 203 generates a counter value AC (schematically illustrated in (i) of FIG. 4) synchronized with the image data ID, from the horizontal synchronization signal HD and clock CLK illustrated in (f) of FIG. 4.

(91) The address counter 203 supplies the generated counter value AC to write address terminals WADRS and read address terminals RADRS of the data memories 205a and 205b.

(92) When the write enable signal is 1, the image data ID inputted to terminals WDATA is written in the data memories 205a and 205b. When the write enable signal is 0, the data memories 205a and 205b output the written image data ID from terminals RDATA.

(93) The write enable signals supplied to the data memories 205a and 205b have polarities opposite to each other as described above and are set to 1 and 0 for odd-numbered and even-numbered lines, respectively.

(94) The image data of a certain odd-numbered line is written in the data memory 205a and is then outputted from the data memory 205a during the input period of the next even-numbered line as schematically illustrated in (j) of FIG. 4.

(95) The image data of a certain even-numbered line is written in the data memory 205b and is then outputted from the data memory 205b during the next period to input an odd-numbered line as schematically illustrated in (n) of FIG. 4.

(96) When the determination signal LINE supplied to a select terminal SEL is 0, the image data selector 211 selects and outputs odd-numbered line image data ID_ODD which is read from the data memory 205a and supplied to a terminal A.

(97) When the determination signal LINE is 1, the image data selector 211 selects and outputs even-numbered line image data ID_EVEN which is outputted from the data memory 205b and supplied to a terminal B.

(98) The image data selector 211 thereby selects image data of an even-numbered line during each odd-numbered line input period of the input image data ID and selects image data of an odd-numbered line during each even-numbered line input period as schematically illustrated in (q).

(99) The image data selector 211 supplies the selected image data to the shift resistor circuit 103 (FIG. 1A) as the display digital video signal SVD.

(100) The data memories 205a and 205b and image data selector 211 constitute a one-line delay circuit (a delay section) and has a function of selectively outputting one of odd-numbered and even-numbered lines.

(101) In synchronization with the ramp signal VREF outputted from the DA converter 214, the delay section composed of the data memories 205a and 205b and image data selector 211 delays image data of pixels of each line and supplies the same to the holding section composed of the shift resistor circuit 103 and one-line latch circuit 104.

(102) In the histogram memory 206a, the histogram for a certain line is written during the period when the image data of an odd-numbered line is written in the data memory 205a. In the histogram memory 206b, the histogram for a certain line is written during the period when the image data of an even-numbered line is written in the data memory 205b.

(103) The adders 208a and 208b add 1 to read data outputted from terminals RDATA of the histogram memories 206a and 206b and supplies the results to terminals WDATA of the same, respectively.

(104) Specifically, the histogram memories 206a and 206b generate histogram values in the following manner: the input image data ID is supplied to the write address terminals WADRS; and the values obtained by adding 1 to the read data from the histogram memories 206a and 206b through the adders 208a and 208b are written in the histogram memories 206a and 206b.

(105) The read data from the histogram memories 206a and 206b are values stored at addresses corresponding to the gray levels of pixels in the input image data ID which are supplied to the write address terminals WADRS.

(106) Before histogram values for a certain line are written in the histogram memories 206a and 206b, all of the histogram values of another line previously stored in the histogram memories 206a and 206b are cleared by clear signals.

(107) The read address terminals RADRS of the histogram memories 206a and 206b are supplied with read address signals having opposite truth values through switches 209a and 209b, and reading operation for the histogram memories 206a and 206b is performed for each line which is not subjected to writing operation.

(108) The odd-numbered line accumulator 210a accumulates plural histogram values HISTD_ODD of each odd-numbered line as schematically illustrated in (k) of FIG. 4. The histogram values HISTD_ODD are sequentially read from the terminal RDATA of the histogram memory 206a in the same period (1H) as each horizontal scanning period after the odd-numbered line accumulator 210a is cleared by a signal with the period 1H from the AND circuit 207a.

(109) The odd-numbered line accumulator 210a outputs a calculated cumulative sum HISTADD_ODD as schematically illustrated in (m) of FIG. 4.

(110) The even-numbered line accumulator 210b accumulates plural histogram values HISTD_EVEN of each even-numbered line as schematically illustrated in (o) of FIG. 4. The histogram values HISTD_EVEN are sequentially read from the terminal RDATA of the histogram memory 206b in the period 1H after the even-numbered line accumulator 210b is cleared by the signal of the period 1H from the AND circuit 207b.

(111) The even-numbered accumulator 210b outputs a calculated cumulative value HISTADD_EVEN as schematically illustrated in (p) of FIG. 4.

(112) When the determination signal LINE supplied to a select terminal SEL of the histogram value selector 212 is 0, the histogram value selector 212 selects and outputs the cumulative value HISTADD_ODD for each odd-numbered line which is read from the odd-numbered line accumulator 210a and is supplied to a terminal A (illustrated (m) of FIG. 4).

(113) When the determination signal LINE is 1, the histogram value selector 212 selects and outputs the cumulative value HISTADD_EVEN for even-numbered lines which is read from the even-numbered line accumulator 210b and is supplied to a terminal B (illustrated (p) of FIG. 4).

(114) The histogram value selector 212 outputs histogram value data HISTD that represents histogram values for the same line as the line the image data of which is outputted from the image data selector 211 as schematically illustrated in (r) of FIG. 4.

(115) In (r) of FIG. 4, a1, b1, c1, d1, . . . illustrated in HISTD(1) are occurrence frequencies (histogram values) of respective gray levels in odd-numbered line image data ID(1). a2, b2, c2, d2, . . . illustrated in HISTD(2) are occurrence frequencies (histogram values) of respective gray levels in even-numbered line image data ID(2).

(116) Next, a description is given of the operations of the histogram memories 206a and 206b, and odd-numbered and even-numbered line accumulators 210a and 210b in more detail with reference to the timing diagram of FIG. 5.

(117) The input image data ID illustrated in (a) of FIG. 5 is synchronized with the vertical synchronization signal (vertical reset signal) VD, the horizontal synchronization signal (horizontal reset signal) HD illustrated in (c) of FIG. 5, and the clock CLK illustrated in (b) of FIG. 5.

(118) (d) of FIG. 5 illustrates the determination signal LINE outputted from the one-bit line counter 202 (FIG. 3). Herein, the determination signal LINE is 1 when the input image data ID is odd-numbered line image data ID(11) and is 0 when the input image data ID is even-numbered line image data ID(12).

(119) As illustrated in (e) of FIG. 5, for example, the address counter 203 counts from 0 to 7 in increments of one in each period 1H and outputs the counter value AC. The address counter 203 repeatedly counts up in each period 1H. Herein, the number of pieces of image data (the number of horizontally arrayed pixels) in each period 1H is set to 8 for simple explanation.

(120) During each odd-numbered line image data input period when the determination signal LINE is 1, the histogram memory 206a generates a histogram of an odd-numbered line.

(121) During the above input period, the determination signal LINE of 1 is inputted to the write enable terminal WE of the histogram memory 206a as the write enable signal as illustrated in (h) of FIG. 5.

(122) To the read address terminal RADRS of the histogram memory 206a, as schematically illustrated in (j) of FIG. 5, the odd-numbered line input image data ID(11) illustrated in (a) of FIG. 5 is inputted through the switch 209a that is connected to a terminal 1.

(123) To the write address terminal WADRS of the histogram memory 206a, the pixel values of the input image data ID(11) as schematically illustrated in (i) of FIG. 5 are inputted as the write address. In the histogram memory 206a, data supplied to the terminal WDATA from the adder 208a (schematically illustrated in (m) of FIG. 5) is written using the pixel values of the input image data ID (11) as the write address.

(124) The data read from the terminal RDATA of the histogram memory 206a represents the number of times that the write address inputted to the write address terminal WADRS is selected before the data is read as illustrated in (k) of FIG. 5.

(125) The write data written in the histogram memory 206a is the value obtained by adding 1 through the adder 208a to data which is read from the terminal RDATA and represents the number of times that the write address is selected.

(126) Specifically, in the input image data ID(11), eight pixels carry pixel values (gray levels) of 2, 5, 3, 2, 7, 2, 5, and 3 as illustrated in (a) of FIG. 5, for example. When these pixel values are inputted sequentially, the histogram memory 206a selects an address indicating each gray level as the read and write addresses.

(127) In the histogram memory 206a, the value obtained by adding 1 to the number of times written in the selected read and write addresses is written.

(128) To the clear terminal CLR of the histogram memory 206a, the horizontal synchronization signal HD is inputted from the AND circuit 207a as the clear signal.

(129) The data values (histogram values) written in the addresses 0 to 7 in the histogram memory 206a are cleared to 0 by the clear signal at each rising edge of the horizontal synchronization signal HD as illustrated in (g) of FIG. 5.

(130) The data values written in the addresses 0 to 7 in the histogram memory 206a are therefore 0 at first.

(131) As illustrated in (k) of FIG. 5, the data values read from read addresses 2, 5, and 3 corresponding to the first three input pixel values are “0”.

(132) As illustrated in (m) of FIG. 5, the data values “0” in the addresses 2, 5, and 3 are added with “1”, and the results of addition “1” are written to the addresses 2, 5, and 3 in the histogram memory 206a.

(133) The data value read from the read address 2 corresponding to the subsequent fourth pixel value is “1” previously written and is then added with “1”. The result of addition “2” is overwritten to the address 2.

(134) After data of all the pixels of the line is inputted, therefore, the data value written to the address 2 is “3”, the data values written to the addresses 3 and 5 are “2”, the data value written to the address 7 is “1”, and the data values written to the other addresses 0, 1, 4, and 6 are “0” as illustrated in (n) of FIG. 5.

(135) The histogram memory 206a therefore stores histogram values HISTD_Q which are frequencies of respective gray levels of eight pixels of each odd-numbered line. In the histogram memory 206a, the addresses represent the gray levels, and the data values written to the addresses are frequencies of the respective gray levels.

(136) The histogram memory 206a thus generates the histogram values HISTD_ODD of respective gray levels of the input image data of each odd-numbered line when the determination signal LINE is 1.

(137) Subsequently, during each even-numbered line image data input period when the determination signal L is 0, by the same operation as that of the histogram memory 206a described above, the histogram memory 206b generates the histogram values HISTD_EVEN of respective gray levels of the input image data of an even-numbered line.

(138) At the same time, since the histogram memory 206a is not supplied with the write enable signal of 1, the histogram memory 206a performs only reading operation and correct load variation using the histogram values HISTD_ODD stored in the previous odd-numbered line image data input period.

(139) During each even-numbered line image data input period, the switch 209a is switched and connected to a terminal 0. Accordingly, the terminal RADRS of the histogram memory 206a is supplied with the counter value AC illustrated in (e) of FIG. 5 through the switch 209a as the read address as illustrated in (j) and (f) of FIG. 5.

(140) The histogram memory 206a thereby uses the counter value AC, which counts in increments of 1, as the read address and the horizontal synchronization signal as the reset. As illustrated in (k) of FIG. 5, the histogram memory 206a sequentially outputs the histogram values HISTD_ODD stored during the odd-numbered line image data input period illustrated in (n) of FIG. 5.

(141) The histogram values HISTD_ODD of the gray levels “2”, “3”, “5”, and “7” read from the addresses 2, 3, 5, and 7 are 3, 2, 2, and 1, respectively. Moreover, the histogram values HISTD_ODD of the other gray levels “0”, “1”, “4”, and “6” are 0.

(142) The histogram values are delayed by one line. Accordingly, the image data of the odd-numbered line corresponding to the above period is delayed by one line and outputted from the data memory 205a as ID_ODD.

(143) To the terminal INDATA of the odd-numbered line accumulator 210a, the histogram values HISTD_ODD of the gray levels of each odd-numbered line read from the histogram memory 206a (illustrated in (k) of FIG. 5) are inputted. The odd-numbered line accumulator 210a accumulates the histogram values HISTD_ODD and outputs cumulative sums HISTADD_ODD illustrated in (o) of FIG. 5 from a terminal EXDATA.

(144) Each cumulative sum HISTADD_ODD is the number s of analog switches which are turned off at the current time.

(145) The gray levels (data levels) of input image data ID(11) during the odd-numbered line image data input period, histogram values HISTD_ODD, and cumulative sums HISTADD_ODD which are described above are summarized as illustrated in FIG. 6.

(146) During the image data input period of each even-numbered line, the same operation as that during each odd-numbered line image data input period is performed by the even-numbered line ramp signal data generator 201B. This operation is only shifted from the operation for the odd-numbered lines by the period 1H and can be easily known. The detailed description thereof is omitted.

(147) The histogram memory 206b outputs the even-numbered line histogram values HISTD_EVEN, and the even-numbered line accumulator 210b outputs cumulative sums HISTADD_EVEN which indicate the number s of analog switches turned off at the process for each even-numbered line.

(148) When the ramp signal is configured to change in level from the value corresponding to the lowest gray level to the value corresponding to the highest gray level value in each period 1H, the histogram memories 206a and 206b output histogram values in ascending order of gray levels in synchronization with the horizontal synchronization signal.

(149) On the contrary, when the ramp signal has a waveform changing in level from the value corresponding to the highest gray level to the value corresponding to the lowest gray level value in the period 1H, the histogram memories 206a and 206b output histogram values in descending order of gray levels in synchronization with the horizontal synchronization signal.

(150) In the following description, the ramp signal has the former waveform.

(151) When the determination signal LINE supplied to a select terminal SEL is 0, the histogram value selector 212 illustrated in FIG. 3 selects the odd-numbered line cumulative sums HISTADD_ODD which are outputted from the odd-numbered line accumulator 210a and are supplied to a terminal A and outputs the same as the histogram value data HISTD as schematically illustrated in (p) of FIG. 5.

(152) During this period, the image data selector 211 outputs image data ID_ODD of the same odd-numbered line as schematically illustrated in (q) of FIG. 5.

(153) When the determination signal LINE supplied to the select terminal SEL is 1, the histogram value selector 212 selects the even-numbered line cumulative sums HISTADD_EVEN which are outputted from the even-numbered line accumulator 210b and are supplied to a terminal B and outputs the same as the histogram value data HISTD.

(154) The ramp signal data generator 213 illustrated in FIG. 3 is supplied with the histogram value data HISTD selected and outputted from the histogram value selector 212, the clock CLK, and the horizontal synchronization signal HD.

(155) The ramp signal data generator 213 generates ramp signal data VREFD of digital values. The ramp signal is a sawtooth wave changing in level from the value corresponding to the minimum gray level at the beginning of the period ID to the maximum gray level right before the end of the period 1H. Moreover, the ramp wave has a non-linear slope variably controlled in accordance with the cumulative sums.

(156) The DA converter 214 includes a buffer and converts the ramp signal data VREFD (digital signal) to the ramp signal VREF (analog signal) based on the clock CLK. The DA converter 214 supplies the ramp signal VREF to the analog switches 107.sub.1 to 107.sub.n through the ramp signal line Ls illustrated in FIG. 1A.

(157) The ramp signal data generator 213 generates the digital ramp signal data VREFD having a non-linear slope variably controlled in accordance with the cumulative sums. The conversion analog signal generator 101 thereby reduces voltage fluctuation of the ramp signal due to load variation dynamically caused by the output impedance of the DA converter 214 and the input impedance represented by the analog switches 107.sub.1 to 107.sub.n.

(158) The reduction of the changes in voltage of the ramp signal is concretely described below. The equivalent circuit of the circuit section including the DA converter 214 and analog switches 107.sub.1 to 107.sub.n is illustrated in FIG. 16 in a similar manner to the conventional one. Herein, the load variation rate is expressed by the following equation:
Load variation rate=V.sub.1(s)/V.sub.0=Z.sub.1/{(n−s)Z.sub.0+Z.sub.1}  (2)
where Z.sub.1 is the input impedance of each analog switch 107.sub.1 to 107.sub.n illustrated in FIG. 1A and s is the number of analog switches which are turned off to display the input gray level.

(159) In Equation (2), 0<=s<=n, and V.sub.0 is output voltage of the buffer of the DA converter 214. V.sub.1(s) is ramp signal voltage supplied from the DA converter 214 through the ramp signal line Ls to the n analog switches.

(160) FIG. 7 illustrates a graph of an example of the relationship between load variation rate and the number s of off analog switches. The load variation rate expressed by Equation (2) changes non-linearly to the number s of off analog switches as illustrated in FIG. 7 where Z.sub.0=1, Z.sub.1=100, and the total number n of analog switches=256.

(161) The smaller the number s of off analog switches, the lower the load variation rate. The aforementioned parameters are set for easy visual understanding and may be different from the actual parameters.

(162) The load variation rate illustrated in FIG. 7 changes non-linearly to the number s of off analog switches.

(163) The ramp signal data generator 213 in the image display apparatus 100 generates the ramp signal data VREFD by multiplying the ramp signal by load variation correction data corresponding to the load variation rate (illustrated in FIG. 8) depending on the number s of off analog switches. The number s is the cumulative sum (the histogram value) of the number of target pixels carrying each gray level and is obtained from the histogram memories 206a and 206b.

(164) The ramp signal data VREFD is digital data, and when the ramp signal data VREFD is converted into the ramp signal VREF having an analog waveform, the ramp signal VREF is variably controlled in accordance with the histogram values and has a non-linear slope.

(165) The load variation correction data illustrated in FIG. 8 is calculated by Equation (3), for example.
Load Variation Correction Data={(n−s)Z.sub.0+Z.sub.1}/Z.sub.1   (3)

(166) The load variation correction data is the reciprocal of the load variation rate expressed by Equation (2). The load variation correction data only needs to include data values allowing correction based on the load variation and is not limited to Equation (3).

(167) In accordance with the image display apparatus 100 according to the embodiment, the aforementioned operation reduces grayscale degradation due to voltage fluctuation of the ramp signal VREF which is caused by load variation of the ramp signal data generator 213 that dynamically changes depending on the number of pixels carrying each gray level in each line of the display digital video signal.

(168) Next, a description is given of the operation to generate the ramp signal data VREFD with the load variation of the ramp signal data generator 213 corrected more specifically in more detail with reference to FIGS. 9, 10A, 10B, 11A, and 11B.

(169) As illustrated in FIG. 9, it is assumed that the image display apparatus 100 displays an image including a 50% gray box (an image 2c) and a 50% gray box (an image 3c) which are arranged side by side in vertical direction on an image 1c which is a black background. The box of the image 2c includes 64 pixels in the horizontal direction. The box of the image 3c includes 128 pixels in the horizontal direction. The total number n of pixels in the horizontal direction is 256.

(170) In FIG. 9, the 50% gray images 2a and 3a are illustrated in white. The image illustrated in FIG. 9 is the same image as the original image illustrated in FIG. 15A.

(171) FIGS. 10A, 10B, and 10C illustrate the load variation rate F at displaying the images 1c, 2c, and 3c by the relationship between the counter value QD and input voltage V.sub.1, respectively. FIGS. 11A, 11B, and 11C illustrate the slope of the ramp signal data VREFD at displaying the images 1c, 2c, and 3c by the relationship between the counter value QD and input voltage V.sub.1.

(172) The counter value QD represented by the horizontal axes in FIGS. 10A to 10C and 11A to 11C is outputted from the gray-level counter 105 of FIG. 1A and is increased from 0 to 255 corresponding to the number of pixels horizontally arranged (256 pixels) in increments of one in the period 1H in synchronization with the clock period.

(173) In the case of not performing load variation correction, the ramp signal data generator 213 generates a ramp signal having a triangle waveform with the 1H period. The ramp signal linearly changes with time from 0 V representing the black level as the minimum gray level (corresponding to 0% light transmittance of the liquid crystal layer) to 1 V representing the white level as the maximum gray level (corresponding to 100% light transmittance of the liquid crystal layer) in the period 1H, and the waveform thereof has a linear slope.

(174) In Equations (2) and (3), Z.sub.0=1, and Z.sub.1=100.

(175) In the process of displaying any one line of the image 1c as the black background, all of the 256 pixels horizontally arranged have a gray level of 0, and all of the 256 analog switches corresponding to all the pixels horizontally arranged are simultaneously turned off when the counter value QD is 0.

(176) The 256 analog switches then remain turned off during the period 1H in which the counter value QD changes to 255. The load variation rate F(255) in this process is 1 as illustrated in FIG. 10A (no load variation).

(177) Herein, the load variation rate F(255) is expressed by 100/{256−256}×1+100}. In the process of displaying any one line of the image 1C, there is no load variation, and the ramp signal data generator 213 generates the ramp signal data VREFD of a triangular waveform with the level linearly changing from 0 V to 1 V as the counter value QD changes as illustrated in FIG. 11A.

(178) Next, in the process of displaying a line of the 50% gray image 2c having a shorter horizontal width, among 256 pixels in the line, 64 pixels are 50% gray, and the remaining 192 pixels are of the same gray level as the black background.

(179) Accordingly, when the counter value QD is 0 just after the beginning of the horizontal scanning period, the 192 analog switches corresponding to the 192 pixels of the same gray level as the black background are simultaneously turned off, and the 64 analog switches corresponding to the 64 pixels remain turned on.

(180) When the counter value QD becomes 128 indicating the gray level of 50%, the counter value QD matches pixel values of 50%. Upon the matching pulses outputted from the comparators 106.sub.1 to 106.sub.n, the remaining 64 analog switches are turned off, and 0.5 V of the ramp signal (the triangular waveform), that indicates the gray level of 50%, is sampled just before the analog switches are turned off. All the 256 analog switches are turned off at this time.

(181) Accordingly, in the process of displaying the image 2c, as illustrated in FIG. 10B, the load variation rate F(192) is 0.610 (=100/{256−192}×1+100) by Equation (2) in the period when the counter value QD is 0 to 127 and is 1 when the counter value QD is 128 to 255.

(182) In FIG. 10B, the load variation rate F shows a non-linear line which has a slope of 0.610 in a range of the counter value QD from 0 to 127 and has a slope of 1 in a range of the counter value QD from 128 to 255.

(183) Accordingly, the ramp signal data generator 213 generates a load variation correction value H for correcting the load variation rate F(192) using Equation (3) and generates the ramp signal data VREFD having a slope changing as indicated by I in FIG. 11B in accordance with the counter value QD.

(184) When the counter value QD is from 128 to 255, the load variation rate F(255) is 1. Accordingly, the slope of the ramp signal data VREFD is 1 as indicated by II in FIG. 11B.

(185) The ramp signal data generator 213 thus generates the ramp signal data VREFD having a non-liner slope illustrated in FIG. 11B.

(186) Next, in the process of displaying each line of the 50% gray image 3c having a larger horizontal width, among 256 pixels in the line, 128 pixels are 50% gray, and the remaining 128 pixels are of the same gray level as the black background.

(187) Accordingly, when the counter value QD is 0 just after the beginning of the horizontal scanning period, the 128 analog switches corresponding to the 128 pixels of the same gray level as the black background are simultaneously turned off, and the 128 analog switches corresponding to the other 128 pixels remain turned on.

(188) When the counter value QD becomes 128 corresponding to a gray level of 50%, the counter value QD matches pixel values of 50%. Upon the matching pulses outputted from the comparators 106.sub.1 to 106.sub.n, the remaining 128 analog switches are turned off, and 0.5 V of the ramp signal (the triangular waveform) that indicates a gray level of 50%, is sampled just before the analog switches are turned off. All the 256 analog switches are turned off at this time.

(189) Accordingly, in the process of displaying the image 3c, as illustrated in FIG. 10C, the load variation rate F(128) is 0.439 (=100/{256−128}×1+100) by Equation (2) in the period when the counter value QD is 0 to 127 and is 1 when the counter value QD is 128 to 255.

(190) In FIG. 10C, the load variation rate F shows a non-linear line having a slope of 0.439 in a range of the counter value QD i from 0 to 127 and has a slope of 1 in a range of the counter value QD from 128 to 255.

(191) Accordingly, the ramp signal data generator 213 generates the load variation correction value H for correcting the load variation rate F(192) using Equation (3) and generates the ramp signal data VREFD having a slope changing as indicated by III in FIG. 11C as the counter value QD changes.

(192) When the counter value QD is from 128 to 255, the load variation rate F(255) is 1. Accordingly, the ramp signal data VREFD has a slope of 1 as indicated by IV in FIG. 11C.

(193) The ramp signal data generator 213 thus generates the ramp signal data VREFD having a non-liner slope illustrated in FIG. 11C. The slope in the part indicated by I in FIG. 11B is different from that of the slope in the part indicated by III of FIG. 11C.

(194) In the embodiment, the ramp signal is generated based on the ramp signal data VREFD by correcting the load variation. Accordingly, compared with the conventional images 2b and 3b in the display image of FIG. 15B, the displayed images of the images 2c and 3c obtained by sampling and holding the ramp signal VREF include less degradation in tonality and can be displayed in nearly original 50% gray.

(195) Next, a description is given of specific configuration examples of the ramp signal data generator 213 illustrated in FIG. 3.

(196) (First Configuration Example of Ramp Signal Generating Section)

(197) FIG. 12 is a block diagram of a first configuration example of the ramp signal data generator 213. A ramp signal data generator 213A of the first configuration example illustrated in FIG. 12 includes a counter 301 and a data generator 302. The counter 301 counts up or down the pulses of the clock CLK. The counter 301 is reset by the horizontal synchronization signal HD to generate counter values representing the minimum through maximum gray levels in each horizontal scanning period.

(198) The clock CLK is the clock illustrated in (e) of FIG. 2 and (f) of FIG. 4. The counter 301 outputs a counter value QD (a second counter value) synchronized with the counter value QD (a first counter value) outputted from the gray-level counter 105 illustrated in FIG. 1A.

(199) The data generator 302 receives the histogram value data HISTD outputted from the histogram value selector 212 illustrated in FIG. 3 and the counter value QD of the counter 301 as an address. The data generator 302 outputs the ramp signal data VREFD as digital signal corresponding to the histogram value data HISTD and counter value QD.

(200) The data generator 302 can be composed of a look-up table (LUT). The histogram value data HISTD inputted as an address represents the number s of off analog switches for each value of the counter value QD. The data generator 302 can therefore generate the ramp signal data VREFD of a triangle wave having slope characteristics with the load variation corrected.

(201) The data generator 302 stores ramp signal data (LUT data) including at least one of the following features: correction of the triangle waveform represented by the counter value QD; execution of de-gamma for display digital video signal; and to correction of the voltage-transmittance characteristics (VT characteristics) of liquid crystal elements.

(202) The data generator 302 supplies the generated ramp signal data VREFD to the DA converter 214 illustrated in FIG. 3.

(203) When the load variation rate illustrated in FIG. 7 has a non-linear characteristic in particular and the load variation rate steeply rises, tonal steps are seen on the display image. The ramp signal data generator 213A of the first configuration example is suitably used when the tonal steps seen in the image are too noticeable to be acceptable.

(204) The ramp signal data generator 213A of the first configuration example is optimal for the case where the ramp signal needs to have non-linearity for degamma of the display digital video signal among monotonically increasing functions instead of using the gray level data constituting a simple triangle wave and the case where the VT characteristics of liquid crystal elements need to be corrected all at once.

(205) Even when the analog switches 107.sub.1 to 107.sub.n vary in impedance and serve as a buffer load non-linear to the histogram values, the ramp signal data generator 213A of the first configuration example is adaptable to various cases by designing the LUT data to fit to the load characteristics of the analog switches 107.sub.1 to 107.sub.n.

(206) The ramp signal data generator 213A can effectively prevent tonality degradation.

(207) (Second Configuration Example of Ramp Signal Generating Section)

(208) FIG. 13 illustrates a block diagram of a second configuration example of the ramp signal data generator 213. In FIG. 13, the same constituent portions as those of FIG. 12 are given the same reference numerals. A ramp signal data generator 213B of the second configuration example illustrated in FIG. 13 includes a multiplier instead of the data generator 302 in FIG. 12 and further includes a load variation correction data generator 303.

(209) The load variation correction data generator 303 is composed of an LUT, for example. The load variation correction data generator 303 receives the histogram value data HISTD as an address. The load variation correction data generator 303 generates the load variation correction data having the characteristics illustrated in FIG. 8 and supplies the generated data to the multiplier 304.

(210) The LUT constituting the load variation correction data generator 303 outputs the load variation correction data having data values corresponding to the number s of off analog switches indicated by the histogram value data HISTD inputted as the address.

(211) The multiplier 304 multiplies the counter value QD from the counter 301 (the multiplied value) by the load variation correction data (the multiplying value) and supplies the result of multiplication to the DA converter 214 (FIG. 3) as the ramp signal data VREFD.

(212) The ramp signal data VREFD represents a digital ramp signal of a sawtooth wave changing in level from a value corresponding to the minimum gray level at the beginning of each period 1H and having a value corresponding to the maximum gray level just before the end of the period 1H and has a non-linear slope variably controlled in accordance with the histogram value data HISTD.

(213) The ramp signal data generator 213B of the second configuration example is effective when the number n of pixels horizontally arranged is not large and when the output impedance Z.sub.0 of the buffer within the DA converter 214 is small enough compared with the input impedance Z.sub.1 of the analog switches 107.sub.k to 107.sub.n (Z.sub.0<<Z.sub.1).

(214) Moreover, since the ramp signal data generator 213B generates the ramp signal data VREFD using the multiplier 304 instead of the LUT, the ramp signal data generator 213B has a simple configuration and can provide the effect of reducing the load variation at a low cost.

(215) (Third Configuration Example of Ramp Signal Generating Section)

(216) FIG. 14 illustrates a block diagram of a third configuration example of the ramp signal data generator 213. In FIG. 14, the same constituent portions as those of FIG. 13 are given the same reference numerals.

(217) A ramp signal data generator 213C illustrated in FIG. 14 is composed of a combination of the ramp signal data generators 213A and 213B. The ramp signal data generator 213C multiplies the LUT data outputted from the data generator 305 by the load variation correction data outputted from the load variation correction data generator 303, through the multiplier 306.

(218) The data generator 305 is composed of an LUT. The data generator 305 receives the counter value QD from the counter 301 as an address. The data generator 305 stores LUT data (correction data) for performing degamma processing for display digital video signal or correcting the VT characteristics of liquid crystal elements.

(219) The multiplier 306 multiplies the LUT data from the data generator 305 (multiplied value) by the load variation correction data (multiplying value) and supplies the result of multiplication to the DA converter 214 (FIG. 3) as the ramp signal data VREFD.

(220) The ramp signal data generator 213C is effective for the case of correcting the VT characteristic of liquid crystal elements, the case of performing degamma, and the case where the load variation is considered to be substantially linear to the number s of off analog switches.

(221) The correction of the VT characteristic of liquid crystal elements and correction by degamma processing are generally non-linear to the grayscale. The ramp signal data generator 213C is effective in the case of requiring correction parameters and the case of properly changing the correction value (the degamma characteristic) for cancelling the signal gamma value that varies on video contents, such as 2.2, 1.8, and 2.6. An example of the correction parameters is a correction parameter concerning variation in liquid crystal film thickness in the manufacturing process. The liquid crystal film thickness varies between display elements.

(222) The ramp signal data generator 213C performs the aforementioned correction in the data generator 305 and multiplies the LUT data outputted from the data generator 305 by the load variation correction data through the subsequent multiplier 306, thereby reducing the load variation.

(223) According to the aforementioned configuration of the ramp signal data generator 213C, the memory size for the LUT can be significantly reduced, thereby reducing the cost and size of the image display apparatus.

(224) According to the image display apparatus 100 of the embodiment described above, in an image display apparatus using a ramp signal for DA conversion, it is possible to precisely reduce the tonality degradation (waveform interference) due to voltage fluctuation in the ramp signal VREF which is caused by the load variation of the ramp signal data generator 213 dynamically changing in each line of the digital video signal for the display.

(225) According to the image display apparatus 100 of the embodiment, by controlling the effect of reducing the tonality degradation in accordance with variation in analog switch characteristics of display elements, it is possible to implement high quality display excellent in tonality.

(226) According to the image display apparatus 100 of the embodiment, it is not necessary to provide dummy pixels in the pixels. It is therefore possible to avoid yield reduction due to an increase in circuit scale and suppress an increase in cost.

(227) The present invention is not limited to the above-described embodiment and can be modified in various ways. For example, the ramp signal may be composed of a sawtooth wave changing in level from the value corresponding to the maximum gray level to the value corresponding to the minimum gray level in each horizontal scanning period.

(228) In this case, the counter value needs to be counted down from the value corresponding to the maximum gray level to the value corresponding to the minimum gray level.

(229) As described above, according to the image display apparatus of the embodiment, it is possible to prevent tonality degradation (waveform interference) without providing dummy pixels and implement high-quality display with excellent tonality.

(230) The present invention is applicable to an image display apparatus using other display elements similar to the liquid crystal display elements. The present invention is applicable to every image display apparatus that performs image display using DA conversion.