Method for increasing the integration level of superconducting electronics circuits, and a resulting circuit

Abstract

A method for increasing the integration level of superconducting electronic circuits, comprising fabricating a series of planarized electrically conductive layers patterned into wiring, separated by planarized insulating layers, with vias communicating between the conductive layers. Contrary to the standard sequence of patterning from the bottom up, the pattern of vias in at least one insulating layer is formed prior to the pattern of wiring in the underlying conductive layer. This enables a reduction in the number of planarization steps, leading to a fabrication process which is faster and more reliable. In a preferred embodiment, the superconductor is niobium and the insulator is silicon dioxide. This method can provide 10 or more wiring layers in a complex integrated circuit, and is compatible with non-planarized circuits placed above the planarized wiring layers.

Claims

1. A planarized integrated circuit on a substrate, comprising: a series of planarized layers comprising at least two layers, formed successively on the substrate, each respective layer comprising: an electrically conductive via layer, patterned into a set of vias which define a set of vertically extending structures which electrically interconnect with conductive structures of an adjacent layer; an electrically conductive layer, formed by deposition over, and adjacent to, the electrically conductive via layer patterned into the set of vias, the electrically conductive layer-being patterned into a set of wires by removal of portions of the electrically conductive layer surrounding the set of wires, with the set of vertically extending structures extending above the set of wires which do not overly the set of vias; a first insulating layer formed over the electrically conductive via layer and the electrically conductive layer which is etched using an anisotropic etch process, to maintain a nonplanar raised Caldera pattern surrounding edges of the set of wires; and a second insulating layer formed over the set of wires and the set of vias, formed over the first insulating layer having the maintained raised Caldera pattern surrounding edges of the set of wires, to produce a conformal coating, which is etched using an anisotropic etch process, to maintain conformally coated raised Caldera pattern surrounding edges of the set of wires, and raised Caldera pattern surrounding edges of the set of vias, the second insulating layer being planarized to expose upper portions of the set of vertically extending structures, and remove the conformally coated raised Caldera pattern surrounding edges of the set of wires and the raised Caldera pattern surrounding edges of the set of vias, wherein the conformally coated raised Caldera pattern is independent of the set of vertically extending structures, wherein the electrically conductive layer, electrically conductive via layer, first insulating layer and second planarized insulating layer being formed as a four layer stack which is planarized once, such that upper portions of the set of vertically extending structures are exposed through the planarized second insulating layer, and wherein the electrically conductive via layer of a respective planarized layer is formed over exposed upper portions of the set of vertically extending structures of a respectively lower planarized layer.

2. The integrated circuit of claim 1, wherein at least one of the electrically conductive layer and the electrically conductive via layer comprises a niobium-based superconductive material.

3. The integrated circuit of claim 1, wherein the insulating layer comprises silicon dioxide.

4. The integrated circuit of claim 1, further comprising at least one non-planarized circuit layer lying above at least one planarized layer.

5. The integrated circuit of claim 1, further comprising at least one Josephson junction formed within a planarized layer, electrically connected to the set of wires.

6. The integrated circuit of claim 1, further comprising a single-flux-quantum circuit formed having a Josephson junction within a planarized layer, electrically connected to the set of wires.

7. The integrated circuit of claim 1, wherein a minimum transverse dimension of a conductive wire is less than 1 micron.

8. The integrated circuit of claim 1, wherein at least one conductive layer comprises a ground plane.

9. The superconducting integrated circuit of claim 1, wherein at least 10 planarized layers are present.

10. The planarized integrated circuit of claim 1, wherein the raised Caldera pattern surrounding edges of the set of vias is formed by a complementary-to-the-metal-mask pattern mask biased for misalignment compensation, and reactive ion etching.

11. The planarized integrated circuit of claim 10, wherein the electrically conductive layer and the electrically conductive via layer are each formed of a cryogenically superconductive material.

12. A planarized integrated circuit on a substrate, comprising a series of successive planarized sets of layers, at least one planarized set of layers comprising: an electrically conductive via layer patterned into a set of vias having via edges, formed on a planar surface; a patterned electrically conductive layer formed into a set of wires having wire edges, superposed on the patterned electrically conductive via layer, wherein portions where the set of wires which coincide in a plane of the planarized set of layers with the set of vias, define vertically extending conductive structures configured to provide a conductive path between the set of wires of the respective layer and a set of wires of an adjacent layer; a first insulating sublayer conformally surrounding the set of wires and the set of vias, which is anisotropically etched to produce a raised pattern having first protrusions corresponding to the wire edges; and a second insulating sublayer, deposited over the first insulating sublayer, having a raised pattern comprising second protrusions corresponding to the first protrusions, and the set of vias, which is anisotropically etched to produce a modified raised pattern having third protrusions corresponding to the via edges, and the second protrusions, the second insulating sublayer being planarized after the anisotropic etch, such that portions of the vertically extending structures are exposed at an upper surface of the planarized second insulating sublayer, and edges of the planarized second insulating sublayer around the exposed portions of the vertically extending structures, comprise planarized Caldera edges, and portions of the set of wires not superposed on the set of vias are covered by the first insulating sublayer and the second insulating sublayer.

13. The planarized integrated circuit of claim 12, wherein the electrically conductive via layer of a subsequent planarized set of layers is disposed on a planarized surface of a respective planarized second insulating sublayer of a preceding set of layers, formed by plasma-enhanced, chemical vapor deposition, in electrical contact with the exposed portions of the vertically extending structures of the preceding planarized set of layers.

14. The planarized integrated circuit of claim 12, wherein the planarized second insulating sublayer has a chemical-mechanical polishing planarized surface.

15. The planarized integrated circuit of claim 12, comprising at least 8 successive planarized sets of layers.

16. The planarized integrated circuit of claim 12, wherein at least one of the electrically conductive layer, and the electrically conductive via layer is a sputtered layer.

17. The planarized integrated circuit of claim 12, wherein at least one of the electrically conductive layer and the electrically conductive via layer has a reactive ion etching-formed pattern.

18. The planarized integrated circuit of claim 12, further comprising at least one Josephson junction formed within a planarized set of layers, electrically connected to the set of wires.

19. The planarized integrated circuit of claim 12, wherein the raised pattern having first protrusions is formed by a complementary-to-the-metal-mask pattern mask biased for misalignment compensation, and reactive ion etching.

20. The planarized integrated circuit of claim 19, wherein the electrically conductive layer and the electrically conductive via layer are each formed of a cryogenically superconductive material, without any intervening layer.

21. A planarized integrated circuit having a substrate, comprising at least one planarized layer formed on the substrate, the at least one planarized layer comprising: at least two layers of cryogenically superconductive material formed on a planar surface, comprising a wiring layer patterned to provide lateral conductive pathways in a plane of a respective layer, and a via layer patterned to provide vertically conductive pathways to an overlying layer, wherein the via layer of a respective planarized layer is patterned prior to superposition of the wiring layer of the respective planarized layer, such that a respective via of the respective planarized layer comprises a stack of the electrically conductive via layer and the superposed electrically conductive layer having a height above a surrounding portion of the wiring layer; and an insulating layer formed over the at least two layers of cryogenically superconductive material, comprising a first non-planarized, anisotropically etched, insulating sublayer covering the wiring layer and having a pattern of vertical protrusions corresponding to edges of the wiring layer, and a second anisotropically etched planarized insulating sublayer formed over the first non-planarized insulating layer, which is planarized to expose an upper portion of the stacks of electrically conductive via layer and the electrically conductive layer, and wherein an edge of the insulating layer surrounding the exposed upper portion of the stacks of electrically conductive via layer comprise planarized Caldera edges.

22. The planarized integrated circuit according to claim 21, wherein the electrically conductive via layer and the electrically conductive layer are each formed of a cryogenically superconducting material, without any layer therebetween, the integrated circuit further comprising a least two Josephson junctions electrically communicating through at least one wiring layer.

23. The planarized integrated circuit of claim 21, comprising at least 8 successive planarized layers.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 shows a First layer of the Prior Art Hypres Inc. process M0, sputter deposited, dark field mask lithography, SF.sub.6 RIE etched, chemically stripped. Moats and ground pad holes defined;

(2) FIG. 2 shows the Second layer of the Prior Art Hypres Inc. process I0, Ion Beam deposited, dark field mask lithography defining Vias between M1 and M0, etched in CH.sub.4+O.sub.2 mixture, chemically stripped;

(3) FIG. 3 shows the Third layer of the Prior Art Hypres Inc. process Tri-layer in situ sputter deposited Nb/Al/AlOx/Nb, I1C clear field mask lithography defining junctions hard baked photoresist, Anodization, chemically stripped;

(4) FIG. 4 shows the Fourth layer of the Prior Art Hypres Inc. process A1, Anodization ring definition, A1 clear field mask lithography defining Josephson Junctions, Ion Beam milled, chemically stripped;

(5) FIG. 5 shows the fifth layer of the Prior Art Hypres Inc. process M1, base electrode of the tri-layer. M1 clear field mask lithography defining inductances and interconnects by RIE, chemically stripped;

(6) FIG. 6 shows the sixth layer of the Prior Art Hypres Inc. process R2, Sputter deposited molybdenum, clear field mask lithography defining the shunt and bias resistors of the circuit, SF.sub.6 plasma etched, chemically stripped;

(7) FIG. 7 shows the seventh layer of the Prior Art Hypres Inc. process I1B-1 and I1B-2, PECVD deposited, I1B lithography dark field mask defining vias to Junction, resistors and contact pads, etched in CH4+O2 mixture, chemically stripped;

(8) FIG. 8 shows the Eighth layer of the Prior Art Hypres Inc. process M2, sputter deposited niobium, clear field mask lithography defining M2 inductors and interconnects, SF.sub.6 RIE etched, chemically stripped;

(9) FIG. 9 shows the ninth layer of the Prior Art Hypres Inc. process M2, PECVD deposited, dark field mask lithography defining vias to contact pad and M2 wiring, etched in CH4+O2 mixture, chemically stripped;

(10) FIG. 10 shows the tenth layer of the Prior Art Hypres Inc. process M3, sputter deposited niobium, clear field mask lithography defining M3 interconnects, SF.sub.6 RIE etched, chemically stripped;

(11) FIG. 11 shows the eleventh layer of the Prior Art Hypres Inc. process R3, Image reversal lithography using clear field mask defining R3, electron beam evaporated Ti/Pl/Au, Lift-off, chemically cleaned;

(12) FIG. 12 show a layout of a shunted Junction of the Prior Art Hypres Inc. process, connected to bias pad with a bias resistor and grounded through the base electrode of the junction;

(13) FIG. 13 shows the base technology level description of the RIPPLE-7 process according to the present invention, where Mn8 to M0 layers are planarized;

(14) FIGS. 14A and 14B show the xth Superconducting metal layer extension, after plug definition;

(15) FIGS. 15A and 15B show the Al wet etch, Pattern #2, Niobium metal RIE;

(16) FIGS. 16A and 16B show the First Interlayer dielectric (SiO.sub.2) deposition;

(17) FIGS. 17A and 17B show the removal of Interlayer dielectric by Reactive Ion Etch;

(18) FIGS. 18A and 18B show the Second ILD deposition;

(19) FIGS. 19A and 19B show the ILD Planarization by RIE SiO.sub.2 etch;

(20) FIGS. 20A and 20B show Chemical Mechanical Planarization;

(21) FIGS. 21A and 21B show an alternative method (using Anodization);

(22) FIG. 22 shows a prior art 4-layer metal process;

(23) FIG. 23 shows a planarized 6 metal layer process;

(24) FIG. 24 shows RIPPLE-8, a process with 12 superconducting layers, Shielded passive transmission lines, shielded DC power distributions;

(25) FIGS. 25A and 25B show schematic planarized layers according to the Prior Art; and

(26) FIGS. 26A, 26B and 26C show via plugs and underground superconducting wire defined without aluminum etch stop; 26A After the definition of the via-plug; 26B After the deposition of the metal layer; and 26C After the definition of the wiring layer.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

(27) 1.0 Prior Art Fabrication Process

(28) The details of a known Hypres Inc. (Elmsford N.Y.) the process flow will be described by following the cross-section of a biased, shunted Josephson junction as it made layer-by-layer. The layout of this is given in FIG. 12, which shows a layout of a shunted Junction connected to a bias pad with a bias resistor and grounded through the base electrode of the junction.

(29) The process starts with a bare 150 mm diameter oxidized silicon wafer by deposition the first Nb metal layer (M0). Of course, other substrates may be used. Typically, the substrate is planarized before the first step, and indeed, may be a planarized circuit formed from preceding manufacturing steps.

(30) The deposition is done in a cryo-pumped chamber to a pressure of about 10.sup.−7 Torr. Magnetron sputtering is used for deposition, where the wafer is scanned under the target at constant speed. Both the scan speed and the chamber pressure are adjusted to get the required film thickness growing without stress. At 3 kW power the wafer is scanned at 20 cm/sec to make a film of thickness 1000 Å for M0 at a stress-free chamber pressure of 17 mTorr. After deposition the Nb thin film is patterned using the M0-mask, a dark field mask and a positive photoresist AZ5214-E IR. The pattern is transferred to the thin film after etching it in end-point-detected SF.sub.6 plasma RIE. Following etching, the resist and etch by-products are stripped and cleared by wet processing. The final cross section after the completion of the first layer is given in FIG. 1 (The figure is to scale with nano-meter scale on the Y-axis and micro-meter scale on the X-axis), shows a First layer—M0, sputter deposited, dark field mask lithography, SF.sub.6 RIE etched, chemically stripped. Moats and ground pad holes are defined.

(31) The following describes the 11 layers of the standard Hypres Inc. (Elmsford N.Y.) legacy (non-planarized) fabrication process, according to a preferred embodiment:

(32) 1.1 M0—the First Niobium Superconductor Layer

(33) The first Niobium superconductor layer is grown to a thickness of 1000 ű10% and the film's sheet resistance at room temperature is 1.90±0.2Ω/□. In a circuit this layer is used as grounding and most of the return current flows through it. To reduce the effect of ground current induced magnetic field interference to the operation of the circuit, a number of holes and moats are included in this layer. Holes and moats can have a minimum size of 2×2 μm and a bias (0.25±0.25) μm and a minimum spacing of 3 μm between them.

(34) 1.2 I0—Interlayer Dielectric Between M0 and M1

(35) FIG. 2 shows the Second layer I0—Ion Beam deposited, dark field mask lithography defining Vias between M1 and M0, etched in CH.sub.4+O.sub.2 mixture, chemically stripped.

(36) The interlayer dielectric between M0 and M1 is PECVD deposited SiO.sub.2 insulator of thickness 1500 ű10% with a specific capacitance of 0.277 fF/μm.sup.2±20%. Contact to M0 is through I0 vias with a minimum size of 2×2 μm and a bias (0.30±0.25) μm. The alignment tolerance of I0 to M0 is ±0.25 μm.

(37) 1.3 I1C—Niobium Superconductor Counter Electrode of the Tri-Layer

(38) FIG. 3 shows the Third layer—Tri-layer in situ sputter deposited Nb/Al/AlO.sub.x/Nb, I1C clear field mask lithography defining junctions hard baked photoresist, Anodization, chemically stripped.

(39) The Niobium superconductor counter electrode of the tri-layer is deposited by magnetron sputtering in a load locked, cryo-pumped chamber with a base pressure of 1×10.sup.−9 T. It is grown to a thickness of 500 ű10%. Junctions are defined in this layer by using a Clearfield mask I1C. The alignment tolerance of I1C to M0 and/or I0 is ±0.25 μm. After the counter electrode is etched in SF.sub.6 plasma, the wafer is anodized.

(40) 1.4 A1—Al.sub.2O.sub.3/Nb.sub.2O.sub.5 Double Layer

(41) FIG. 4 shows the Fourth layer—A1, Anodization ring definition, A1 clear field mask lithography defining Josephson Junctions, Ion Beam milled, chemically stripped.

(42) The A1—Al.sub.2O.sub.3/Nb.sub.2O.sub.5 double layer is grown by anodization after RIE of the base electrode by applying a constant voltage of about 28 mV and 700 mA initial current forming a double protecting layer of Al.sub.2O.sub.3 and Nb.sub.2O.sub.5. The thickness of the bi-layer is about 560 ű10%. After A1 definition the remaining bi-layer surrounds the Josephson junctions by about 0.5 μm. A1 is aligned to I1C with an alignment tolerance of ±0.25 μm.

(43) 1.5 M1—Niobium Superconductor Counter Electrode of the Tri-Layer

(44) FIG. 5 shows the fifth layer—M1, base electrode of the tri-layer. M1 clear field mask lithography defining inductances and interconnects by RIE, chemically stripped.

(45) The Niobium superconductor counter electrode of the tri-layer is deposited by magnetron sputtering in a load locked, cryo-pumped chamber with a base pressure of 1×10.sup.−9 T. It is grown to a thickness of 1500 ű10% and the film's sheet resistance at room temperature is 1.70±0.2Ω/□. Most circuit inductances are defined in this layer by micro-strip lines with M0 as ground plane and M2 for double ground plane. A specific inductance of 0.487±0.007 pH with a fringing factor of 0.54±0.13 μm. Minimum line width 2 μm and a bias (−0.30±0.25) μm. The alignment tolerance of M1 to M0 and/or I0 is ±0.25 μm.

(46) 1.6 R2—Molybdenum Resistor Material

(47) FIG. 6 shows the sixth layer R2, Sputter deposited molybdenum, clear field mask lithography defining the shunt and bias resistors of the circuit, SF.sub.6 plasma etched, chemically stripped.

(48) The Molybdenum resistor material is deposited by magnetron sputtering in a load locked; cryo-pumped chamber with a base pressure of 1×10.sup.−7 T right after the first part of the I1B1 dielectric is deposited. It is grown to a thickness of 750 ű10% and the film's sheet resistance at room temperature is 1.95±0.1Ω/□ and is reduced to 1.0±0.1Ω/□ at 4.2 K. Minimum line width allowed is 2 μm and a bias (−0.2±0.25) μm. This bias is corrected on the mask. Shunt and bias resistors are defined in this layer. The alignment tolerance of R2 to I1A is ±0.25 μm.

(49) 1.7 I1B—Interlayer Dielectric Between Tri-Layer and R2-I1B1; Tri-Layer and M2-I1B2

(50) FIG. 7 shows the seventh layer I1B-1 and I1B-2—PECVD deposited, I1B lithography dark field mask defining vias to Junction, resistors and contact pads, etched in CH.sub.4+O.sub.2 mixture, chemically stripped.

(51) I1B1 and I1B2 are PECVD deposited SiO.sub.2 insulator of thickness 2000 ű20% with a specific capacitance of 0.416 fF/μm.sup.2±20%. Contact to M1 and I1A is through I1B vias with a minimum size of 2 μm and a bias (0.20±0.25) μm. The alignment tolerance of I1B to I1A is ±0.1 μm.

(52) 1.8 M2—Niobium Superconductor Material

(53) FIG. 8 shows the Eighth layer—M2, sputter deposited niobium, clear field mask lithography defining M2 inductors and interconnects, SF.sub.6 RIE etched, chemically stripped.

(54) The Niobium superconductor material is deposited by magnetron sputtering in a load locked, cryo-pumped chamber with a base pressure of 1×10.sup.−7 T. It is grown to a thickness of 3000 ű10% and the film's sheet resistance at room temperature is 1.60Ω/□±10%. Minimum line width 2 μm and a minimum gap between lines of 2.5 μm and a bias of (−0.5±0.25) μm. The alignment tolerance of M2 to I1B is ±0.25 μm. This layer is mainly used for wiring, as an inductor with M0 as a ground plane and M3 for double ground plane. A specific inductance of 0.67±0.01 pH/□ and Josephson penetration and a fringing factor of 0.98±0.19 μm.

(55) 1.9 I2—Interlayer Dielectric Between M2 and M3

(56) FIG. 9 shows the ninth layer I2—PECVD deposited, dark field mask lithography defining vias to contact pad and M2 wiring, etched in CH.sub.4+O.sub.2 mixture, chemically stripped.

(57) The interlayer dielectric between M2 and M3 is PECVD deposited SiO.sub.2 insulator of thickness 5000 ű10% with a specific capacitance of 0.08 fF/μm.sup.2±20%. Contact to M2 is through I2 vias with a minimum size of 2×2 μm and a bias (0.20±0.25) μm. The alignment tolerance of I2 to M2 is ±0.25 μm.

(58) 1.10 M3—Niobium Superconductor Material

(59) FIG. 10 shows the tenth layer—M3, sputter deposited niobium, clear field mask lithography defining M3 interconnects, SF.sub.6 RIE etched, chemically stripped.

(60) The Niobium superconductor material layer is deposited by magnetron sputtering in a load locked, cryo-pumped chamber with a base pressure of 1×10.sup.−7 T. It is grown to a thickness of 6000 ű10% and the film's sheet resistance at room temperature is 0.60Ω/□±10%. Minimum line width 2 μm and a minimum gap between lines of 2.5 μm and a bias of (−0.75±0.25) μm. The alignment tolerance of M3 to I2 is ±0.5 μm. This layer is mainly used for wiring and as an inductor with M0 as a ground plane. A specific inductance of 1.26±0.02 pH/□ and a fringing factor of 1.9±0.1 μm.

(61) 1.11 R3—Titanium/Palladium/Gold (Ti/Pl/Au) Resistor Material

(62) FIG. 11 shows the eleventh layer—R3, Image reversal lithography using clear field mask defining R3, electron beam evaporated Ti/Pl/Au, Lift-off, chemically cleaned.

(63) The Titanium/Palladium/Gold (Ti/Pl/Au) resistor material is deposited by electron beam evaporation in a cryo-pumped chamber with a base pressure of 1×10.sup.−7 T. It is grown to a thickness of (300/1000/2000 Å)±10% and the film's sheet resistance at room temperature is 0.23±0.05Ω/□ and is reduced to 0.15±0.05Ω/□ at 4.2 K. Minimum line width 2 μm. Contact pads are defined in this layer. The alignment tolerance of R3 to M3 is ±0.5 μm.

(64) 2 Rapid Planarized Process for Layer Extension (RIPPLE)

(65) The RIPPLE process described below represents one embodiment of the new process for extending prior superconducting fabrication processes.

(66) The Acronym RIPPLE stands for:

(67) Rapid: One deposition and CMP less (˜20% less time per layer)

(68) Integrated: to the current standard process, by adding new wiring layers under the ground plane of the old 4-layer Process

(69) Planarization

(70) Process: Modified “Caldera” process (K. Hinode, et al., Physica C 412-414 (2004) 1437-1441)

(71) Layer

(72) Extension: Easily extendible 4+n, (n=2 has been successfully demonstrated)

(73) All the new superconducting metal layers labeled Mn1, Mn2, Mn3 . . . are placed below the ground plane of the current process—M0. The interconnect between the layers is done through Plugs labeled In1, In2, In3 . . . . The Mnx/Inx duo is deposited at one go with a thin layer of Aluminum separating them. Although Aluminum is not superconducting at 4.2 K, the sub-nanometer thickness renders it superconducting because of the proximity effect. Once the thin film deposition of the now three layers (Mnx—Al—Inx) is done and the both the Plug and superconducting metal layer are defined through a fabrication process that involves: photolithography and reactive ion etch of the Plug; wet chemical or ion beam milling of the Aluminum; photolithography and reactive ion etch of the superconducting metal layer. The respective interlayer dielectric are deposited and partially planarized by photolithography followed by reactive ion etch. By design the photolithography is done in such a way that it leaves a rim of dielectric (20 nm wide) on the perimeter of the superconducting metal and its plug. This insures a uniform dielectric roughness throughout enabling the next process to be pattern independent. The chemical mechanical polishing is thus pattern independent and hence very uniform across the entire wafer. The technology level based on the integration level is now as follows:

(74) 1) RIPPLE-0 A process where the M0 ground plane of the legacy process is planarized with 4 superconducting layers.

(75) 2) RIPPLE-1 A process where Mn1 to M0 layers are planarized with 5 superconducting metal layers.

(76) 3) RIPPLE-2 A process where Mn2 to M0 layers are planarized with 6 superconducting metal layers.

(77) 4) RIPPLE-4 A process where Mn4 to M0 layers are planarized with 8 superconducting metal layers.

(78) 5) RIPPLE-6 A process where Mn6 to M0 layers are planarized with 10 superconducting metal layers.

(79) 6) RIPPLE-8 A process where Mn8 to M0 layers are planarized with 12 superconducting metal layers

(80) A RIPPLE-7 process where Mn8 to M0 layers are planarized is illustrated in FIG. 13, which shows the base technology level description.

(81) 2.1 Advantages of Ripple

(82) 1) Rapid: It is estimated that it is 20% faster than a process that would could accomplish similar results by processing one layer at a time, for example CALDERA process. See, Fourie, Coenrad; Xizhu Peng; Takahashi, Akitomo; Yoshikawa, Nobuyuki, “Modeling and calibration of ADP process for inductance calculation with InductEx,” Superconductive Electronics Conference (ISEC), 2013 IEEE 14th International, vol., no., pp. 1.3, 7-11 Jul. 2013, doi: 10.1109/ISEC.2013.6604270, expressly incorporated herein by reference. This is because the superconducting wiring layer and the plug that connects it to the subsequent layer are processed in parallel.

(83) 2) Easily to implement and increase the integration level of superconducting electronic circuits. All the new layers are “underground layers” with no effect to the layers on the top. They are underground because they go under the M0 layer of the legacy process which is mainly used for grounding.

(84) 3) The Chemical Mechanical polishing part of the process has been optimized and made easy to implement by rendering it pattern independent.

(85) 4) Easily extendible, Since they same basic process is used to define all the underground layers, as a result it is easy to accommodate designs that require more layers.

(86) 5) It can be adopted to define self-aligned Josephson junctions

(87) 2.2 Ripple Process Details

(88) 2.2.1 Mnx/Inx—Superconducting Metal Layer and Plugs Deposition (Nb—Al—Nb)

(89) This is the first step in increasing the integration level of superconducting electronics circuits. The Niobium-Aluminum-Niobium trilayer is deposited by magnetron sputtering in a load locked, cryo-pumped chamber with a base pressure of 1×10.sup.−7 T. The Niobium metal layer are grown to a thickness of 2000 ű10% each with a 100 ű10% Aluminum in between. The film's sheet resistance at room temperature is 0.54Ω/□±10%. Minimum line width 0.8 μm and a minimum gap between lines of 0.5 μm and a bias of (−0.20±0.20) μm. This layer can be used for wiring interconnects, passive transmission lines and inductors.

(90) 2.2.1.1 Pattern Inx (“Plugs”), Reactive Ion Etch (Al as an Etch-Stop)

(91) FIGS. 14A and 14B show the x.sup.th Superconducting metal layer extension, after the plug definition.

(92) After deposition of the tri-layer, the first step is to pattern the Plug as illustrated in FIG. 14A, which is a 3D aerial view showing two of the defined Plugs, while FIG. 14B is a cross-sectional view zooming into one of the plugs. Etching of metal and dielectric is done in two Reactive Ion Etching (RIE) systems. The first one is an RIE system with fluorine based chemistries (SF.sub.6, CHF.sub.3, CF.sub.4) and the second one is an inductively-coupled plasma (ICP) etch system equipped with both flouring and chlorine-based chemistries (Cl.sub.2, BCl.sub.3). RIE is a preferred method of etching as it is very anisotropic with high selectivity. For niobium etch the most commonly used are fluorine-based plasmas, e.g., SF.sub.6 plasma. The typical etch parameter are an SF.sub.6 gas flowing at 20 sccm in a chamber pressurized to 2 Pascal and plasma sustained with an RF power of 45.

(93) 2.2.1.2 Al Removal (Wet Etch or Anodization/Mill)

(94) The next step is to remove the aluminum etch stop either by means of wet etch, anodization or milling.

(95) 2.2.2 Pattern #2—Mnx, Reactive Ion Etch

(96) FIGS. 15A and 15B show the Al wet etch, Pattern #2, Niobium metal RIE.

(97) Then photolithography is done to define the Mnx superconducting metal layer, as illustrated in FIG. 15A, shows a 3D aerial view showing two of the defined Mnx metals with their respective plugs while FIG. 15B shows a cross-sectional view. The reactive ion etch is done the same manner as the plug.

(98) 2.2.3 First Interlayer Dielectric (SiO.sub.2) Deposition (PECVD)

(99) FIGS. 16A and 16B show the First Interlayer dielectric (SiO2) deposition.

(100) Then SiO.sub.2 interlayer dielectric is a plasma enhanced chemical vapor deposition (PECVD) layer formed having a thickness equal to Mnx of 2000 ű10% with a specific capacitance of 0.24 fF/μm.sup.2±20%. The resulting profile is illustrated in FIG. 16A.

(101) 2.2.3.1 Pattern #2 (with 0.2-μm Bias) SiO.sub.2 Planarization (RIE)

(102) FIGS. 17A and 17B show the removal of Interlayer dielectric by Reactive Ion Etch.

(103) The respective interlayer dielectric are deposited and partially planarized by photolithography followed by reactive ion etch. By design the photolithography is done in such a way that it leaves a rim of dielectric (20 nm wide) on the perimeter of the superconducting metal and its plug. All dielectric layers are etched in a CHF.sub.3 and O.sub.2 plasma, 8 sccm of O.sub.2 and 45 sccm of CHF.sub.3 is flown into the chamber held at a pressure of 13.33 Pa. Etching is done at 150 W RF power and the temperature on the back of the wafer is kept controlled by a chiller set to about 11° C. The resulting cross section is shown in FIG. 17A.

(104) 2.2.4 SiO.sub.2 Deposition (PECVD)

(105) FIGS. 18A and 18B show the Second ILD deposition.

(106) Then SiO.sub.2 interlayer dielectric is plasma enhance chemical vapor deposited (PECVD) thickness equal to Inx of 2000 ű10% with a specific capacitance of 0.24 fF/μm.sup.2±20%. The resulting profile is illustrated in FIG. 18A.

(107) 2.2.4.1 Pattern #1 (with 0.2-μm Bias), SiO.sub.2 Planarization (RIE)

(108) FIGS. 19A and 19B show the ILD (interlayer dielectric) Planarization by RIE SiO.sub.2 etch.

(109) Then photolithography is done in the same manner as pattern #1, the reactive ion etch is done in the same manner as the pattern #1, resulting in features illustrated in FIG. 19A, which shows a 3D aerial view with two of the defined Mnx metals and their respective plugs while FIG. 19B shows a cross-sectional view.

(110) 2.2.5 SiO.sub.2 Planarization (CMP)

(111) FIGS. 20A and 20B show Chemical Mechanical Polishing Planarization. The final, but not the least step is one that takes care of the residual interlayer dielectric on the perimeter of the metals and the plugs by chemical mechanical polishing, resulting in a structure illustrated in FIGS. 21A and 21B, which w an alternative approach to Chemical Mechanical Polishing Planarization as shown in FIGS. 20A and 20B, of achieving the same planarized metal with a plug, but the only difference being the aluminum layer that is used as an etch stop is not removed instead is anodized and kept as part of the interlayer dielectric.

(112) FIG. 22 shows a prior art 4-layer metal process, which is not planarized, and thus has a varying topography between each layer.

(113) FIG. 23 shows a planarized 6 metal layer process, in which lower interconnection layers have planarized topography, while the upper layers above the ground plane (magnetic shielding layer between interconnect layers and Josephson junction trilayer) are non-planar.

(114) FIG. 24 shows a RIPPLE-8 process integrated circuit device having 12 superconducting layers (8 planarized and 4 non-planarized), shielded passive transmission lines, and shielded DC power distributions below the ground plane, and 4-layer traditional non-planarized active superconducting circuitry above the ground plane.

(115) FIG. 25A shows a simplified picture of a completed planarized conducting layer and insulating overlayer, with the patterned wiring and via labeled. A planarized intermediate structure according to the prior art is shown in FIG. 25B. According to the prior art, two planarization steps (produced by, e.g., CMP) are therefore required to produce FIG. 25A. In contrast, in the RIPPLE process as described, the intermediate structure of FIG. 25B is never present, but a final structure that is functionally equivalent to FIG. 25A is obtained using only a single planarization step (produced by CMP). This corresponds to a fabrication process that is faster and more reliable.

(116) 3. Alternative Embodiment of RIPPLE Process

(117) The RIPPLE process above starts with deposition of a Nb/Al/Nb trilayer, where the Al act as an etch stop. This, of course, requires later steps for the removal of this etch stop layer. An alternative embodiment of the process is also presented in FIGS. 26A, 26B, and 26C, without the need for such an etch stop or associated Al removal. The process starts with the deposition of a single 200 nm niobium thin film followed by via plugs patterning and definition (FIG. 26A). The next step is to deposit a second 200-nm thick niobium film by sputtering (FIG. 26B). During this step, the via-plugs will get coated conformally and grow together with the wiring layer. At this stage, the wiring layer is patterned and defined; the resulting structure is shown in FIG. 26C. Then 200 nm silicon dioxide (the same thickness as the wiring layer) is deposited, yielding the same structure as shown in FIGS. 16A and 16B, except for the aluminum. The rest of the process follows the RIPPLE steps described with respect to FIGS. 17-20. In this case also, only a single CMP step is needed for each wiring layer, including the via plug. This alternative embodiment may provide improved reliability and speed by skipping the aluminum etch step.

(118) These are representative examples of the RIPPLE process, and others are also possible. The key is to pattern the vias before the wiring, which requires only a single CMP step for each wiring bi-layer in a process that can be extended to an arbitrary number of such bi-layers with small stacked vias between them.

(119) The above description of illustrated embodiments is not intended to be exhaustive or to limit the embodiments to the precise forms disclosed. Although specific embodiments and examples are described herein for illustrative purposes, various equivalent modifications can be made without departing from the spirit and scope of the disclosure, as will be recognized by those skilled in the relevant art. The teachings provided herein of the various embodiments can be applied to other electronic systems, methods and apparatus, not necessarily the exemplary electronic systems, methods and apparatus generally described above.

(120) As will be apparent to those skilled in the art, the various embodiments described above can be combined to provide further embodiments. Aspects of the present systems, methods and apparatus can be modified, if necessary, to employ systems, methods, apparatus and concepts of the various patents, applications and publications to provide yet further embodiments of the invention. For example, the various systems, methods and apparatus may include a different number of metal or dielectric layers than set out in the illustrated embodiments, such as three or more metal layers and two or more insulating dielectric layers alternating with the metal layers, the layers may be disposed in a different order or area, or the embodiments may omit some elements, and/or employ additional elements.

(121) All of the U.S. patents, U.S. patent application publications, U.S. patent applications, referred to in this specification are incorporated herein by reference, in their entirety and for all purposes. Aspects of the embodiments can be modified, if necessary, to employ systems, circuits and concepts of the various patents, applications and publications to provide yet further embodiments.

(122) These and other changes can be made to the present systems, methods and apparatus in light of the above description. In general, in the following claims, the terms used should not be construed to limit the invention to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the invention is not limited by the disclosure, but instead its scope is to be determined entirely by the following claims.